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authorfabient <fabient@FreeBSD.org>2012-09-06 13:54:01 +0000
committerfabient <fabient@FreeBSD.org>2012-09-06 13:54:01 +0000
commit2a46ae3db5a3216c95ab197a89cbc84bffed9a12 (patch)
treed50b30c19763737203bcb55a18d846c64a23d2a8 /sys/dev/hwpmc/hwpmc_intel.c
parent825c974e400cd1d3d1048aa3d9ecb2ac62fc3e0c (diff)
downloadFreeBSD-src-2a46ae3db5a3216c95ab197a89cbc84bffed9a12.zip
FreeBSD-src-2a46ae3db5a3216c95ab197a89cbc84bffed9a12.tar.gz
Add Intel Ivy Bridge support to hwpmc(9).
Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
Diffstat (limited to 'sys/dev/hwpmc/hwpmc_intel.c')
-rw-r--r--sys/dev/hwpmc/hwpmc_intel.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/sys/dev/hwpmc/hwpmc_intel.c b/sys/dev/hwpmc/hwpmc_intel.c
index c21f5d9..6345522 100644
--- a/sys/dev/hwpmc/hwpmc_intel.c
+++ b/sys/dev/hwpmc/hwpmc_intel.c
@@ -146,6 +146,10 @@ pmc_intel_initialize(void)
cputype = PMC_CPU_INTEL_SANDYBRIDGE;
nclasses = 5;
break;
+ case 0x3A: /* Per Intel document 253669-043US 05/2012. */
+ cputype = PMC_CPU_INTEL_IVYBRIDGE;
+ nclasses = 3;
+ break;
}
break;
#if defined(__i386__) || defined(__amd64__)
@@ -184,6 +188,7 @@ pmc_intel_initialize(void)
case PMC_CPU_INTEL_CORE2:
case PMC_CPU_INTEL_CORE2EXTREME:
case PMC_CPU_INTEL_COREI7:
+ case PMC_CPU_INTEL_IVYBRIDGE:
case PMC_CPU_INTEL_SANDYBRIDGE:
case PMC_CPU_INTEL_WESTMERE:
error = pmc_core_initialize(pmc_mdep, ncpus);
@@ -266,6 +271,7 @@ pmc_intel_finalize(struct pmc_mdep *md)
case PMC_CPU_INTEL_CORE2:
case PMC_CPU_INTEL_CORE2EXTREME:
case PMC_CPU_INTEL_COREI7:
+ case PMC_CPU_INTEL_IVYBRIDGE:
case PMC_CPU_INTEL_SANDYBRIDGE:
case PMC_CPU_INTEL_WESTMERE:
pmc_core_finalize(md);
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