- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo

  and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and
  model 0x1C (Atom).

  In these CPUs, the actual numbers, kinds and widths of PMCs present
  need to queried at run time.  Support for specific "architectural"
  events also needs to be queried at run time.

  Model 0xE CPUs support programmable PMCs, subsequent CPUs
  additionally support "fixed-function" counters.

- Use event names that are close to vendor documentation, taking in
  account that:
  - events with identical semantics on two or more CPUs in this family
    can have differing names in vendor documentation,
  - identical vendor event names may map to differing events across
    CPUs,
  - each type of CPU supports a different subset of measurable
    events.

  Fixed-function and programmable counters both use the same vendor
  names for events.  The use of a class name prefix ("iaf-" or
  "iap-" respectively) permits these to be distinguished.

- In libpmc, refactor pmc_name_of_event() into a public interface
  and an internal helper function, for use by log handling code.

- Minor code tweaks: staticize a global, freshen a few comments.

Tested by:	gnn

1 files changed, 37 insertions, 5 deletions

diff --git a/sys/dev/hwpmc/hwpmc_intel.c b/sys/dev/hwpmc/hwpmc_intel.c
index 80916c6..7532559 100644
--- a/sys/dev/hwpmc/hwpmc_intel.c
+++ b/sys/dev/hwpmc/hwpmc_intel.c
@@ -88,20 +88,24 @@ pmc_intel_initialize(void)
 	cputype = -1;
 	nclasses = 2;
 
+	model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4);
+
 	switch (cpu_id & 0xF00) {
 #if	defined(__i386__)
 	case 0x500:		/* Pentium family processors */
 		cputype = PMC_CPU_INTEL_P5;
 		break;
+#endif
 	case 0x600:		/* Pentium Pro, Celeron, Pentium II & III */
-		switch ((cpu_id & 0xF0) >> 4) { /* model number field */
+		switch (model) {
+#if	defined(__i386__)
 		case 0x1:
 			cputype = PMC_CPU_INTEL_P6;
 			break;
 		case 0x3: case 0x5:
 			cputype = PMC_CPU_INTEL_PII;
 			break;
-		case 0x6:
+		case 0x6: case 0x16:
 			cputype = PMC_CPU_INTEL_CL;
 			break;
 		case 0x7: case 0x8: case 0xA: case 0xB:
@@ -110,12 +114,26 @@ pmc_intel_initialize(void)
 		case 0x9: case 0xD:
 			cputype = PMC_CPU_INTEL_PM;
 			break;
+#endif
+		case 0xE:
+			cputype = PMC_CPU_INTEL_CORE;
+			break;
+		case 0xF:
+			cputype = PMC_CPU_INTEL_CORE2;
+			nclasses = 3;
+			break;
+		case 0x17:
+			cputype = PMC_CPU_INTEL_CORE2EXTREME;
+			nclasses = 3;
+			break;
+		case 0x1C:	/* Per Intel document 320047-002. */
+			cputype = PMC_CPU_INTEL_ATOM;
+			nclasses = 3;
+			break;
 		}
 		break;
-#endif
 #if	defined(__i386__) || defined(__amd64__)
 	case 0xF00:		/* P4 */
-		model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4);
 		if (model >= 0 && model <= 6) /* known models */
 			cputype = PMC_CPU_INTEL_PIV;
 		break;
@@ -144,6 +162,14 @@ pmc_intel_initialize(void)
 
 	switch (cputype) {
 #if	defined(__i386__) || defined(__amd64__)
+		/*
+		 * Intel Core, Core 2 and Atom processors.
+		 */
+	case PMC_CPU_INTEL_ATOM:
+	case PMC_CPU_INTEL_CORE:
+	case PMC_CPU_INTEL_CORE2:
+		error = pmc_core_initialize(pmc_mdep, ncpus);
+		break;
 
 		/*
 		 * Intel Pentium 4 Processors, and P4/EMT64 processors.
@@ -184,7 +210,7 @@ pmc_intel_initialize(void)
 
 		KASSERT(pmc_mdep->pmd_npmc == TSC_NPMCS + PENTIUM_NPMCS,
 		    ("[intel,%d] incorrect npmc count %d", __LINE__,
-		    md->pmd_npmc));
+		    pmc_mdep->pmd_npmc));
 		break;
 #endif
 
@@ -209,6 +235,12 @@ pmc_intel_finalize(struct pmc_mdep *md)
 
 	switch (md->pmd_cputype) {
 #if	defined(__i386__) || defined(__amd64__)
+	case PMC_CPU_INTEL_ATOM:
+	case PMC_CPU_INTEL_CORE:
+	case PMC_CPU_INTEL_CORE2:
+		pmc_core_finalize(md);
+		break;
+
 	case PMC_CPU_INTEL_PIV:
 		pmc_p4_finalize(md);
 		break;