Split the registers into two halves in preparation for SBus support.

Obtained from:	NetBSD (loosely)
MFC after:	2 weeks

4 files changed, 285 insertions, 212 deletions

diff --git a/sys/dev/gem/if_gem.c b/sys/dev/gem/if_gem.c
index 5d05a8d..5517aaa 100644
--- a/sys/dev/gem/if_gem.c
+++ b/sys/dev/gem/if_gem.c
@@ -96,8 +96,8 @@ CTASSERT(powerof2(GEM_NTXDESC) && GEM_NTXDESC >= 32 && GEM_NTXDESC <= 8192);
 #define	GEM_CSUM_FEATURES	(CSUM_TCP)
 
 static int	gem_add_rxbuf(struct gem_softc *sc, int idx);
-static int	gem_bitwait(struct gem_softc *sc, bus_addr_t r, uint32_t clr,
-		    uint32_t set);
+static int	gem_bitwait(struct gem_softc *sc, u_int bank, bus_addr_t r,
+		    uint32_t clr, uint32_t set);
 static void	gem_cddma_callback(void *xsc, bus_dma_segment_t *segs,
 		    int nsegs, int error);
 static int	gem_disable_rx(struct gem_softc *sc);
@@ -140,6 +140,11 @@ MODULE_DEPEND(gem, miibus, 1, 1, 1);
 #define	KTR_GEM		KTR_CT2
 #endif
 
+#define	GEM_BANK1_BITWAIT(sc, r, clr, set)				\
+	gem_bitwait((sc), GEM_RES_BANK1, (r), (clr), (set))
+#define	GEM_BANK2_BITWAIT(sc, r, clr, set)				\
+	gem_bitwait((sc), GEM_RES_BANK2, (r), (clr), (set))
+
 int
 gem_attach(struct gem_softc *sc)
 {
@@ -252,7 +257,7 @@ gem_attach(struct gem_softc *sc)
 
 	/* Bad things will happen when touching this register on ERI. */
 	if (sc->sc_variant != GEM_SUN_ERI)
-		bus_write_4(sc->sc_res[0], GEM_MII_DATAPATH_MODE,
+		GEM_BANK1_WRITE_4(sc, GEM_MII_DATAPATH_MODE,
 		    GEM_MII_DATAPATH_MII);
 
 	gem_mifinit(sc);
@@ -261,10 +266,10 @@ gem_attach(struct gem_softc *sc)
 	 * Look for an external PHY.
 	 */
 	error = ENXIO;
-	v = bus_read_4(sc->sc_res[0], GEM_MIF_CONFIG);
+	v = GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG);
 	if ((v & GEM_MIF_CONFIG_MDI1) != 0) {
 		v |= GEM_MIF_CONFIG_PHY_SEL;
-		bus_write_4(sc->sc_res[0], GEM_MIF_CONFIG, v);
+		GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, v);
 		switch (sc->sc_variant) {
 		case GEM_SUN_ERI:
 			sc->sc_phyad = GEM_PHYAD_EXTERNAL;
@@ -282,7 +287,7 @@ gem_attach(struct gem_softc *sc)
 	 */
 	if (error != 0 && (v & GEM_MIF_CONFIG_MDI0) != 0) {
 		v &= ~GEM_MIF_CONFIG_PHY_SEL;
-		bus_write_4(sc->sc_res[0], GEM_MIF_CONFIG, v);
+		GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, v);
 		switch (sc->sc_variant) {
 		case GEM_SUN_ERI:
 		case GEM_APPLE_K2_GMAC:
@@ -303,12 +308,11 @@ gem_attach(struct gem_softc *sc)
 	 * Try the external PCS SERDES if we didn't find any PHYs.
 	 */
 	if (error != 0 && sc->sc_variant == GEM_SUN_GEM) {
-		bus_write_4(sc->sc_res[0], GEM_MII_DATAPATH_MODE,
+		GEM_BANK1_WRITE_4(sc, GEM_MII_DATAPATH_MODE,
 		    GEM_MII_DATAPATH_SERDES);
-		bus_write_4(sc->sc_res[0], GEM_MII_SLINK_CONTROL,
+		GEM_BANK1_WRITE_4(sc, GEM_MII_SLINK_CONTROL,
 		    GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D);
-		bus_write_4(sc->sc_res[0], GEM_MII_CONFIG,
-		    GEM_MII_CONFIG_ENABLE);
+		GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE);
 		sc->sc_flags |= GEM_SERDES;
 		sc->sc_phyad = GEM_PHYAD_EXTERNAL;
 		error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus,
@@ -329,10 +333,10 @@ gem_attach(struct gem_softc *sc)
 
 	/* Get RX FIFO size. */
 	sc->sc_rxfifosize = 64 *
-	    bus_read_4(sc->sc_res[0], GEM_RX_FIFO_SIZE);
+	    GEM_BANK1_READ_4(sc, GEM_RX_FIFO_SIZE);
 
 	/* Get TX FIFO size. */
-	v = bus_read_4(sc->sc_res[0], GEM_TX_FIFO_SIZE);
+	v = GEM_BANK1_READ_4(sc, GEM_TX_FIFO_SIZE);
 	device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n",
 	    sc->sc_rxfifosize / 1024, v / 16);
 
@@ -592,18 +596,18 @@ gem_tick(void *arg)
 	 * Unload collision counters.
 	 */
 	ifp->if_collisions +=
-	    bus_read_4(sc->sc_res[0], GEM_MAC_NORM_COLL_CNT) +
-	    bus_read_4(sc->sc_res[0], GEM_MAC_FIRST_COLL_CNT) +
-	    bus_read_4(sc->sc_res[0], GEM_MAC_EXCESS_COLL_CNT) +
-	    bus_read_4(sc->sc_res[0], GEM_MAC_LATE_COLL_CNT);
+	    GEM_BANK1_READ_4(sc, GEM_MAC_NORM_COLL_CNT) +
+	    GEM_BANK1_READ_4(sc, GEM_MAC_FIRST_COLL_CNT) +
+	    GEM_BANK1_READ_4(sc, GEM_MAC_EXCESS_COLL_CNT) +
+	    GEM_BANK1_READ_4(sc, GEM_MAC_LATE_COLL_CNT);
 
 	/*
 	 * Then clear the hardware counters.
 	 */
-	bus_write_4(sc->sc_res[0], GEM_MAC_NORM_COLL_CNT, 0);
-	bus_write_4(sc->sc_res[0], GEM_MAC_FIRST_COLL_CNT, 0);
-	bus_write_4(sc->sc_res[0], GEM_MAC_EXCESS_COLL_CNT, 0);
-	bus_write_4(sc->sc_res[0], GEM_MAC_LATE_COLL_CNT, 0);
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_NORM_COLL_CNT, 0);
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_FIRST_COLL_CNT, 0);
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_EXCESS_COLL_CNT, 0);
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_LATE_COLL_CNT, 0);
 
 	mii_tick(sc->sc_mii);
 
@@ -614,13 +618,14 @@ gem_tick(void *arg)
 }
 
 static int
-gem_bitwait(struct gem_softc *sc, bus_addr_t r, uint32_t clr, uint32_t set)
+gem_bitwait(struct gem_softc *sc, u_int bank, bus_addr_t r, uint32_t clr,
+    uint32_t set)
 {
 	int i;
 	uint32_t reg;
 
 	for (i = TRIES; i--; DELAY(100)) {
-		reg = bus_read_4(sc->sc_res[0], r);
+		reg = GEM_BANKN_READ_M(bank, 4, sc, r);
 		if ((reg & clr) == 0 && (reg & set) == set)
 			return (1);
 	}
@@ -639,9 +644,9 @@ gem_reset(sc)
 	gem_reset_tx(sc);
 
 	/* Do a full reset. */
-	bus_write_4(sc->sc_res[0], GEM_RESET, GEM_RESET_RX | GEM_RESET_TX);
-	bus_barrier(sc->sc_res[0], GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE);
-	if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0))
+	GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX);
+	GEM_BANK2_BARRIER(sc, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE);
+	if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0))
 		device_printf(sc->sc_dev, "cannot reset device\n");
 }
 
@@ -719,15 +724,16 @@ gem_reset_rx(struct gem_softc *sc)
 	 * disable DMA first.
 	 */
 	gem_disable_rx(sc);
-	bus_write_4(sc->sc_res[0], GEM_RX_CONFIG, 0);
-	bus_barrier(sc->sc_res[0], GEM_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
-	if (!gem_bitwait(sc, GEM_RX_CONFIG, GEM_RX_CONFIG_RXDMA_EN, 0))
+	GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 0);
+	GEM_BANK1_BARRIER(sc, GEM_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
+	if (!GEM_BANK1_BITWAIT(sc, GEM_RX_CONFIG, GEM_RX_CONFIG_RXDMA_EN, 0))
 		device_printf(sc->sc_dev, "cannot disable RX DMA\n");
 
 	/* Finally, reset the ERX. */
-	bus_write_4(sc->sc_res[0], GEM_RESET, GEM_RESET_RX);
-	bus_barrier(sc->sc_res[0], GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE);
-	if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) {
+	GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_RX);
+	GEM_BANK2_BARRIER(sc, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE);
+	if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX,
+	    0)) {
 		device_printf(sc->sc_dev, "cannot reset receiver\n");
 		return (1);
 	}
@@ -756,28 +762,26 @@ gem_reset_rxdma(struct gem_softc *sc)
 	GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD);
 
 	/* NOTE: we use only 32-bit DMA addresses here. */
-	bus_write_4(sc->sc_res[0], GEM_RX_RING_PTR_HI, 0);
-	bus_write_4(sc->sc_res[0], GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
-	bus_write_4(sc->sc_res[0], GEM_RX_KICK, GEM_NRXDESC - 4);
-	bus_write_4(sc->sc_res[0], GEM_RX_CONFIG,
+	GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0);
+	GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
+	GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, GEM_NRXDESC - 4);
+	GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG,
 	    gem_ringsize(GEM_NRXDESC /* XXX */) |
 	    ((ETHER_HDR_LEN + sizeof(struct ip)) <<
 	    GEM_RX_CONFIG_CXM_START_SHFT) |
 	    (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) |
 	    (2 << GEM_RX_CONFIG_FBOFF_SHFT));
-	bus_write_4(sc->sc_res[0], GEM_RX_BLANKING,
+	GEM_BANK1_WRITE_4(sc, GEM_RX_BLANKING,
 	    (6 << GEM_RX_BLANKING_TIME_SHIFT) | 6);
-	bus_write_4(sc->sc_res[0], GEM_RX_PAUSE_THRESH,
+	GEM_BANK1_WRITE_4(sc, GEM_RX_PAUSE_THRESH,
 	    (3 * sc->sc_rxfifosize / 256) |
 	    ((sc->sc_rxfifosize / 256) << 12));
-	bus_write_4(sc->sc_res[0], GEM_RX_CONFIG,
-	    bus_read_4(sc->sc_res[0], GEM_RX_CONFIG) |
-	    GEM_RX_CONFIG_RXDMA_EN);
-	bus_write_4(sc->sc_res[0], GEM_MAC_RX_MASK,
+	GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG,
+	    GEM_BANK1_READ_4(sc, GEM_RX_CONFIG) | GEM_RX_CONFIG_RXDMA_EN);
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_MASK,
 	    GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT);
-	bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG,
-	    bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG) |
-	    GEM_MAC_RX_ENABLE);
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG,
+	    GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG) | GEM_MAC_RX_ENABLE);
 }
 
 static int
@@ -789,15 +793,16 @@ gem_reset_tx(struct gem_softc *sc)
 	 * disable DMA first.
 	 */
 	gem_disable_tx(sc);
-	bus_write_4(sc->sc_res[0], GEM_TX_CONFIG, 0);
-	bus_barrier(sc->sc_res[0], GEM_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
-	if (!gem_bitwait(sc, GEM_TX_CONFIG, GEM_TX_CONFIG_TXDMA_EN, 0))
+	GEM_BANK1_WRITE_4(sc, GEM_TX_CONFIG, 0);
+	GEM_BANK1_BARRIER(sc, GEM_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
+	if (!GEM_BANK1_BITWAIT(sc, GEM_TX_CONFIG, GEM_TX_CONFIG_TXDMA_EN, 0))
 		device_printf(sc->sc_dev, "cannot disable TX DMA\n");
 
 	/* Finally, reset the ETX. */
-	bus_write_4(sc->sc_res[0], GEM_RESET, GEM_RESET_TX);
-	bus_barrier(sc->sc_res[0], GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE);
-	if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) {
+	GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_TX);
+	GEM_BANK2_BARRIER(sc, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE);
+	if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX,
+	    0)) {
 		device_printf(sc->sc_dev, "cannot reset transmitter\n");
 		return (1);
 	}
@@ -807,27 +812,23 @@ gem_reset_tx(struct gem_softc *sc)
 static int
 gem_disable_rx(struct gem_softc *sc)
 {
-	uint32_t cfg;
-
-	cfg = bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG);
-	cfg &= ~GEM_MAC_RX_ENABLE;
-	bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, cfg);
-	bus_barrier(sc->sc_res[0], GEM_MAC_RX_CONFIG, 4,
-	    BUS_SPACE_BARRIER_WRITE);
-	return (gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0));
+
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG,
+	    GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG) & ~GEM_MAC_RX_ENABLE);
+	GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
+	return (GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE,
+	    0));
 }
 
 static int
 gem_disable_tx(struct gem_softc *sc)
 {
-	uint32_t cfg;
-
-	cfg = bus_read_4(sc->sc_res[0], GEM_MAC_TX_CONFIG);
-	cfg &= ~GEM_MAC_TX_ENABLE;
-	bus_write_4(sc->sc_res[0], GEM_MAC_TX_CONFIG, cfg);
-	bus_barrier(sc->sc_res[0], GEM_MAC_TX_CONFIG, 4,
-	    BUS_SPACE_BARRIER_WRITE);
-	return (gem_bitwait(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0));
+
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG,
+	    GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG) & ~GEM_MAC_TX_ENABLE);
+	GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
+	return (GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE,
+	    0));
 }
 
 static int
@@ -961,18 +962,18 @@ gem_init_locked(struct gem_softc *sc)
 
 	/* step 6 & 7.  Program Descriptor Ring Base Addresses. */
 	/* NOTE: we use only 32-bit DMA addresses here. */
-	bus_write_4(sc->sc_res[0], GEM_TX_RING_PTR_HI, 0);
-	bus_write_4(sc->sc_res[0], GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0));
+	GEM_BANK1_WRITE_4(sc, GEM_TX_RING_PTR_HI, 0);
+	GEM_BANK1_WRITE_4(sc, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0));
 
-	bus_write_4(sc->sc_res[0], GEM_RX_RING_PTR_HI, 0);
-	bus_write_4(sc->sc_res[0], GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
+	GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0);
+	GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
 #ifdef GEM_DEBUG
 	CTR3(KTR_GEM, "loading RX ring %lx, TX ring %lx, cddma %lx",
 	    GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma);
 #endif
 
 	/* step 8.  Global Configuration & Interrupt Mask */
-	bus_write_4(sc->sc_res[0], GEM_INTMASK,
+	GEM_BANK1_WRITE_4(sc, GEM_INTMASK,
 	    ~(GEM_INTR_TX_INTME | GEM_INTR_TX_EMPTY | GEM_INTR_RX_DONE |
 	    GEM_INTR_RX_NOBUF | GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR |
 	    GEM_INTR_BERR
@@ -980,15 +981,15 @@ gem_init_locked(struct gem_softc *sc)
 	    | GEM_INTR_PCS | GEM_INTR_MIF
 #endif
 	    ));
-	bus_write_4(sc->sc_res[0], GEM_MAC_RX_MASK,
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_MASK,
 	    GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT);
-	bus_write_4(sc->sc_res[0], GEM_MAC_TX_MASK,
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_MASK,
 	    GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP);
 #ifdef GEM_DEBUG
-	bus_write_4(sc->sc_res[0], GEM_MAC_CONTROL_MASK,
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_MASK,
 	    ~(GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME));
 #else
-	bus_write_4(sc->sc_res[0], GEM_MAC_CONTROL_MASK,
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_MASK,
 	    GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME);
 #endif
 
@@ -996,7 +997,7 @@ gem_init_locked(struct gem_softc *sc)
 
 	/* Enable DMA. */
 	v = gem_ringsize(GEM_NTXDESC /* XXX */);
-	bus_write_4(sc->sc_res[0], GEM_TX_CONFIG,
+	GEM_BANK1_WRITE_4(sc, GEM_TX_CONFIG,
 	    v | GEM_TX_CONFIG_TXDMA_EN |
 	    ((0x400 << 10) & GEM_TX_CONFIG_TXFIFO_TH));
 
@@ -1009,37 +1010,36 @@ gem_init_locked(struct gem_softc *sc)
 	    GEM_RX_CONFIG_CXM_START_SHFT);
 
 	/* Enable DMA. */
-	bus_write_4(sc->sc_res[0], GEM_RX_CONFIG,
+	GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG,
 	    v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) |
 	    (2 << GEM_RX_CONFIG_FBOFF_SHFT) | GEM_RX_CONFIG_RXDMA_EN);
 
-	bus_write_4(sc->sc_res[0], GEM_RX_BLANKING,
+	GEM_BANK1_WRITE_4(sc, GEM_RX_BLANKING,
 	    (6 << GEM_RX_BLANKING_TIME_SHIFT) | 6);
 
 	/*
 	 * The following value is for an OFF Threshold of about 3/4 full
 	 * and an ON Threshold of 1/4 full.
 	 */
-	bus_write_4(sc->sc_res[0], GEM_RX_PAUSE_THRESH,
+	GEM_BANK1_WRITE_4(sc, GEM_RX_PAUSE_THRESH,
 	    (3 * sc->sc_rxfifosize / 256) |
 	    ((sc->sc_rxfifosize / 256) << 12));
 
 	/* step 11.  Configure Media. */
 
 	/* step 12.  RX_MAC Configuration Register */
-	v = bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG);
+	v = GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG);
 	v |= GEM_MAC_RX_STRIP_CRC;
-	bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, 0);
-	bus_barrier(sc->sc_res[0], GEM_MAC_RX_CONFIG, 4,
-	    BUS_SPACE_BARRIER_WRITE);
-	if (!gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0))
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 0);
+	GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
+	if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0))
 		device_printf(sc->sc_dev, "cannot disable RX MAC\n");
-	bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, v);
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v);
 
 	/* step 14.  Issue Transmit Pending command. */
 
 	/* step 15.  Give the reciever a swift kick. */
-	bus_write_4(sc->sc_res[0], GEM_RX_KICK, GEM_NRXDESC - 4);
+	GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, GEM_NRXDESC - 4);
 
 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
@@ -1183,60 +1183,59 @@ gem_init_regs(struct gem_softc *sc)
 	/* These registers are not cleared on reset. */
 	if ((sc->sc_flags & GEM_INITED) == 0) {
 		/* magic values */
-		bus_write_4(sc->sc_res[0], GEM_MAC_IPG0, 0);
-		bus_write_4(sc->sc_res[0], GEM_MAC_IPG1, 8);
-		bus_write_4(sc->sc_res[0], GEM_MAC_IPG2, 4);
+		GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG0, 0);
+		GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG1, 8);
+		GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG2, 4);
 
-		bus_write_4(sc->sc_res[0], GEM_MAC_MAC_MIN_FRAME,
-		    ETHER_MIN_LEN);
+		GEM_BANK1_WRITE_4(sc, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN);
 		/* max frame and max burst size */
-		bus_write_4(sc->sc_res[0], GEM_MAC_MAC_MAX_FRAME,
+		GEM_BANK1_WRITE_4(sc, GEM_MAC_MAC_MAX_FRAME,
 		    (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) | (0x2000 << 16));
 
-		bus_write_4(sc->sc_res[0], GEM_MAC_PREAMBLE_LEN, 0x7);
-		bus_write_4(sc->sc_res[0], GEM_MAC_JAM_SIZE, 0x4);
-		bus_write_4(sc->sc_res[0], GEM_MAC_ATTEMPT_LIMIT, 0x10);
+		GEM_BANK1_WRITE_4(sc, GEM_MAC_PREAMBLE_LEN, 0x7);
+		GEM_BANK1_WRITE_4(sc, GEM_MAC_JAM_SIZE, 0x4);
+		GEM_BANK1_WRITE_4(sc, GEM_MAC_ATTEMPT_LIMIT, 0x10);
 		/* dunno... */
-		bus_write_4(sc->sc_res[0], GEM_MAC_CONTROL_TYPE, 0x8088);
-		bus_write_4(sc->sc_res[0], GEM_MAC_RANDOM_SEED,
+		GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_TYPE, 0x8088);
+		GEM_BANK1_WRITE_4(sc, GEM_MAC_RANDOM_SEED,
 		    ((laddr[5] << 8) | laddr[4]) & 0x3ff);
 
 		/* secondary MAC address: 0:0:0:0:0:0 */
-		bus_write_4(sc->sc_res[0], GEM_MAC_ADDR3, 0);
-		bus_write_4(sc->sc_res[0], GEM_MAC_ADDR4, 0);
-		bus_write_4(sc->sc_res[0], GEM_MAC_ADDR5, 0);
+		GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR3, 0);
+		GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR4, 0);
+		GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR5, 0);
 
 		/* MAC control address: 01:80:c2:00:00:01 */
-		bus_write_4(sc->sc_res[0], GEM_MAC_ADDR6, 0x0001);
-		bus_write_4(sc->sc_res[0], GEM_MAC_ADDR7, 0xc200);
-		bus_write_4(sc->sc_res[0], GEM_MAC_ADDR8, 0x0180);
+		GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR6, 0x0001);
+		GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR7, 0xc200);
+		GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR8, 0x0180);
 
 		/* MAC filter address: 0:0:0:0:0:0 */
-		bus_write_4(sc->sc_res[0], GEM_MAC_ADDR_FILTER0, 0);
-		bus_write_4(sc->sc_res[0], GEM_MAC_ADDR_FILTER1, 0);
-		bus_write_4(sc->sc_res[0], GEM_MAC_ADDR_FILTER2, 0);
+		GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER0, 0);
+		GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER1, 0);
+		GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER2, 0);
 
-		bus_write_4(sc->sc_res[0], GEM_MAC_ADR_FLT_MASK1_2, 0);
-		bus_write_4(sc->sc_res[0], GEM_MAC_ADR_FLT_MASK0, 0);
+		GEM_BANK1_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK1_2, 0);
+		GEM_BANK1_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK0, 0);
 
 		sc->sc_flags |= GEM_INITED;
 	}
 
 	/* Counters need to be zeroed. */
-	bus_write_4(sc->sc_res[0], GEM_MAC_NORM_COLL_CNT, 0);
-	bus_write_4(sc->sc_res[0], GEM_MAC_FIRST_COLL_CNT, 0);
-	bus_write_4(sc->sc_res[0], GEM_MAC_EXCESS_COLL_CNT, 0);
-	bus_write_4(sc->sc_res[0], GEM_MAC_LATE_COLL_CNT, 0);
-	bus_write_4(sc->sc_res[0], GEM_MAC_DEFER_TMR_CNT, 0);
-	bus_write_4(sc->sc_res[0], GEM_MAC_PEAK_ATTEMPTS, 0);
-	bus_write_4(sc->sc_res[0], GEM_MAC_RX_FRAME_COUNT, 0);
-	bus_write_4(sc->sc_res[0], GEM_MAC_RX_LEN_ERR_CNT, 0);
-	bus_write_4(sc->sc_res[0], GEM_MAC_RX_ALIGN_ERR, 0);
-	bus_write_4(sc->sc_res[0], GEM_MAC_RX_CRC_ERR_CNT, 0);
-	bus_write_4(sc->sc_res[0], GEM_MAC_RX_CODE_VIOL, 0);
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_NORM_COLL_CNT, 0);
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_FIRST_COLL_CNT, 0);
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_EXCESS_COLL_CNT, 0);
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_LATE_COLL_CNT, 0);
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_DEFER_TMR_CNT, 0);
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_PEAK_ATTEMPTS, 0);
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_FRAME_COUNT, 0);
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_LEN_ERR_CNT, 0);
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_ALIGN_ERR, 0);
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CRC_ERR_CNT, 0);
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CODE_VIOL, 0);
 
 	/* Set XOFF PAUSE time. */
-	bus_write_4(sc->sc_res[0], GEM_MAC_SEND_PAUSE_CMD, 0x1BF0);
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0);
 
 	/*
 	 * Set the internal arbitration to "infinite" bursts of the
@@ -1245,22 +1244,18 @@ gem_init_regs(struct gem_softc *sc)
 	 * especially RX performance.
 	 * Enable silicon bug workarounds for the Apple variants.
 	 */
-	bus_write_4(sc->sc_res[0], GEM_CONFIG,
+	GEM_BANK1_WRITE_4(sc, GEM_CONFIG,
 	    GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT |
 	    GEM_CONFIG_BURST_INF | (GEM_IS_APPLE(sc) ?
 	    GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0));
 
 	/* Set the station address. */
-	bus_write_4(sc->sc_res[0], GEM_MAC_ADDR0,
-	    (laddr[4] << 8) | laddr[5]);
-	bus_write_4(sc->sc_res[0], GEM_MAC_ADDR1,
-	    (laddr[2] << 8) | laddr[3]);
-	bus_write_4(sc->sc_res[0], GEM_MAC_ADDR2,
-	    (laddr[0] << 8) | laddr[1]);
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR0, (laddr[4] << 8) | laddr[5]);
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR1, (laddr[2] << 8) | laddr[3]);
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR2, (laddr[0] << 8) | laddr[1]);
 
 	/* Enable MII outputs. */
-	bus_write_4(sc->sc_res[0], GEM_MAC_XIF_CONFIG,
-	    GEM_MAC_XIF_TX_MII_ENA);
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_XIF_CONFIG, GEM_MAC_XIF_TX_MII_ENA);
 }
 
 static void
@@ -1308,7 +1303,7 @@ gem_start_locked(struct ifnet *ifp)
 		    device_get_name(sc->sc_dev), __func__, sc->sc_txnext);
 #endif
 		GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
-		bus_write_4(sc->sc_res[0], GEM_TX_KICK, sc->sc_txnext);
+		GEM_BANK1_WRITE_4(sc, GEM_TX_KICK, sc->sc_txnext);
 
 		BPF_MTAP(ifp, m);
 	}
@@ -1373,7 +1368,7 @@ gem_tint(struct gem_softc *sc)
 		 * GEM_TX_COMPLETION points to the last descriptor
 		 * processed + 1.
 		 */
-		txlast = bus_read_4(sc->sc_res[0], GEM_TX_COMPLETION);
+		txlast = GEM_BANK1_READ_4(sc, GEM_TX_COMPLETION);
 #ifdef GEM_DEBUG
 		CTR4(KTR_GEM, "%s: txs->txs_firstdesc = %d, "
 		    "txs->txs_lastdesc = %d, txlast = %d",
@@ -1414,11 +1409,10 @@ gem_tint(struct gem_softc *sc)
 #ifdef GEM_DEBUG
 	CTR4(KTR_GEM, "%s: GEM_TX_STATE_MACHINE %x GEM_TX_DATA_PTR %llx "
 	    "GEM_TX_COMPLETION %x",
-	    __func__, bus_read_4(sc->sc_res[0], GEM_TX_STATE_MACHINE),
-	    ((long long)bus_read_4(sc->sc_res[0],
-	    GEM_TX_DATA_PTR_HI) << 32) |
-	    bus_read_4(sc->sc_res[0], GEM_TX_DATA_PTR_LO),
-	    bus_read_4(sc->sc_res[0], GEM_TX_COMPLETION));
+	    __func__, GEM_BANK1_READ_4(sc, GEM_TX_STATE_MACHINE),
+	    ((long long)GEM_BANK1_READ_4(sc, GEM_TX_DATA_PTR_HI) << 32) |
+	    GEM_BANK1_READ_4(sc, GEM_TX_DATA_PTR_LO),
+	    GEM_BANK1_READ_4(sc, GEM_TX_COMPLETION));
 #endif
 
 	if (progress) {
@@ -1473,7 +1467,7 @@ gem_rint(struct gem_softc *sc)
 	 * Read the completion register once.  This limits
 	 * how long the following loop can execute.
 	 */
-	rxcomp = bus_read_4(sc->sc_res[0], GEM_RX_COMPLETION);
+	rxcomp = GEM_BANK1_READ_4(sc, GEM_RX_COMPLETION);
 
 #ifdef GEM_DEBUG
 	CTR3(KTR_GEM, "%s: sc->rxptr %d, complete %d",
@@ -1545,7 +1539,7 @@ gem_rint(struct gem_softc *sc)
 		sc->sc_rxptr = GEM_NEXTRX(sc->sc_rxptr);
 		if ((sc->sc_rxptr % 4) == 0) {
 			GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
-			bus_write_4(sc->sc_res[0], GEM_RX_KICK,
+			GEM_BANK1_WRITE_4(sc, GEM_RX_KICK,
 			    (sc->sc_rxptr + GEM_NRXDESC - 4) &
 			    GEM_NRXDESC_MASK);
 		}
@@ -1572,7 +1566,7 @@ gem_rint(struct gem_softc *sc)
 
 #ifdef GEM_DEBUG
 	CTR3(KTR_GEM, "%s: done sc->rxptr %d, complete %d", __func__,
-	    sc->sc_rxptr, bus_read_4(sc->sc_res[0], GEM_RX_COMPLETION));
+	    sc->sc_rxptr, GEM_BANK1_READ_4(sc, GEM_RX_COMPLETION));
 #endif
 }
 
@@ -1642,7 +1636,7 @@ gem_intr(void *v)
 	uint32_t status, status2;
 
 	GEM_LOCK(sc);
-	status = bus_read_4(sc->sc_res[0], GEM_STATUS);
+	status = GEM_BANK1_READ_4(sc, GEM_STATUS);
 
 #ifdef GEM_DEBUG
 	CTR4(KTR_GEM, "%s: %s: cplt %x, status %x",
@@ -1654,14 +1648,14 @@ gem_intr(void *v)
 	 */
 	if ((status & GEM_INTR_PCS) != 0) {
 		status2 =
-		    bus_read_4(sc->sc_res[0], GEM_MII_INTERRUP_STATUS) |
-		    bus_read_4(sc->sc_res[0], GEM_MII_INTERRUP_STATUS);
+		    GEM_BANK1_READ_4(sc, GEM_MII_INTERRUP_STATUS) |
+		    GEM_BANK1_READ_4(sc, GEM_MII_INTERRUP_STATUS);
 		if ((status2 & GEM_MII_INTERRUP_LINK) != 0)
 			device_printf(sc->sc_dev,
 			    "%s: PCS link status changed\n", __func__);
 	}
 	if ((status & GEM_MAC_CONTROL_STATUS) != 0) {
-		status2 = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_STATUS);
+		status2 = GEM_BANK1_READ_4(sc, GEM_MAC_CONTROL_STATUS);
 		if ((status2 & GEM_MAC_PAUSED) != 0)
 			device_printf(sc->sc_dev,
 			    "%s: PAUSE received (PAUSE time %d slots)\n",
@@ -1688,7 +1682,7 @@ gem_intr(void *v)
 		gem_tint(sc);
 
 	if (status & GEM_INTR_TX_MAC) {
-		status2 = bus_read_4(sc->sc_res[0], GEM_MAC_TX_STATUS);
+		status2 = GEM_BANK1_READ_4(sc, GEM_MAC_TX_STATUS);
 		if ((status2 &
 		    ~(GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP)) != 0)
 			device_printf(sc->sc_dev,
@@ -1698,7 +1692,7 @@ gem_intr(void *v)
 			gem_init_locked(sc);
 	}
 	if (status & GEM_INTR_RX_MAC) {
-		status2 = bus_read_4(sc->sc_res[0], GEM_MAC_RX_STATUS);
+		status2 = GEM_BANK1_READ_4(sc, GEM_MAC_RX_STATUS);
 		/*
 		 * At least with GEM_SUN_GEM and some GEM_SUN_ERI
 		 * revisions GEM_MAC_RX_OVERFLOW happen often due to a
@@ -1725,14 +1719,14 @@ gem_watchdog(struct gem_softc *sc)
 #ifdef GEM_DEBUG
 	CTR4(KTR_GEM,
 	    "%s: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x GEM_MAC_RX_CONFIG %x",
-	    __func__, bus_read_4(sc->sc_res[0], GEM_RX_CONFIG),
-	    bus_read_4(sc->sc_res[0], GEM_MAC_RX_STATUS),
-	    bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG));
+	    __func__, GEM_BANK1_READ_4(sc, GEM_RX_CONFIG),
+	    GEM_BANK1_READ_4(sc, GEM_MAC_RX_STATUS),
+	    GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG));
 	CTR4(KTR_GEM,
 	    "%s: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x GEM_MAC_TX_CONFIG %x",
-	    __func__, bus_read_4(sc->sc_res[0], GEM_TX_CONFIG),
-	    bus_read_4(sc->sc_res[0], GEM_MAC_TX_STATUS),
-	    bus_read_4(sc->sc_res[0], GEM_MAC_TX_CONFIG));
+	    __func__, GEM_BANK1_READ_4(sc, GEM_TX_CONFIG),
+	    GEM_BANK1_READ_4(sc, GEM_MAC_TX_STATUS),
+	    GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG));
 #endif
 
 	if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0)
@@ -1754,8 +1748,8 @@ gem_mifinit(struct gem_softc *sc)
 {
 
 	/* Configure the MIF in frame mode. */
-	bus_write_4(sc->sc_res[0], GEM_MIF_CONFIG, bus_read_4(sc->sc_res[0],
-	    GEM_MIF_CONFIG) & ~GEM_MIF_CONFIG_BB_ENA);
+	GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG,
+	    GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG) & ~GEM_MIF_CONFIG_BB_ENA);
 }
 
 /*
@@ -1811,7 +1805,7 @@ gem_mii_readreg(device_t dev, int phy, int reg)
 			    "%s: unhandled register %d\n", __func__, reg);
 			return (0);
 		}
-		return (bus_read_4(sc->sc_res[0], reg));
+		return (GEM_BANK1_READ_4(sc, reg));
 	}
 
 	/* Construct the frame command. */
@@ -1819,10 +1813,10 @@ gem_mii_readreg(device_t dev, int phy, int reg)
 	    (phy << GEM_MIF_PHY_SHIFT) |
 	    (reg << GEM_MIF_REG_SHIFT);
 
-	bus_write_4(sc->sc_res[0], GEM_MIF_FRAME, v);
+	GEM_BANK1_WRITE_4(sc, GEM_MIF_FRAME, v);
 	for (n = 0; n < 100; n++) {
 		DELAY(1);
-		v = bus_read_4(sc->sc_res[0], GEM_MIF_FRAME);
+		v = GEM_BANK1_READ_4(sc, GEM_MIF_FRAME);
 		if (v & GEM_MIF_FRAME_TA0)
 			return (v & GEM_MIF_FRAME_DATA);
 	}
@@ -1855,13 +1849,13 @@ gem_mii_writereg(device_t dev, int phy, int reg, int val)
 			reg = GEM_MII_STATUS;
 			break;
 		case MII_ANAR:
-			bus_write_4(sc->sc_res[0], GEM_MII_CONFIG, 0);
-			bus_barrier(sc->sc_res[0], GEM_MII_CONFIG, 4,
+			GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, 0);
+			GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4,
 			    BUS_SPACE_BARRIER_WRITE);
-			bus_write_4(sc->sc_res[0], GEM_MII_ANAR, val);
-			bus_write_4(sc->sc_res[0], GEM_MII_SLINK_CONTROL,
+			GEM_BANK1_WRITE_4(sc, GEM_MII_ANAR, val);
+			GEM_BANK1_WRITE_4(sc, GEM_MII_SLINK_CONTROL,
 			    GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D);
-			bus_write_4(sc->sc_res[0], GEM_MII_CONFIG,
+			GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG,
 			    GEM_MII_CONFIG_ENABLE);
 			return (0);
 		case MII_ANLPAR:
@@ -1872,7 +1866,7 @@ gem_mii_writereg(device_t dev, int phy, int reg, int val)
 			    "%s: unhandled register %d\n", __func__, reg);
 			return (0);
 		}
-		bus_write_4(sc->sc_res[0], reg, val);
+		GEM_BANK1_WRITE_4(sc, reg, val);
 		return (0);
 	}
 
@@ -1882,10 +1876,10 @@ gem_mii_writereg(device_t dev, int phy, int reg, int val)
 	    (reg << GEM_MIF_REG_SHIFT) |
 	    (val & GEM_MIF_FRAME_DATA);
 
-	bus_write_4(sc->sc_res[0], GEM_MIF_FRAME, v);
+	GEM_BANK1_WRITE_4(sc, GEM_MIF_FRAME, v);
 	for (n = 0; n < 100; n++) {
 		DELAY(1);
-		v = bus_read_4(sc->sc_res[0], GEM_MIF_FRAME);
+		v = GEM_BANK1_READ_4(sc, GEM_MIF_FRAME);
 		if (v & GEM_MIF_FRAME_TA0)
 			return (1);
 	}
@@ -1933,7 +1927,7 @@ gem_mii_statchg(device_t dev)
 	 * the GEM Gigabit Ethernet ASIC Specification.
 	 */
 
-	rxcfg = bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG);
+	rxcfg = GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG);
 	rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE);
 	txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT;
 	if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
@@ -1942,20 +1936,18 @@ gem_mii_statchg(device_t dev)
 		rxcfg |= GEM_MAC_RX_CARR_EXTEND;
 		txcfg |= GEM_MAC_TX_CARR_EXTEND;
 	}
-	bus_write_4(sc->sc_res[0], GEM_MAC_TX_CONFIG, 0);
-	bus_barrier(sc->sc_res[0], GEM_MAC_TX_CONFIG, 4,
-	    BUS_SPACE_BARRIER_WRITE);
-	if (!gem_bitwait(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0))
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 0);
+	GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
+	if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0))
 		device_printf(sc->sc_dev, "cannot disable TX MAC\n");
-	bus_write_4(sc->sc_res[0], GEM_MAC_TX_CONFIG, txcfg);
-	bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, 0);
-	bus_barrier(sc->sc_res[0], GEM_MAC_RX_CONFIG, 4,
-	    BUS_SPACE_BARRIER_WRITE);
-	if (!gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0))
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, txcfg);
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 0);
+	GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
+	if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0))
 		device_printf(sc->sc_dev, "cannot disable RX MAC\n");
-	bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, rxcfg);
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, rxcfg);
 
-	v = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_CONFIG) &
+	v = GEM_BANK1_READ_4(sc, GEM_MAC_CONTROL_CONFIG) &
 	    ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE);
 #ifdef notyet
 	if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
@@ -1965,21 +1957,21 @@ gem_mii_statchg(device_t dev)
 	    IFM_ETH_TXPAUSE) != 0)
 		v |= GEM_MAC_CC_TX_PAUSE;
 #endif
-	bus_write_4(sc->sc_res[0], GEM_MAC_CONTROL_CONFIG, v);
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_CONFIG, v);
 
 	if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0 &&
 	    gigabit != 0)
-		bus_write_4(sc->sc_res[0], GEM_MAC_SLOT_TIME,
+		GEM_BANK1_WRITE_4(sc, GEM_MAC_SLOT_TIME,
 		    GEM_MAC_SLOT_TIME_CARR_EXTEND);
 	else
-		bus_write_4(sc->sc_res[0], GEM_MAC_SLOT_TIME,
+		GEM_BANK1_WRITE_4(sc, GEM_MAC_SLOT_TIME,
 		    GEM_MAC_SLOT_TIME_NORMAL);
 
 	/* XIF Configuration */
 	v = GEM_MAC_XIF_LINK_LED;
 	v |= GEM_MAC_XIF_TX_MII_ENA;
 	if ((sc->sc_flags & GEM_SERDES) == 0) {
-		if ((bus_read_4(sc->sc_res[0], GEM_MIF_CONFIG) &
+		if ((GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG) &
 		    GEM_MIF_CONFIG_PHY_SEL) != 0 &&
 		    (IFM_OPTIONS(sc->sc_mii->mii_media_active) &
 		    IFM_FDX) == 0)
@@ -1997,13 +1989,13 @@ gem_mii_statchg(device_t dev)
 		v |= GEM_MAC_XIF_GMII_MODE;
 	if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
 		v |= GEM_MAC_XIF_FDPLX_LED;
-	bus_write_4(sc->sc_res[0], GEM_MAC_XIF_CONFIG, v);
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_XIF_CONFIG, v);
 
 	if ((sc->sc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
 	    (sc->sc_flags & GEM_LINK) != 0) {
-		bus_write_4(sc->sc_res[0], GEM_MAC_TX_CONFIG,
+		GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG,
 		    txcfg | GEM_MAC_TX_ENABLE);
-		bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG,
+		GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG,
 		    rxcfg | GEM_MAC_RX_ENABLE);
 	}
 }
@@ -2107,7 +2099,7 @@ gem_setladrf(struct gem_softc *sc)
 	GEM_LOCK_ASSERT(sc, MA_OWNED);
 
 	/* Get the current RX configuration. */
-	v = bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG);
+	v = GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG);
 
 	/*
 	 * Turn off promiscuous mode, promiscuous group mode (all multicast),
@@ -2117,10 +2109,10 @@ gem_setladrf(struct gem_softc *sc)
 	v &= ~(GEM_MAC_RX_PROMISCUOUS | GEM_MAC_RX_HASH_FILTER |
 	    GEM_MAC_RX_PROMISC_GRP);
 
-	bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, v);
-	bus_barrier(sc->sc_res[0], GEM_MAC_RX_CONFIG, 4,
-	    BUS_SPACE_BARRIER_WRITE);
-	if (!gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_HASH_FILTER, 0))
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v);
+	GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
+	if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_HASH_FILTER,
+	    0))
 		device_printf(sc->sc_dev, "cannot disable RX hash filter\n");
 
 	if ((ifp->if_flags & IFF_PROMISC) != 0) {
@@ -2163,10 +2155,10 @@ gem_setladrf(struct gem_softc *sc)
 
 	/* Now load the hash table into the chip (if we are using it). */
 	for (i = 0; i < 16; i++)
-		bus_write_4(sc->sc_res[0],
+		GEM_BANK1_WRITE_4(sc,
 		    GEM_MAC_HASH0 + i * (GEM_MAC_HASH1 - GEM_MAC_HASH0),
 		    hash[i]);
 
  chipit:
-	bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, v);
+	GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v);
 }
diff --git a/sys/dev/gem/if_gem_pci.c b/sys/dev/gem/if_gem_pci.c
index b1bdce3..275b44e 100644
--- a/sys/dev/gem/if_gem_pci.c
+++ b/sys/dev/gem/if_gem_pci.c
@@ -40,6 +40,7 @@ __FBSDID("$FreeBSD$");
 #include <sys/bus.h>
 #include <sys/kernel.h>
 #include <sys/lock.h>
+#include <sys/malloc.h>
 #include <sys/module.h>
 #include <sys/mutex.h>
 #include <sys/resource.h>
@@ -134,8 +135,8 @@ gem_pci_probe(device_t dev)
 }
 
 static struct resource_spec gem_pci_res_spec[] = {
-	{ SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
-	{ SYS_RES_IRQ, 0, RF_SHAREABLE | RF_ACTIVE },
+	{ SYS_RES_IRQ, 0, RF_SHAREABLE | RF_ACTIVE },	/* GEM_RES_INTR */
+	{ SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },	/* GEM_RES_BANK1 */
 	{ -1, 0 }
 };
 
@@ -181,6 +182,24 @@ gem_pci_attach(device_t dev)
 
 	GEM_LOCK_INIT(sc, device_get_nameunit(dev));
 
+	/*
+	 * Derive GEM_RES_BANK2 from GEM_RES_BANK1.  This seemed cleaner
+	 * with the old way of using copies of the bus tag and handle in
+	 * the softc along with bus_space_*()...
+	 */
+	sc->sc_res[GEM_RES_BANK2] = malloc(sizeof(*sc->sc_res[GEM_RES_BANK2]),
+	    M_DEVBUF, M_NOWAIT | M_ZERO);
+	if (sc->sc_res[GEM_RES_BANK2] == NULL) {
+		device_printf(dev, "failed to allocate bank2 resource\n");
+		goto fail;
+	}
+	rman_set_bustag(sc->sc_res[GEM_RES_BANK2],
+	    rman_get_bustag(sc->sc_res[GEM_RES_BANK1]));
+	bus_space_subregion(rman_get_bustag(sc->sc_res[GEM_RES_BANK1]),
+	    rman_get_bushandle(sc->sc_res[GEM_RES_BANK1]),
+	    GEM_PCI_BANK2_OFFSET, GEM_PCI_BANK2_SIZE,
+	    &sc->sc_res[GEM_RES_BANK2]->r_bushandle);
+
 #if defined(__powerpc__) || defined(__sparc64__)
 	OF_getetheraddr(dev, sc->sc_enaddr);
 #else
@@ -216,11 +235,12 @@ gem_pci_attach(device_t dev)
 #define	PCI_VPD_LEN			0x02
 #define	PCI_VPD_DATA			0x03
 
-#define	GEM_ROM_READ_N(n, sc, offs)					\
-	bus_read_ ## n ((sc)->sc_res[0], GEM_PCI_ROM_OFFSET + (offs))
-#define	GEM_ROM_READ_1(sc, offs)	GEM_ROM_READ_N(1, (sc), (offs))
-#define	GEM_ROM_READ_2(sc, offs)	GEM_ROM_READ_N(2, (sc), (offs))
-#define	GEM_ROM_READ_4(sc, offs)	GEM_ROM_READ_N(4, (sc), (offs))
+#define	GEM_ROM_READ_1(sc, offs)					\
+    GEM_BANK1_READ_1((sc), GEM_PCI_ROM_OFFSET + (offs))
+#define	GEM_ROM_READ_2(sc, offs)					\
+    GEM_BANK1_READ_2((sc), GEM_PCI_ROM_OFFSET + (offs))
+#define	GEM_ROM_READ_4(sc, offs)					\
+    GEM_BANK1_READ_4((sc), GEM_PCI_ROM_OFFSET + (offs))
 
 	/* Read PCI Expansion ROM header. */
 	if (GEM_ROM_READ_2(sc, PCI_ROMHDR_SIG) != PCI_ROMHDR_SIG_MAGIC ||
@@ -252,8 +272,7 @@ gem_pci_attach(device_t dev)
 	if (PCI_VPDRES_ISLARGE(GEM_ROM_READ_1(sc,
 	    j + PCI_VPDRES_BYTE0)) == 0 ||
 	    PCI_VPDRES_LARGE_NAME(GEM_ROM_READ_1(sc,
-	    j + PCI_VPDRES_BYTE0)) !=
-	    PCI_VPDRES_TYPE_VPD ||
+	    j + PCI_VPDRES_BYTE0)) != PCI_VPDRES_TYPE_VPD ||
 	    (GEM_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_LSB) << 8 |
 	    GEM_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_MSB)) !=
 	    PCI_VPD_SIZE + ETHER_ADDR_LEN ||
@@ -268,9 +287,9 @@ gem_pci_attach(device_t dev)
 		device_printf(dev, "unexpected PCI VPD\n");
 		goto fail;
 	}
-	bus_read_region_1(sc->sc_res[0], GEM_PCI_ROM_OFFSET + j +
-	    PCI_VPDRES_LARGE_DATA + PCI_VPD_DATA, sc->sc_enaddr,
-	    ETHER_ADDR_LEN);
+	bus_read_region_1(sc->sc_res[GEM_RES_BANK1],
+	    GEM_PCI_ROM_OFFSET + j + PCI_VPDRES_LARGE_DATA + PCI_VPD_DATA,
+	    sc->sc_enaddr, ETHER_ADDR_LEN);
 #endif
 
 	if (gem_attach(sc) != 0) {
@@ -278,8 +297,8 @@ gem_pci_attach(device_t dev)
 		goto fail;
 	}
 
-	if (bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_NET | INTR_MPSAFE,
-	    NULL, gem_intr, sc, &sc->sc_ih) != 0) {
+	if (bus_setup_intr(dev, sc->sc_res[GEM_RES_INTR], INTR_TYPE_NET |
+	    INTR_MPSAFE, NULL, gem_intr, sc, &sc->sc_ih) != 0) {
 		device_printf(dev, "failed to set up interrupt\n");
 		gem_detach(sc);
 		goto fail;
@@ -287,6 +306,8 @@ gem_pci_attach(device_t dev)
 	return (0);
 
  fail:
+	if (sc->sc_res[GEM_RES_BANK2] != NULL)
+		free(sc->sc_res[GEM_RES_BANK2], M_DEVBUF);
 	GEM_LOCK_DESTROY(sc);
 	bus_release_resources(dev, gem_pci_res_spec, sc->sc_res);
 	return (ENXIO);
@@ -298,8 +319,9 @@ gem_pci_detach(device_t dev)
 	struct gem_softc *sc;
 
 	sc = device_get_softc(dev);
-	bus_teardown_intr(dev, sc->sc_res[1], sc->sc_ih);
+	bus_teardown_intr(dev, sc->sc_res[GEM_RES_INTR], sc->sc_ih);
 	gem_detach(sc);
+	free(sc->sc_res[GEM_RES_BANK2], M_DEVBUF);
 	GEM_LOCK_DESTROY(sc);
 	bus_release_resources(dev, gem_pci_res_spec, sc->sc_res);
 	return (0);
diff --git a/sys/dev/gem/if_gemreg.h b/sys/dev/gem/if_gemreg.h
index 569236f..f77ddac 100644
--- a/sys/dev/gem/if_gemreg.h
+++ b/sys/dev/gem/if_gemreg.h
@@ -24,7 +24,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- *	from: NetBSD: gemreg.h,v 1.8 2005/12/11 12:21:26 christos Exp
+ *	from: NetBSD: gemreg.h,v 1.9 2006/11/24 13:01:07 martin Exp
  *
  * $FreeBSD$
  */
@@ -34,6 +34,11 @@
 
 /* Register definitions for Sun GEM gigabit ethernet */
 
+/*
+ * First bank: this registers live at the start of the PCI
+ * mapping, and at the start of the second bank of the SBus
+ * version.
+ */
 #define	GEM_SEB_STATE		0x0000	/* SEB state reg, R/O */
 #define	GEM_CONFIG		0x0004	/* config reg */
 #define	GEM_STATUS		0x000c	/* status reg */
@@ -41,18 +46,30 @@
 #define	GEM_INTMASK		0x0010
 #define	GEM_INTACK		0x0014	/* Interrupt acknowledge, W/O */
 #define	GEM_STATUS_ALIAS	0x001c
+
+/*
+ * Second bank: this registers live at offset 0x1000 of the PCI
+ * mapping, and at the start of the first bank of the SBus
+ * version.
+ */
+#define	GEM_PCI_BANK2_OFFSET	0x1000
+#define	GEM_PCI_BANK2_SIZE	0x14
 /* This is the same as the GEM_STATUS reg but reading it does not clear bits. */
-#define	GEM_ERROR_STATUS	0x1000	/* PCI error status R/C */
-#define	GEM_ERROR_MASK		0x1004
-#define	GEM_BIF_CONFIG		0x1008	/* BIF config reg */
-#define	GEM_BIF_DIAG		0x100c
-#define	GEM_RESET		0x1010	/* Software reset register */
+#define	GEM_ERROR_STATUS	0x0000	/* PCI error status R/C */
+#define	GEM_ERROR_MASK		0x0004
+#define	GEM_SBUS_CONFIG		0x0004
+#define	GEM_BIF_CONFIG		0x0008	/* BIF config reg */
+#define	GEM_BIF_DIAG		0x000c
+#define	GEM_RESET		0x0010	/* Software reset register */
 
 
 /* Bits in GEM_SEB register */
 #define	GEM_SEB_ARB		0x000000002	/* Arbitration status */
 #define	GEM_SEB_RXWON		0x000000004
 
+/* Bits in GEM_SBUS_CONFIG register */
+#define	GEM_SBUS_CFG_BMODE64	0x00000008
+#define	GEM_SBUS_CFG_PARITY	0x00000200
 
 /* Bits in GEM_CONFIG register */
 #define	GEM_CONFIG_BURST_64	0x000000000	/* maximum burst size 64KB */
@@ -119,6 +136,7 @@
 #define	GEM_RESET_RSTOUT	0x000000004	/* Force PCI RSTOUT# */
 
 
+/* The rest of the registers live in the first bank again. */
 /* GEM TX DMA registers */
 #define	GEM_TX_KICK		0x2000		/* Write last valid desc + 1 */
 #define	GEM_TX_CONFIG		0x2004
diff --git a/sys/dev/gem/if_gemvar.h b/sys/dev/gem/if_gemvar.h
index 5a2952f..76e2b20 100644
--- a/sys/dev/gem/if_gemvar.h
+++ b/sys/dev/gem/if_gemvar.h
@@ -115,7 +115,11 @@ struct gem_softc {
 	int		sc_wdog_timer;	/* watchdog timer */
 
 	void		*sc_ih;
-	struct resource *sc_res[2];
+	struct resource *sc_res[3];
+#define	GEM_RES_INTR		0
+#define	GEM_RES_BANK1		1
+#define	GEM_RES_BANK2		2
+
 	bus_dma_tag_t	sc_pdmatag;	/* parent bus DMA tag */
 	bus_dma_tag_t	sc_rdmatag;	/* RX bus DMA tag */
 	bus_dma_tag_t	sc_tdmatag;	/* TX bus DMA tag */
@@ -176,6 +180,43 @@ struct gem_softc {
 	int		sc_csum_features;
 };
 
+#define	GEM_BANKN_BARRIER(n, sc, offs, len, flags)			\
+	bus_barrier((sc)->sc_res[(n)], (offs), (len), (flags))
+#define	GEM_BANK1_BARRIER(sc, offs, len, flags)				\
+	GEM_BANKN_BARRIER(GEM_RES_BANK1, (sc), (offs), (len), (flags))
+#define	GEM_BANK2_BARRIER(sc, offs, len, flags)				\
+	GEM_BANKN_BARRIER(GEM_RES_BANK2, (sc), (offs), (len), (flags))
+
+#define	GEM_BANKN_READ_M(n, m, sc, offs)				\
+	bus_read_ ## m((sc)->sc_res[(n)], (offs))
+#define	GEM_BANK1_READ_1(sc, offs)					\
+	GEM_BANKN_READ_M(GEM_RES_BANK1, 1, (sc), (offs))
+#define	GEM_BANK1_READ_2(sc, offs)					\
+	GEM_BANKN_READ_M(GEM_RES_BANK1, 2, (sc), (offs))
+#define	GEM_BANK1_READ_4(sc, offs)					\
+	GEM_BANKN_READ_M(GEM_RES_BANK1, 4, (sc), (offs))
+#define	GEM_BANK2_READ_1(sc, offs)					\
+	GEM_BANKN_READ_M(GEM_RES_BANK2, 1, (sc), (offs))
+#define	GEM_BANK2_READ_2(sc, offs)					\
+	GEM_BANKN_READ_M(GEM_RES_BANK2, 2, (sc), (offs))
+#define	GEM_BANK2_READ_4(sc, offs)					\
+	GEM_BANKN_READ_M(GEM_RES_BANK2, 4, (sc), (offs))
+
+#define	GEM_BANKN_WRITE_M(n, m, sc, offs, v)				\
+	bus_write_ ## m((sc)->sc_res[n], (offs), (v))
+#define	GEM_BANK1_WRITE_1(sc, offs, v)					\
+	GEM_BANKN_WRITE_M(GEM_RES_BANK1, 1, (sc), (offs), (v))
+#define	GEM_BANK1_WRITE_2(sc, offs, v)					\
+	GEM_BANKN_WRITE_M(GEM_RES_BANK1, 2, (sc), (offs), (v))
+#define	GEM_BANK1_WRITE_4(sc, offs, v)					\
+	GEM_BANKN_WRITE_M(GEM_RES_BANK1, 4, (sc), (offs), (v))
+#define	GEM_BANK2_WRITE_1(sc, offs, v)					\
+	GEM_BANKN_WRITE_M(GEM_RES_BANK2, 1, (sc), (offs), (v))
+#define	GEM_BANK2_WRITE_2(sc, offs, v)					\
+	GEM_BANKN_WRITE_M(GEM_RES_BANK2, 2, (sc), (offs), (v))
+#define	GEM_BANK2_WRITE_4(sc, offs, v)					\
+	GEM_BANKN_WRITE_M(GEM_RES_BANK2, 4, (sc), (offs), (v))
+
 /* XXX this should be handled by bus_dma(9). */
 #define	GEM_DMA_READ(sc, v)						\
 	((((sc)->sc_flags & GEM_PCI) != 0) ? le64toh(v) : be64toh(v))