Device driver for Intel Pro/100 PCI Fast Ethernet controller.

2 files changed, 1313 insertions, 0 deletions

diff --git a/sys/dev/fxp/if_fxp.c b/sys/dev/fxp/if_fxp.c
new file mode 100644
index 0000000..ff895e7
--- /dev/null
+++ b/sys/dev/fxp/if_fxp.c
@@ -0,0 +1,1036 @@
+/*
+ * Copyright (c) 1995, David Greenman
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice unmodified, this list of conditions, and the following
+ *    disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by David Greenman.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	$Id$
+ */
+
+/*
+ * Intel EtherExpress Pro/100 PCI Fast Ethernet driver
+ */
+
+#include "bpfilter.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/ioctl.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/devconf.h>
+#include <sys/syslog.h>
+
+#include <net/if.h>
+#include <net/if_dl.h>
+#include <net/if_types.h>
+
+#ifdef INET
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/ip.h>
+#include <netinet/if_ether.h>
+#endif
+
+#ifdef IPX
+#include <netipx/ipx.h>
+#include <netipx/ipx_if.h>
+#endif
+
+#ifdef NS
+#include <netns/ns.h>
+#include <netns/ns_if.h>
+#endif
+
+#if NBPFILTER > 0
+#include <net/bpf.h>
+#include <net/bpfdesc.h>
+#endif
+
+#include <vm/vm.h>
+#include <vm/vm_param.h>
+#include <machine/clock.h>
+#include <machine/pmap.h>
+
+#include <pci/pcivar.h>
+#include <pci/if_fxpreg.h>
+
+struct fxp_softc {
+	struct arpcom arpcom;
+	caddr_t bpf;
+	struct fxp_csr *csr;
+	struct fxp_cb_tx *cbl_base;	/* base of TxCB list */
+	struct fxp_cb_tx *cbl_first;	/* first active TxCB in list */
+	struct fxp_cb_tx *cbl_last;	/* last active TxCB in list */
+	struct mbuf *rfa_headm;		/* first mbuf in receive frame area */
+	struct mbuf *rfa_tailm;		/* last mbuf in receive frame area */
+	struct fxp_stats *fxp_stats;	/* Pointer to interface stats */
+	int tx_queued;			/* # of active TxCB's */
+	int promisc_mode;		/* promiscuous mode enabled */
+};
+
+#include "fxp.h"
+static struct fxp_softc *fxp_sc[NFXP];	/* XXX Yuck */
+
+static u_long fxp_count;
+
+/*
+ * Template for default configuration parameters.
+ * See struct fxp_cb_config for the bit definitions.
+ */
+static u_char fxp_cb_config_template[] = {
+	0x0, 0x0,		/* cb_status */
+	0x80, 0x2,		/* cb_command */
+	0xff, 0xff, 0xff, 0xff,	/* link_addr */
+	0x16,	/*  0 */
+	0x8,	/*  1 */
+	0x0,	/*  2 */
+	0x0,	/*  3 */
+	0x0,	/*  4 */
+	0x80,	/*  5 */
+	0xb2,	/*  6 */
+	0x3,	/*  7 */
+	0x1,	/*  8 */
+	0x0,	/*  9 */
+	0x26,	/* 10 */
+	0x0,	/* 11 */
+	0x60,	/* 12 */
+	0x0,	/* 13 */
+	0xf2,	/* 14 */
+	0x48,	/* 15 */
+	0x0,	/* 16 */
+	0x40,	/* 17 */
+	0xf3,	/* 18 */
+	0x0,	/* 19 */
+	0x3f,	/* 20 */
+	0x5,	/* 21 */
+	0x0, 0x0
+};
+
+static char *fxp_probe		__P((pcici_t, pcidi_t));
+static void fxp_attach		__P((pcici_t, int));
+static int fxp_shutdown		__P((struct kern_devconf *, int));
+static int fxp_intr		__P((void *));
+static void fxp_start		__P((struct ifnet *));
+static int fxp_ioctl		__P((struct ifnet *, int, caddr_t));
+static void fxp_init		__P((int));
+static void fxp_stop		__P((int));
+static void fxp_watchdog	__P((int));
+static void fxp_get_macaddr	__P((struct fxp_softc *));
+static int fxp_add_rfabuf	__P((struct fxp_softc *, struct mbuf *));
+
+timeout_t fxp_stats_update;
+
+static struct pci_device fxp_device = {
+	"fxp",
+	fxp_probe,
+	fxp_attach,
+	&fxp_count,
+	fxp_shutdown
+};
+DATA_SET(pcidevice_set, fxp_device);
+
+/*
+ * Number of transmit control blocks. This determines the number
+ * of transmit buffers that can be chained in the CB list.
+ * This must be a power of two.
+ */
+#define FXP_NTXCB	64
+
+/*
+ * TxCB list index mask. This is used to do list wrap-around.
+ */
+#define FXP_TXCB_MASK	(FXP_NTXCB - 1)
+
+/*
+ * Number of DMA segments in a TxCB. Note that this is carefully
+ * chosen to make the total struct size an even power of two.
+ */
+#define FXP_NTXSEG	13
+
+/*
+ * Number of receive frame area buffers. These are large so chose
+ * wisely.
+ */
+#define FXP_NRFABUFS	32
+
+static inline void
+fxp_scb_wait(csr)
+	struct fxp_csr *csr;
+{
+	int i = 10000;
+
+	while ((csr->scb_command & FXP_SCB_COMMAND_MASK) && --i);
+}
+
+static char *
+fxp_probe(config_id, device_id)
+	pcici_t config_id;
+	pcidi_t device_id;
+{
+	if (((device_id & 0xffff) == FXP_VENDORID_INTEL) &&
+	    ((device_id >> 16) & 0xffff) == FXP_DEVICEID_i82557)
+		return ("Intel EtherExpress Pro/100 Fast Ethernet");
+
+	return NULL;
+}
+
+/*
+ * Allocate data structures and attach the device.
+ */
+static void
+fxp_attach(config_id, unit)
+	pcici_t config_id;
+	int unit;
+{
+	struct fxp_softc *sc;
+	struct ifnet *ifp;
+	vm_offset_t pbase;
+	int s, i;
+
+	sc = malloc(sizeof(struct fxp_softc), M_DEVBUF, M_NOWAIT);
+	if (sc == NULL)
+		return;
+	bzero(sc, sizeof(struct fxp_softc));
+
+	s = splimp();
+
+	if (!pci_map_mem(config_id, FXP_PCI_MMBA,
+	    (vm_offset_t *)&sc->csr, &pbase)) {
+		printf("fxp%d: couldn't map memory\n", unit);
+		goto fail;
+	}
+
+	/*
+	 * Now that the CSR is mapped, issue a software reset.
+	 */
+	sc->csr->port = 0;
+	DELAY(10);
+
+	if (!pci_map_int(config_id, fxp_intr, sc, &net_imask)) {
+		printf("fxp%d: couldn't map interrupt\n", unit);
+		goto fail;
+	}
+
+	sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB,
+	    M_DEVBUF, M_NOWAIT);
+	if (sc->cbl_base == NULL)
+		goto malloc_fail;
+
+	sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, M_NOWAIT);
+	if (sc->fxp_stats == NULL)
+		goto malloc_fail;
+	bzero(sc->fxp_stats, sizeof(struct fxp_stats));
+
+	for (i = 0; i < FXP_NRFABUFS; i++) {
+		if (fxp_add_rfabuf(sc, NULL) != 0) {
+			goto malloc_fail;
+		}
+	}
+
+	fxp_sc[unit] = sc;
+
+	ifp = &sc->arpcom.ac_if;
+	ifp->if_unit = unit;
+	ifp->if_name = "fxp";
+	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+	ifp->if_ioctl = fxp_ioctl;
+	ifp->if_output = ether_output;
+	ifp->if_start = fxp_start;
+	ifp->if_watchdog = fxp_watchdog;
+
+	fxp_get_macaddr(sc);
+	printf("fxp%d: Ethernet address %s\n", unit,
+	    ether_sprintf(sc->arpcom.ac_enaddr));
+
+	if_attach(ifp);
+#if NBPFILTER > 0
+	bpfattach(&sc->bpf, ifp, DLT_EN10MB, sizeof(struct ether_header));
+#endif
+	splx(s);
+	return;
+
+malloc_fail:
+	printf("fxp%d: Failed to malloc memory\n", unit);
+	(void) pci_unmap_int(config_id);
+	if (sc && sc->cbl_base)
+		free(sc->cbl_base, M_DEVBUF);
+	if (sc && sc->fxp_stats)
+		free(sc->fxp_stats, M_DEVBUF);
+	/* frees entire chain */
+	if (sc && sc->rfa_headm)
+		m_freem(sc->rfa_headm);
+fail:
+	if (sc)
+		free(sc, M_DEVBUF);
+	splx(s);
+}
+
+/*
+ * Read station (MAC) address from serial EEPROM. Basically, you
+ * manually shift in the read opcode (one bit at a time) and then
+ * shift in the address, and then you shift out the data (all of
+ * this one bit at a time). The word size is 16 bits, so you have
+ * to provide the address for every 16 bits of data. The MAC address
+ * is in the first 3 words (6 bytes total).
+ */
+static void
+fxp_get_macaddr(sc)
+	struct fxp_softc *sc;
+{
+	struct fxp_csr *csr;
+	u_short reg, *data;
+	int i, x;
+
+	csr = sc->csr;
+	data = (u_short *)sc->arpcom.ac_enaddr;
+
+	for (i = 0; i < 3; i++) {
+		csr->eeprom_control = FXP_EEPROM_EECS;
+		/*
+		 * Shift in read opcode.
+		 */
+		for (x = 3; x > 0; x--) {
+			if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) {
+				reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
+			} else {
+				reg = FXP_EEPROM_EECS;
+			}
+			csr->eeprom_control = reg;
+			csr->eeprom_control = reg | FXP_EEPROM_EESK;
+			DELAY(1);
+			csr->eeprom_control = reg;
+			DELAY(1);
+		}
+		/*
+		 * Shift in address.
+		 */
+		for (x = 6; x > 0; x--) {
+			if (i & (1 << (x - 1))) {
+				reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
+			} else {
+				reg = FXP_EEPROM_EECS;
+			}
+			csr->eeprom_control = reg;
+			csr->eeprom_control = reg | FXP_EEPROM_EESK;
+			DELAY(1);
+			csr->eeprom_control = reg;
+			DELAY(1);
+		}
+		reg = FXP_EEPROM_EECS;
+		data[i] = 0;
+		/*
+		 * Shift out data.
+		 */
+		for (x = 16; x > 0; x--) {
+			csr->eeprom_control = reg | FXP_EEPROM_EESK;
+			DELAY(1);
+			if (csr->eeprom_control & FXP_EEPROM_EEDO)
+				data[i] |= (1 << (x - 1));
+			csr->eeprom_control = reg;
+			DELAY(1);
+		}
+		csr->eeprom_control = 0;
+		DELAY(1);
+	}
+}
+
+/*
+ * Device shutdown routine. Usually called at system shutdown. The
+ * main purpose of this routine is to shut off receiver DMA so that
+ * kernel memory doesn't get clobbered during warmboot.
+ */
+static int
+fxp_shutdown(kdc, force)
+	struct kern_devconf *kdc;
+	int force;
+{
+	struct fxp_softc *sc = fxp_sc[kdc->kdc_unit];
+	
+	/*
+	 * Cancel stats updater.
+	 */
+	untimeout(fxp_stats_update, sc);
+	/*
+	 * Issue software reset.
+	 */
+	sc->csr->port = 0;
+
+	(void) dev_detach(kdc);
+	return 0;
+}
+
+/*
+ * Start packet transmission on the interface.
+ */
+static void
+fxp_start(ifp)
+	struct ifnet *ifp;
+{
+	struct fxp_softc *sc = fxp_sc[ifp->if_unit];
+	struct fxp_csr *csr = sc->csr;
+	struct fxp_cb_tx *txp;
+	struct mbuf *m, *mb_head;
+	int segment;
+
+txloop:
+	/*
+	 * See if a TxCB is available. If not, indicate this to the
+	 * outside world and exit.
+	 */
+	if (sc->tx_queued >= FXP_NTXCB) {
+		ifp->if_flags |= IFF_OACTIVE;
+		return;
+	}
+	IF_DEQUEUE(&sc->arpcom.ac_if.if_snd, mb_head);
+	if (mb_head == NULL) {
+		/*
+		 * No more packets to send.
+		 */
+		return;
+	}
+
+	txp = sc->cbl_last->next;
+
+	/*
+	 * Go through each of the mbufs in the chain and initialize
+	 * the transmit buffers descriptors with the physical address
+	 * and size of the mbuf.
+	 */
+	for (m = mb_head, segment = 0; m != NULL; m = m->m_next) {
+		if (m->m_len != 0) {
+			if (segment == FXP_NTXSEG)
+				break;
+			txp->tbd[segment].tb_addr =
+			    vtophys(mtod(m, vm_offset_t));
+			txp->tbd[segment].tb_size = m->m_len;
+			segment++;
+		}
+	}
+	if (m != NULL && segment == FXP_NTXSEG) {
+		/*
+		 * We ran out of segments. We have to recopy this mbuf
+		 * chain first.
+		 */
+		panic("fxp%d: ran out of segments", ifp->if_unit);
+	} else {
+		txp->tbd_number = segment;
+	}
+	/*
+	 * Finish the initialization of this TxCB.
+	 */
+	txp->cb_status = 0;
+	txp->cb_command =
+	    FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | FXP_CB_COMMAND_S;
+	txp->tx_threshold = 16;	/* bytes*8 */
+	txp->mb_head = mb_head;
+	
+	/*
+	 * Advance the end-of-list forward.
+	 */
+	sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
+	sc->cbl_last = txp;
+
+	/*
+	 * If no packets were previously queued then advance the first
+	 * pointer to this TxCB.
+	 */
+	if (sc->tx_queued++ == 0) {
+		sc->cbl_first = txp;
+	}
+
+	/*
+	 * Resume transmission if suspended.
+	 */
+	fxp_scb_wait(csr);
+	csr->scb_command = FXP_SCB_COMMAND_CU_RESUME;
+
+#if NBPFILTER > 0
+	/*
+	 * Pass packet to bpf if there is a listener.
+	 */
+	if (sc->bpf != NULL)
+		bpf_mtap(sc->bpf, mb_head);
+#endif
+	/*
+	 * Set a 5 second timer just in case we don't hear from the
+	 * card again.
+	 */
+	ifp->if_timer = 5;
+
+	goto txloop;
+}
+
+/*
+ * Process interface interrupts. Returns 1 if the interrupt
+ * was handled, 0 if it wasn't.
+ */
+static int
+fxp_intr(arg)
+	void *arg;
+{
+	struct fxp_softc *sc = arg;
+	struct fxp_csr *csr = sc->csr;
+	struct ifnet *ifp = &sc->arpcom.ac_if;
+	int found = 0;
+	u_char statack;
+
+	while ((statack = csr->scb_statack) != 0) {
+		found = 1;
+		/*
+		 * First ACK all the interrupts in this pass.
+		 */
+		csr->scb_statack = statack;
+
+		/*
+		 * Free any finished transmit mbuf chains.
+		 */
+		if (statack & FXP_SCB_STATACK_CNA) {
+			struct fxp_cb_tx *txp;
+
+			for (txp = sc->cbl_first;
+			    (txp->cb_status & FXP_CB_STATUS_C) &&
+			    txp->mb_head != NULL;
+			    txp = txp->next) {
+				m_freem(txp->mb_head);
+				txp->mb_head = NULL;
+				sc->tx_queued--;
+			}
+			sc->cbl_first = txp;
+			/*
+			 * We unconditionally clear IFF_OACTIVE since it
+			 * doesn't hurt to do so even if the tx queue is
+			 * still full - it will just get set again in
+			 * fxp_start(). If we get a CNA interrupt, it is
+			 * (almost?) certain that we've freed up space for
+			 * at least one more packet.
+			 */
+			ifp->if_flags &= ~IFF_OACTIVE;
+			/*
+			 * Clear watchdog timer. It may or may not be set
+			 * again in fxp_start().
+			 */
+			ifp->if_timer = 0;
+			fxp_start(ifp);
+		}
+		/*
+		 * Process receiver interrupts. If a no-resource (RNR)
+		 * condition exists, get whatever packets we can and
+		 * re-start the receiver.
+		 */
+		if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) {
+			struct mbuf *m;
+			struct fxp_rfa *rfa;
+rcvloop:
+			m = sc->rfa_headm;
+			rfa = (struct fxp_rfa *)(mtod(m, u_long) & ~(MCLBYTES - 1));
+
+			if (rfa->rfa_status & FXP_RFA_STATUS_C) {
+				sc->rfa_headm = m->m_next;
+				m->m_next = NULL;
+
+				if (fxp_add_rfabuf(sc, m) == 0) {
+					struct ether_header *eh;
+					u_short total_len;
+
+					total_len = rfa->actual_size & (MCLBYTES - 1);
+					m->m_pkthdr.rcvif = ifp;
+					m->m_pkthdr.len = m->m_len = total_len -
+					    sizeof(struct ether_header);
+					eh = mtod(m, struct ether_header *);
+#if NBPFILTER > 0
+					if (sc->bpf != NULL) {
+						bpf_tap(sc->bpf, mtod(m, caddr_t), total_len);
+						/*
+						 * Only pass this packet up if it is for us.
+						 */
+						if ((ifp->if_flags & IFF_PROMISC) &&
+						    (rfa->rfa_status & FXP_RFA_STATUS_IAMATCH) &&
+						    (eh->ether_dhost[0] & 1) == 0) {
+							m_freem(m);
+							goto rcvloop;
+						}
+					}
+#endif
+					m->m_data += sizeof(struct ether_header);
+					ether_input(ifp, eh, m);
+				}
+				goto rcvloop;
+			}
+			if (statack & FXP_SCB_STATACK_RNR) {
+				struct fxp_csr *csr = sc->csr;
+
+				ifp->if_ierrors++;
+				fxp_scb_wait(csr);
+				csr->scb_general = vtophys(mtod(sc->rfa_headm, u_long) &
+				    ~(MCLBYTES - 1));
+				csr->scb_command = FXP_SCB_COMMAND_RU_START;
+			}
+		}
+	}
+
+	return found;
+}
+
+void
+fxp_stats_update(arg)
+	void *arg;
+{
+	struct fxp_softc *sc = arg;
+	struct ifnet *ifp = &sc->arpcom.ac_if;
+	struct fxp_stats *sp = sc->fxp_stats;
+
+	ifp->if_opackets += sp->tx_good;
+	ifp->if_collisions += sp->tx_total_collisions;
+	ifp->if_ipackets += sp->rx_good;
+	/*
+	 * If there is a pending command, don't wait for it to
+	 * be accepted - we'll pick up the stats the next time
+	 * around. Make sure we don't count the stats twice
+	 * however.
+	 */
+	if (sc->csr->scb_command & FXP_SCB_COMMAND_MASK) {
+		sp->tx_good = 0;
+		sp->tx_total_collisions = 0;
+		sp->rx_good = 0;
+		return;
+	}
+	/*
+	 * Start another stats dump. By waiting for it to be accepted,
+	 * we avoid having to do splhigh locking when writing scb_command
+	 * in other parts of the driver.
+	 */
+	sc->csr->scb_command = FXP_SCB_COMMAND_CU_DUMPRESET;
+	fxp_scb_wait(sc);
+	/*
+	 * Schedule another timeout one second from now.
+	 */
+	timeout(fxp_stats_update, sc, hz);
+}
+
+/*
+ * Stop the interface. Cancels the statistics updater and resets
+ * the interface.
+ */
+static void
+fxp_stop(unit)
+	int unit;
+{
+	struct fxp_softc *sc = fxp_sc[unit];
+	struct ifnet *ifp = &sc->arpcom.ac_if;
+
+	/*
+	 * Cancel stats updater.
+	 */
+	untimeout(fxp_stats_update, sc);
+	sc->csr->port = 0;
+	DELAY(10);
+
+	ifp->if_flags &= ~IFF_RUNNING;
+}
+
+/*
+ * Watchdog/transmission transmit timeout handler. Called when a
+ * transmission is started on the interface, but no interrupt is
+ * received before the timeout. This usually indicates that the
+ * card has wedged for some reason.
+ */
+static void
+fxp_watchdog(unit)
+	int unit;
+{
+	struct fxp_softc *sc = fxp_sc[unit];
+	struct ifnet *ifp = &sc->arpcom.ac_if;
+
+	log(LOG_ERR, "fxp%d: device timeout\n", unit);
+	++sc->arpcom.ac_if.if_oerrors;
+
+	fxp_stop(unit);
+	fxp_init(unit);
+}
+
+static void
+fxp_init(unit)
+	int unit;
+{
+	struct fxp_softc *sc = fxp_sc[unit];
+	struct ifnet *ifp = &sc->arpcom.ac_if;
+	struct fxp_cb_config *cbp;
+	struct fxp_cb_ias *cb_ias;
+	struct fxp_cb_tx *txp;
+	struct fxp_csr *csr = sc->csr;
+	int i, s, mcast, prm;
+
+	/*
+	 * Cancel stats updater.
+	 */
+	untimeout(fxp_stats_update, sc);
+
+	s = splimp();
+	/*
+	 * Issue software reset and wait 10us for the card to recover.
+	 */
+	csr->port = 0;
+	DELAY(10);
+
+	prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
+	sc->promisc_mode = prm;
+	/*
+	 * Sleeze out here and enable reception of all multicasts if
+	 * multicasts are enabled. Ideally, we'd program the multicast
+	 * address filter to only accept specific multicasts.
+	 */
+	mcast = (ifp->if_flags & (IFF_MULTICAST|IFF_ALLMULTI)) ? 1 : 0;
+
+	/*
+	 * Initialize base of CBL and RFA memory. Loading with zero
+	 * sets it up for regular linear addressing.
+	 */
+	csr->scb_general = 0;
+	csr->scb_command = FXP_SCB_COMMAND_CU_BASE;
+
+	fxp_scb_wait(csr);
+	csr->scb_command = FXP_SCB_COMMAND_RU_BASE;
+
+	/*
+	 * Initialize base of dump-stats buffer.
+	 */
+	fxp_scb_wait(csr);
+	csr->scb_general = vtophys(sc->fxp_stats);
+	csr->scb_command = FXP_SCB_COMMAND_CU_DUMP_ADR;
+
+	/*
+	 * We temporarily use memory that contains the TxCB list to
+	 * construct the config CB. The TxCB list memory is rebuilt
+	 * later.
+	 */
+	cbp = (struct fxp_cb_config *) sc->cbl_base;
+
+	/*
+	 * This bcopy is kind of disgusting, but there are a bunch of must be
+	 * zero and must be one bits in this structure and this is the easiest
+	 * way to initialize them all to proper values.
+	 */
+	bcopy(fxp_cb_config_template, cbp, sizeof(struct fxp_cb_config));
+
+	cbp->cb_status =	0;
+	cbp->cb_command =	FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL;
+	cbp->link_addr =	-1;	/* (no) next command */
+	cbp->byte_count =	22;	/* (22) bytes to config */
+	cbp->rx_fifo_limit =	8;	/* rx fifo threshold */
+	cbp->tx_fifo_limit =	0;	/* tx fifo threshold */
+	cbp->adaptive_ifs =	0;	/* (no) adaptive interframe spacing */
+	cbp->rx_dma_bytecount =	0;	/* (no) rx DMA max */
+	cbp->tx_dma_bytecount =	0;	/* (no) tx DMA max */
+	cbp->dma_bce =		1;	/* (enable) dma max counters */
+	cbp->late_scb =		0;	/* (don't) defer SCB update */
+	cbp->tno_int =		0;	/* (disable) tx not okay interrupt */
+	cbp->ci_int =		0;	/* (do) interrupt on CU not active */
+	cbp->save_bf =		prm;	/* save bad frames */
+	cbp->disc_short_rx =	!prm;	/* discard short packets */
+	cbp->underrun_retry =	1;	/* retry mode (1) on DMA underrun */
+	cbp->mediatype =	1;	/* (MII) interface mode */
+	cbp->nsai =		1;	/* (don't) disable source addr insert */
+	cbp->preamble_length =	2;	/* (7 byte) preamble */
+	cbp->loopback =		0;	/* (don't) loopback */
+	cbp->linear_priority =	0;	/* (normal CSMA/CD operation) */
+	cbp->linear_pri_mode =	0;	/* (wait after xmit only) */
+	cbp->interfrm_spacing =	6;	/* (96 bits of) interframe spacing */
+	cbp->promiscuous =	prm;	/* promiscuous mode */
+	cbp->bcast_disable =	0;	/* (don't) disable broadcasts */
+	cbp->crscdt =		0;	/* (CRS only) */
+	cbp->stripping =	!prm;	/* truncate rx packet to byte count */
+	cbp->padding =		1;	/* (do) pad short tx packets */
+	cbp->rcv_crc_xfer =	0;	/* (don't) xfer CRC to host */
+	cbp->force_fdx =	0;	/* (don't) force full duplex */
+	cbp->fdx_pin_en =	0;	/* (ignore) FDX# pin */
+	cbp->multi_ia =		0;	/* (don't) accept multiple IAs */
+	cbp->mc_all =		mcast;	/* accept all multicasts */
+
+	/*
+	 * Start the config command/DMA.
+	 */
+	fxp_scb_wait(csr);
+	csr->scb_general = vtophys(cbp);
+	csr->scb_command = FXP_SCB_COMMAND_CU_START;
+	/* ...and wait for it to complete. */
+	while (!(cbp->cb_status & FXP_CB_STATUS_C));
+
+	/*
+	 * Now initialize the station address. Temporarily use the TxCB
+	 * memory area like we did above for the config CB.
+	 */
+	cb_ias = (struct fxp_cb_ias *) sc->cbl_base;
+	cb_ias->cb_status = 0;
+	cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL;
+	cb_ias->link_addr = -1;
+	bcopy(sc->arpcom.ac_enaddr, (void *)cb_ias->macaddr,
+	    sizeof(sc->arpcom.ac_enaddr));
+
+	/*
+	 * Start the IAS (Individual Address Setup) command/DMA.
+	 */
+	fxp_scb_wait(csr);
+	csr->scb_command = FXP_SCB_COMMAND_CU_START;
+	/* ...and wait for it to complete. */
+	while (!(cb_ias->cb_status & FXP_CB_STATUS_C));
+
+	/*
+	 * Initialize transmit control block (TxCB) list.
+	 */
+
+	txp = sc->cbl_base;
+	bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
+	for (i = 0; i < FXP_NTXCB; i++) {
+		txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK;
+		txp[i].cb_command = FXP_CB_COMMAND_NOP;
+		txp[i].link_addr = vtophys(&txp[(i + 1) & FXP_TXCB_MASK]);
+		txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]);
+		txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK];
+	}
+	/*
+	 * Set the stop flag on the first TxCB and start the control
+	 * unit. It will execute the NOP and then suspend.
+	 */
+	txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S;
+	sc->cbl_first = sc->cbl_last = txp;
+	sc->tx_queued = 0;
+
+	fxp_scb_wait(csr);
+	csr->scb_command = FXP_SCB_COMMAND_CU_START;
+
+	/*
+	 * Initialize receiver buffer area - RFA.
+	 */
+	fxp_scb_wait(csr);
+	csr->scb_general = vtophys(mtod(sc->rfa_headm, u_long) & ~(MCLBYTES - 1));
+	csr->scb_command = FXP_SCB_COMMAND_RU_START;
+
+	ifp->if_flags |= IFF_RUNNING;
+	ifp->if_flags &= ~IFF_OACTIVE;
+	splx(s);
+
+	/*
+	 * Start stats updater.
+	 */
+	timeout(fxp_stats_update, sc, hz);
+}
+
+/*
+ * Add a buffer to the end of the RFA buffer list.
+ * Return 0 if successful, 1 for failure. A failure results in
+ * adding the 'oldm' (if non-NULL) on to the end of the list -
+ * tossing out it's old contents and recycling it.
+ * The RFA struct is stuck at the beginning of mbuf cluster and the
+ * data pointer is fixed up to point just past it.
+ */
+static int
+fxp_add_rfabuf(sc, oldm)
+	struct fxp_softc *sc;
+	struct mbuf *oldm;
+{
+	struct mbuf *m;
+	struct fxp_rfa *rfa, *p_rfa;
+
+	MGETHDR(m, M_DONTWAIT, MT_DATA);
+	if (m != NULL) {
+		MCLGET(m, M_DONTWAIT);
+		if ((m->m_flags & M_EXT) == 0) {
+			m_freem(m);
+			m = oldm;
+		}
+	} else {
+		m = oldm;
+	}
+	if (m == NULL)
+		return 1;
+	rfa = mtod(m, struct fxp_rfa *);
+	rfa->rfa_status = 0;
+	rfa->rfa_control = FXP_RFA_CONTROL_EL;
+	rfa->link_addr = -1;
+	rfa->rbd_addr = -1;
+	rfa->actual_size = 0;
+	rfa->size = MCLBYTES - sizeof(struct fxp_rfa);
+	m->m_data += sizeof(struct fxp_rfa);
+	if (sc->rfa_headm != NULL) {
+		p_rfa = (struct fxp_rfa *) (mtod(sc->rfa_tailm, u_long) & ~(MCLBYTES - 1));
+		sc->rfa_tailm->m_next = m;
+		p_rfa->link_addr = vtophys(rfa);
+		p_rfa->rfa_control &= ~FXP_RFA_CONTROL_EL;
+	} else {
+		sc->rfa_headm = m;
+	}
+	sc->rfa_tailm = m;
+
+	return m == oldm ? 1 : 0;
+}
+
+static int
+fxp_ioctl(ifp, command, data)
+	struct ifnet *ifp;
+	int command;
+	caddr_t data;
+{
+	struct ifaddr *ifa = (struct ifaddr *) data;
+	struct fxp_softc *sc = fxp_sc[ifp->if_unit];
+	struct ifreq *ifr = (struct ifreq *) data;
+	int s, error = 0;
+
+	s = splimp();
+
+	switch (command) {
+
+	case SIOCSIFADDR:
+		ifp->if_flags |= IFF_UP;
+
+		switch (ifa->ifa_addr->sa_family) {
+#ifdef INET
+		case AF_INET:
+			fxp_init(ifp->if_unit);	/* before arpwhohas */
+			arp_ifinit((struct arpcom *)ifp, ifa);
+			break;
+#endif
+#ifdef IPX
+		/*
+		 * XXX - This code is probably wrong
+		 */
+		case AF_IPX:
+			{
+				register struct ipx_addr *ina = &(IA_SIPX(ifa)->sipx_addr);
+
+				if (ipx_nullhost(*ina))
+					ina->x_host =
+					    *(union ipx_host *) (sc->arpcom.ac_enaddr);
+				else {
+					bcopy((caddr_t) ina->x_host.c_host,
+					      (caddr_t) sc->arpcom.ac_enaddr,
+					      sizeof(sc->arpcom.ac_enaddr));
+				}
+
+				/*
+				 * Set new address
+				 */
+				fxp_init(ifp->if_unit);
+				break;
+			}
+#endif
+#ifdef NS
+		/*
+		 * XXX - This code is probably wrong
+		 */
+		case AF_NS:
+			{
+				register struct ns_addr *ina = &(IA_SNS(ifa)->sns_addr);
+
+				if (ns_nullhost(*ina))
+					ina->x_host =
+					    *(union ns_host *) (sc->arpcom.ac_enaddr);
+				else {
+					bcopy((caddr_t) ina->x_host.c_host,
+					      (caddr_t) sc->arpcom.ac_enaddr,
+					      sizeof(sc->arpcom.ac_enaddr));
+				}
+
+				/*
+				 * Set new address
+				 */
+				fxp_init(ifp->if_unit);
+				break;
+			}
+#endif
+		default:
+			fxp_init(ifp->if_unit);
+			break;
+		}
+		break;
+
+	case SIOCGIFADDR:
+		{
+			struct sockaddr *sa;
+
+			sa = (struct sockaddr *) & ifr->ifr_data;
+			bcopy((caddr_t) sc->arpcom.ac_enaddr,
+			      (caddr_t) sa->sa_data, sizeof(sc->arpcom.ac_enaddr));
+		}
+		break;
+
+	case SIOCSIFFLAGS:
+
+		/*
+		 * If interface is marked up and not running, then start it.
+		 * If it is marked down and running, stop it.
+		 * XXX If it's up then re-initialize it. This is so flags
+		 * such as IFF_PROMISC are handled.
+		 */
+		if (ifp->if_flags & IFF_UP) {
+			fxp_init(ifp->if_unit);
+		} else {
+			if (ifp->if_flags & IFF_RUNNING)
+				fxp_stop(ifp->if_unit);
+		}
+		break;
+
+	case SIOCADDMULTI:
+	case SIOCDELMULTI:
+		/*
+		 * Update out multicast list.
+		 */
+		error = (command == SIOCADDMULTI) ?
+		    ether_addmulti(ifr, &sc->arpcom) :
+		    ether_delmulti(ifr, &sc->arpcom);
+
+		if (error == ENETRESET) {
+			/*
+			 * Multicast list has changed; set the hardware filter
+			 * accordingly.
+			 */
+			fxp_init(ifp->if_unit);
+
+			error = 0;
+		}
+		break;
+
+	case SIOCSIFMTU:
+		/*
+		 * Set the interface MTU.
+		 */
+		if (ifr->ifr_mtu > ETHERMTU) {
+			error = EINVAL;
+		} else {
+			ifp->if_mtu = ifr->ifr_mtu;
+		}
+		break;
+
+	default:
+		error = EINVAL;
+	}
+	(void) splx(s);
+	return (error);
+}
diff --git a/sys/dev/fxp/if_fxpreg.h b/sys/dev/fxp/if_fxpreg.h
new file mode 100644
index 0000000..61c3a5f
--- /dev/null
+++ b/sys/dev/fxp/if_fxpreg.h
@@ -0,0 +1,277 @@
+/*
+ * Copyright (c) 1995, David Greenman
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice unmodified, this list of conditions, and the following
+ *    disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by David Greenman.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	$Id$
+ */
+
+#define FXP_VENDORID_INTEL	0x8086
+#define FXP_DEVICEID_i82557	0x1229
+
+#define FXP_PCI_MMBA	0x10
+#define FXP_PCI_IOBA	0x14
+
+struct fxp_csr {
+	volatile u_int8_t	:2,
+				scb_rus:4,
+				scb_cus:2;
+	volatile u_int8_t	scb_statack;
+	volatile u_int8_t	scb_command;
+	volatile u_int8_t	scb_intrcntl;
+	volatile u_int32_t	scb_general;
+	volatile u_int32_t	port;
+	volatile u_int16_t	flash_control;
+	volatile u_int16_t	eeprom_control;
+	volatile u_int32_t	mdi_control;
+};
+
+#define FXP_SCB_RUS_IDLE		0
+#define FXP_SCB_RUS_SUSPENDED		1
+#define FXP_SCB_RUS_NORESOURCES		2
+#define FXP_SCB_RUS_READY		4
+#define FXP_SCB_RUS_SUSP_NORBDS		9
+#define FXP_SCB_RUS_NORES_NORBDS	10
+#define FXP_SCB_RUS_READY_NORBDS	12
+
+#define FXP_SCB_CUS_IDLE		0
+#define FXP_SCB_CUS_SUSPENDED		1
+#define FXP_SCB_CUS_ACTIVE		2
+
+#define FXP_SCB_STATACK_SWI		0x04
+#define FXP_SCB_STATACK_MDI		0x08
+#define FXP_SCB_STATACK_RNR		0x10
+#define FXP_SCB_STATACK_CNA		0x20
+#define FXP_SCB_STATACK_FR		0x40
+#define FXP_SCB_STATACK_CXTNO		0x80
+
+#define FXP_SCB_COMMAND_MASK		0xff
+#define FXP_SCB_COMMAND_CU_NOP		0x00
+#define FXP_SCB_COMMAND_CU_START	0x10
+#define FXP_SCB_COMMAND_CU_RESUME	0x20
+#define FXP_SCB_COMMAND_CU_DUMP_ADR	0x40
+#define FXP_SCB_COMMAND_CU_DUMP		0x50
+#define FXP_SCB_COMMAND_CU_BASE		0x60
+#define FXP_SCB_COMMAND_CU_DUMPRESET	0x70
+
+#define FXP_SCB_COMMAND_RU_NOP		0
+#define FXP_SCB_COMMAND_RU_START	1
+#define FXP_SCB_COMMAND_RU_RESUME	2
+#define FXP_SCB_COMMAND_RU_ABORT	4
+#define FXP_SCB_COMMAND_RU_LOADHDS	5
+#define FXP_SCB_COMMAND_RU_BASE		6
+#define FXP_SCB_COMMAND_RU_RBDRESUME	7
+
+/*
+ * Command block definitions
+ */
+struct fxp_cb_nop {
+	volatile u_int16_t cb_status;
+	volatile u_int16_t cb_command;
+	volatile u_int32_t link_addr;
+};
+struct fxp_cb_ias {
+	volatile u_int16_t cb_status;
+	volatile u_int16_t cb_command;
+	volatile u_int32_t link_addr;
+	volatile u_int8_t macaddr[6];
+};
+/* I hate bit-fields :-( */
+struct fxp_cb_config {
+	volatile u_int16_t	cb_status;
+	volatile u_int16_t	cb_command;
+	volatile u_int32_t	link_addr;
+	volatile u_int8_t	byte_count:6,
+				:2;
+	volatile u_int8_t	rx_fifo_limit:4,
+				tx_fifo_limit:3,
+				:1;
+	volatile u_int8_t	adaptive_ifs;
+	volatile u_int8_t	:8;
+	volatile u_int8_t	rx_dma_bytecount:7,
+				:1;
+	volatile u_int8_t	tx_dma_bytecount:7,
+				dma_bce:1;
+	volatile u_int8_t	late_scb:1,
+				:1,
+				tno_int:1,
+				ci_int:1,
+				:3,
+				save_bf:1;
+	volatile u_int8_t	disc_short_rx:1,
+				underrun_retry:2,
+				:5;
+	volatile u_int8_t	mediatype:1,
+				:7;
+	volatile u_int8_t	:8;
+	volatile u_int8_t	:3,
+				nsai:1,
+				preamble_length:2,
+				loopback:2;
+	volatile u_int8_t	linear_priority:3,
+				:5;
+	volatile u_int8_t	linear_pri_mode:1,
+				:3,
+				interfrm_spacing:4;
+	volatile u_int8_t	:8;
+	volatile u_int8_t	:8;
+	volatile u_int8_t	promiscuous:1,
+				bcast_disable:1,
+				:5,
+				crscdt:1;
+	volatile u_int8_t	:8;
+	volatile u_int8_t	:8;
+	volatile u_int8_t	stripping:1,
+				padding:1,
+				rcv_crc_xfer:1,
+				:5;
+	volatile u_int8_t	:6,
+				force_fdx:1,
+				fdx_pin_en:1;
+	volatile u_int8_t	:6,
+				multi_ia:1,
+				:1;
+	volatile u_int8_t	:3,
+				mc_all:1,
+				:4;
+};
+struct fxp_tbd {
+	volatile u_int32_t tb_addr;
+	volatile u_int32_t tb_size;
+};
+
+struct fxp_cb_tx {
+	volatile u_int16_t cb_status;
+	volatile u_int16_t cb_command;
+	volatile u_int32_t link_addr;
+	volatile u_int32_t tbd_array_addr;
+	volatile u_int16_t byte_count;
+	volatile u_int8_t tx_threshold;
+	volatile u_int8_t tbd_number;
+	/*
+	 * The following isn't actually part of the TxCB.
+	 */
+	volatile struct fxp_tbd tbd[13];
+	struct mbuf *mb_head;
+	struct fxp_cb_tx *next;
+};
+
+/*
+ * Control Block (CB) definitions
+ */
+
+/* status */
+#define FXP_CB_STATUS_OK	0x2000
+#define FXP_CB_STATUS_C		0x8000
+/* commands */
+#define FXP_CB_COMMAND_NOP	0x0
+#define FXP_CB_COMMAND_IAS	0x1
+#define FXP_CB_COMMAND_CONFIG	0x2
+#define FXP_CB_COMMAND_MAS	0x3
+#define FXP_CB_COMMAND_XMIT	0x4
+#define FXP_CB_COMMAND_RESRV	0x5
+#define FXP_CB_COMMAND_DUMP	0x6
+#define FXP_CB_COMMAND_DIAG	0x7
+/* command flags */
+#define FXP_CB_COMMAND_SF	0x0008	/* simple/flexible mode */
+#define FXP_CB_COMMAND_I	0x2000	/* generate interrupt on completion */
+#define FXP_CB_COMMAND_S	0x4000	/* suspend on completion */
+#define FXP_CB_COMMAND_EL	0x8000	/* end of list */
+
+/*
+ * RFA definitions
+ */
+
+struct fxp_rfa {
+	volatile u_int16_t rfa_status;
+	volatile u_int16_t rfa_control;
+	volatile u_int32_t link_addr;
+	volatile u_int32_t rbd_addr;
+	volatile u_int16_t actual_size;
+	volatile u_int16_t size;
+};
+#define FXP_RFA_STATUS_RCOL	0x0001	/* receive collision */
+#define FXP_RFA_STATUS_IAMATCH	0x0002	/* 0 = matches station address */
+#define FXP_RFA_STATUS_S4	0x0010	/* receive error from PHY */
+#define FXP_RFA_STATUS_TL	0x0020	/* type/length */
+#define FXP_RFA_STATUS_FTS	0x0080	/* frame too short */
+#define FXP_RFA_STATUS_OVERRUN	0x0100	/* DMA overrun */
+#define FXP_RFA_STATUS_RNR	0x0200	/* no resources */
+#define FXP_RFA_STATUS_ALIGN	0x0400	/* alignment error */
+#define FXP_RFA_STATUS_CRC	0x0800	/* CRC error */
+#define FXP_RFA_STATUS_OK	0x2000	/* packet received okay */
+#define FXP_RFA_STATUS_C	0x8000	/* packet reception complete */
+#define FXP_RFA_CONTROL_SF	0x08	/* simple/flexible memory mode */
+#define FXP_RFA_CONTROL_H	0x10	/* header RFD */
+#define FXP_RFA_CONTROL_S	0x4000	/* suspend after reception */
+#define FXP_RFA_CONTROL_EL	0x8000	/* end of list */
+
+/*
+ * Statistics dump area definitions
+ */
+struct fxp_stats {
+	volatile u_int32_t tx_good;
+	volatile u_int32_t tx_maxcols;
+	volatile u_int32_t tx_latecols;
+	volatile u_int32_t tx_underruns;
+	volatile u_int32_t tx_lostcrs;
+	volatile u_int32_t tx_deffered;
+	volatile u_int32_t tx_single_collisions;
+	volatile u_int32_t tx_multiple_collisions;
+	volatile u_int32_t tx_total_collisions;
+	volatile u_int32_t rx_good;
+	volatile u_int32_t rx_crc_errors;
+	volatile u_int32_t rx_alignment_errors;
+	volatile u_int32_t rx_rnr_errors;
+	volatile u_int32_t rx_overrun_errors;
+	volatile u_int32_t rx_cdt_errors;
+	volatile u_int32_t rx_shortframes;
+	volatile u_int32_t completion_status;
+};
+#define FXP_STATS_DUMP_COMPLETE	0xa005
+#define FXP_STATS_DR_COMPLETE	0xa007
+	
+/*
+ * Serial EEPROM control register bits
+ */
+/* shift clock */
+#define FXP_EEPROM_EESK		0x01
+/* chip select */
+#define FXP_EEPROM_EECS		0x02
+/* data in */
+#define FXP_EEPROM_EEDI		0x04
+/* data out */
+#define FXP_EEPROM_EEDO		0x08
+
+/*
+ * Serial EEPROM opcodes, including start bit
+ */
+#define FXP_EEPROM_OPC_ERASE	0x4
+#define FXP_EEPROM_OPC_WRITE	0x5
+#define FXP_EEPROM_OPC_READ	0x6