MFC r258779,r258780,r258787,r258822:

Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this
shifts into the sign bit.  Instead use (1U << 31) which gets the
expected result.

Similar to the (1 << 31) case it is not defined to do (2 << 30).

This fix is not ideal as it assumes a 32 bit int, but does fix the issue
for most cases.

A similar change was made in OpenBSD.

1 files changed, 219 insertions, 4 deletions

diff --git a/sys/dev/etherswitch/arswitch/arswitchreg.h b/sys/dev/etherswitch/arswitch/arswitchreg.h
index 38be689..f221014 100644
--- a/sys/dev/etherswitch/arswitch/arswitchreg.h
+++ b/sys/dev/etherswitch/arswitch/arswitchreg.h
@@ -46,7 +46,7 @@
 #define		AR8X16_MASK_CTRL_REV_MASK	0x000000ff
 #define		AR8X16_MASK_CTRL_VER_MASK	0x0000ff00
 #define		AR8X16_MASK_CTRL_VER_SHIFT	8
-#define		AR8X16_MASK_CTRL_SOFT_RESET	(1 << 31)
+#define		AR8X16_MASK_CTRL_SOFT_RESET	(1U << 31)
 
 #define	AR8X16_REG_MODE			0x0008
 /* DIR-615 E4 U-Boot */
@@ -111,7 +111,7 @@
 #define		AR8X16_VLAN_VID_SHIFT		16
 #define		AR8X16_VLAN_PRIO		0x70000000
 #define		AR8X16_VLAN_PRIO_SHIFT		28
-#define		AR8X16_VLAN_PRIO_EN		(1 << 31)
+#define		AR8X16_VLAN_PRIO_EN		(1U << 31)
 
 #define	AR8X16_REG_VLAN_DATA		0x0044
 #define		AR8X16_VLAN_MEMBER		0x0000003f
@@ -151,6 +151,8 @@
 #define		AR8X16_MIB_FUNC_CAPTURE		0x3
 #define		AR8X16_MIB_FUNC_XXX		(1 << 30) /* 0x40000000 */
 
+#define		AR934X_MIB_ENABLE		(1 << 30)
+
 #define	AR8X16_REG_MDIO_HIGH_ADDR	0x0094
 
 #define	AR8X16_REG_MDIO_CTRL		0x0098
@@ -160,7 +162,7 @@
 #define		AR8X16_MDIO_CTRL_CMD_WRITE	0
 #define		AR8X16_MDIO_CTRL_CMD_READ	(1 << 27)
 #define		AR8X16_MDIO_CTRL_MASTER_EN	(1 << 30)
-#define		AR8X16_MDIO_CTRL_BUSY		(1 << 31)
+#define		AR8X16_MDIO_CTRL_BUSY		(1U << 31)
 
 #define	AR8X16_REG_PORT_BASE(_p)	(0x0100 + (_p) * 0x0100)
 
@@ -287,5 +289,218 @@
 
 #define	AR8X16_MAX_VLANS		16
 
-#endif /* __AR8X16_SWITCHREG_H__ */
+/*
+ * AR9340 switch specific definitions.
+ */
+
+/* XXX Linux define compatibility stuff */
+#define	BITM(_count)			((1 << _count) - 1)
+#define	BITS(_shift, _count)		(BITM(_count) << _shift)
+
+#define	AR934X_REG_OPER_MODE0		0x04
+#define		AR934X_OPER_MODE0_MAC_GMII_EN	(1 << 6)
+#define		AR934X_OPER_MODE0_PHY_MII_EN	(1 << 10)
+
+#define	AR934X_REG_OPER_MODE1		0x08
+#define		AR934X_REG_OPER_MODE1_PHY4_MII_EN	(1 << 28)
+
+#define	AR934X_REG_FLOOD_MASK		0x2c
+#define		AR934X_FLOOD_MASK_MC_DP(_p)	(1 << (16 + (_p)))
+#define		AR934X_FLOOD_MASK_BC_DP(_p)	(1 << (25 + (_p)))
+
+#define	AR934X_REG_QM_CTRL		0x3c
+#define		AR934X_QM_CTRL_ARP_EN	(1 << 15)
+
+#define	AR934X_REG_AT_CTRL		0x5c
+#define		AR934X_AT_CTRL_AGE_TIME		BITS(0, 15)
+#define		AR934X_AT_CTRL_AGE_EN		(1 << 17)
+#define		AR934X_AT_CTRL_LEARN_CHANGE	(1 << 18)
+
+#define	AR934X_REG_PORT_BASE(_port)	(0x100 + (_port) * 0x100)
+
+#define	AR934X_REG_PORT_VLAN1(_port)	(AR934X_REG_PORT_BASE((_port)) + 0x08)
+#define		AR934X_PORT_VLAN1_DEFAULT_SVID_S		0
+#define		AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN		(1 << 12)
+#define		AR934X_PORT_VLAN1_PORT_TLS_MODE			(1 << 13)
+#define		AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN		(1 << 14)
+#define		AR934X_PORT_VLAN1_PORT_CLONE_EN			(1 << 15)
+#define		AR934X_PORT_VLAN1_DEFAULT_CVID_S		16
+#define		AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN		(1 << 28)
+#define		AR934X_PORT_VLAN1_ING_PORT_PRI_S		29
+
+#define	AR934X_REG_PORT_VLAN2(_port)	(AR934X_REG_PORT_BASE((_port)) + 0x0c)
+#define		AR934X_PORT_VLAN2_PORT_VID_MEM_S		16
+#define		AR934X_PORT_VLAN2_8021Q_MODE_S			30
+#define		AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY		0
+#define		AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK	1
+#define		AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY		2
+#define		AR934X_PORT_VLAN2_8021Q_MODE_SECURE		3
 
+/*
+ * AR8327 specific registers
+ */
+#define	AR8327_NUM_PORTS		7
+#define	AR8327_NUM_PHYS			5
+#define	AR8327_PORTS_ALL		0x7f
+
+#define	AR8327_REG_MASK			0x000
+
+#define	AR8327_REG_PAD0_MODE		0x004
+#define	AR8327_REG_PAD5_MODE		0x008
+#define	AR8327_REG_PAD6_MODE		0x00c
+
+#define		AR8327_PAD_MAC_MII_RXCLK_SEL	(1 << 0)
+#define		AR8327_PAD_MAC_MII_TXCLK_SEL	(1 << 1)
+#define		AR8327_PAD_MAC_MII_EN		(1 << 2)
+#define		AR8327_PAD_MAC_GMII_RXCLK_SEL	(1 << 4)
+#define		AR8327_PAD_MAC_GMII_TXCLK_SEL	(1 << 5)
+#define		AR8327_PAD_MAC_GMII_EN		(1 << 6)
+#define		AR8327_PAD_SGMII_EN		(1 << 7)
+#define		AR8327_PAD_PHY_MII_RXCLK_SEL	(1 << 8)
+#define		AR8327_PAD_PHY_MII_TXCLK_SEL	(1 << 9)
+#define		AR8327_PAD_PHY_MII_EN		(1 << 10)
+#define		AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL	(1 << 11)
+#define		AR8327_PAD_PHY_GMII_RXCLK_SEL	(1 << 12)
+#define		AR8327_PAD_PHY_GMII_TXCLK_SEL	(1 << 13)
+#define		AR8327_PAD_PHY_GMII_EN		(1 << 14)
+#define		AR8327_PAD_PHYX_GMII_EN		(1 << 16)
+#define		AR8327_PAD_PHYX_RGMII_EN	(1 << 17)
+#define		AR8327_PAD_PHYX_MII_EN		(1 << 18)
+#define		AR8327_PAD_SGMII_DELAY_EN	(1 << 19)
+#define		AR8327_PAD_RGMII_RXCLK_DELAY_SEL	BITS(20, 2)
+#define		AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S		20
+#define		AR8327_PAD_RGMII_TXCLK_DELAY_SEL	BITS(22, 2)
+#define		AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S	22
+#define		AR8327_PAD_RGMII_RXCLK_DELAY_EN	(1 << 24)
+#define		AR8327_PAD_RGMII_TXCLK_DELAY_EN	(1 << 25)
+#define		AR8327_PAD_RGMII_EN		(1 << 26)
+
+#define	AR8327_REG_POWER_ON_STRIP	0x010
+#define		AR8327_POWER_ON_STRIP_POWER_ON_SEL	(1U << 31)
+#define		AR8327_POWER_ON_STRIP_LED_OPEN_EN	(1 << 24)
+#define		AR8327_POWER_ON_STRIP_SERDES_AEN	(1 << 7)
+
+#define	AR8327_REG_INT_STATUS0		0x020
+#define		AR8327_INT0_VT_DONE			(1 << 20)
+
+#define	AR8327_REG_INT_STATUS1		0x024
+#define	AR8327_REG_INT_MASK0		0x028
+#define	AR8327_REG_INT_MASK1		0x02c
+
+#define	AR8327_REG_MODULE_EN		0x030
+#define		AR8327_MODULE_EN_MIB		(1 << 0)
+
+#define	AR8327_REG_MIB_FUNC		0x034
+#define		AR8327_MIB_CPU_KEEP		(1 << 20)
+
+#define	AR8327_REG_SERVICE_TAG		0x048
+#define	AR8327_REG_LED_CTRL0		0x050
+#define	AR8327_REG_LED_CTRL1		0x054
+#define	AR8327_REG_LED_CTRL2		0x058
+#define	AR8327_REG_LED_CTRL3		0x05c
+#define	AR8327_REG_MAC_ADDR0		0x060
+#define	AR8327_REG_MAC_ADDR1		0x064
+
+#define	AR8327_REG_MAX_FRAME_SIZE	0x078
+#define		AR8327_MAX_FRAME_SIZE_MTU	BITS(0, 14)
+
+#define	AR8327_REG_PORT_STATUS(_i)	(0x07c + (_i) * 4)
+
+#define	AR8327_REG_HEADER_CTRL		0x098
+#define	AR8327_REG_PORT_HEADER(_i)		(0x09c + (_i) * 4)
+
+#define	AR8327_REG_SGMII_CTRL		0x0e0
+#define		AR8327_SGMII_CTRL_EN_PLL		(1 << 1)
+#define		AR8327_SGMII_CTRL_EN_RX			(1 << 2)
+#define		AR8327_SGMII_CTRL_EN_TX			(1 << 3)
+
+#define	AR8327_REG_PORT_VLAN0(_i)		(0x420 + (_i) * 0x8)
+#define		AR8327_PORT_VLAN0_DEF_SVID		BITS(0, 12)
+#define		AR8327_PORT_VLAN0_DEF_SVID_S		0
+#define		AR8327_PORT_VLAN0_DEF_CVID		BITS(16, 12)
+#define		AR8327_PORT_VLAN0_DEF_CVID_S		16
+
+#define	AR8327_REG_PORT_VLAN1(_i)		(0x424 + (_i) * 0x8)
+#define		AR8327_PORT_VLAN1_PORT_VLAN_PROP	(1 << 6)
+#define		AR8327_PORT_VLAN1_OUT_MODE		BITS(12, 2)
+#define		AR8327_PORT_VLAN1_OUT_MODE_S		12
+#define		AR8327_PORT_VLAN1_OUT_MODE_UNMOD	0
+#define		AR8327_PORT_VLAN1_OUT_MODE_UNTAG	1
+#define		AR8327_PORT_VLAN1_OUT_MODE_TAG		2
+#define		AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH	3
+
+#define	AR8327_REG_ATU_DATA0		0x600
+#define	AR8327_REG_ATU_DATA1		0x604
+#define	AR8327_REG_ATU_DATA2		0x608
+
+#define	AR8327_REG_ATU_FUNC		0x60c
+#define		AR8327_ATU_FUNC_OP		BITS(0, 4)
+#define		AR8327_ATU_FUNC_OP_NOOP			0x0
+#define		AR8327_ATU_FUNC_OP_FLUSH		0x1
+#define		AR8327_ATU_FUNC_OP_LOAD			0x2
+#define		AR8327_ATU_FUNC_OP_PURGE		0x3
+#define		AR8327_ATU_FUNC_OP_FLUSH_LOCKED		0x4
+#define		AR8327_ATU_FUNC_OP_FLUSH_UNICAST	0x5
+#define		AR8327_ATU_FUNC_OP_GET_NEXT		0x6
+#define		AR8327_ATU_FUNC_OP_SEARCH_MAC		0x7
+#define		AR8327_ATU_FUNC_OP_CHANGE_TRUNK		0x8
+#define		AR8327_ATU_FUNC_BUSY			(1U << 31)
+
+#define	AR8327_REG_VTU_FUNC0		0x0610
+#define		AR8327_VTU_FUNC0_EG_MODE	BITS(4, 14)
+#define		AR8327_VTU_FUNC0_EG_MODE_S(_i)	(4 + (_i) * 2)
+#define		AR8327_VTU_FUNC0_EG_MODE_KEEP	0
+#define		AR8327_VTU_FUNC0_EG_MODE_UNTAG	1
+#define		AR8327_VTU_FUNC0_EG_MODE_TAG	2
+#define		AR8327_VTU_FUNC0_EG_MODE_NOT	3
+#define		AR8327_VTU_FUNC0_IVL		(1 << 19)
+#define		AR8327_VTU_FUNC0_VALID		(1 << 20)
+
+#define	AR8327_REG_VTU_FUNC1		0x0614
+#define		AR8327_VTU_FUNC1_OP		BITS(0, 3)
+#define		AR8327_VTU_FUNC1_OP_NOOP	0
+#define		AR8327_VTU_FUNC1_OP_FLUSH	1
+#define		AR8327_VTU_FUNC1_OP_LOAD	2
+#define		AR8327_VTU_FUNC1_OP_PURGE	3
+#define		AR8327_VTU_FUNC1_OP_REMOVE_PORT	4
+#define		AR8327_VTU_FUNC1_OP_GET_NEXT	5
+#define		AR8327_VTU_FUNC1_OP_GET_ONE	6
+#define		AR8327_VTU_FUNC1_FULL		(1 << 4)
+#define		AR8327_VTU_FUNC1_PORT		(1 << 8, 4)
+#define		AR8327_VTU_FUNC1_PORT_S		8
+#define		AR8327_VTU_FUNC1_VID		(1 << 16, 12)
+#define		AR8327_VTU_FUNC1_VID_S		16
+#define		AR8327_VTU_FUNC1_BUSY		(1U << 31)
+
+#define	AR8327_REG_FWD_CTRL0		0x620
+#define		AR8327_FWD_CTRL0_CPU_PORT_EN	(1 << 10)
+#define		AR8327_FWD_CTRL0_MIRROR_PORT	BITS(4, 4)
+#define		AR8327_FWD_CTRL0_MIRROR_PORT_S	4
+
+#define	AR8327_REG_FWD_CTRL1		0x624
+#define		AR8327_FWD_CTRL1_UC_FLOOD	BITS(0, 7)
+#define		AR8327_FWD_CTRL1_UC_FLOOD_S	0
+#define		AR8327_FWD_CTRL1_MC_FLOOD	BITS(8, 7)
+#define		AR8327_FWD_CTRL1_MC_FLOOD_S	8
+#define		AR8327_FWD_CTRL1_BC_FLOOD	BITS(16, 7)
+#define		AR8327_FWD_CTRL1_BC_FLOOD_S	16
+#define		AR8327_FWD_CTRL1_IGMP		BITS(24, 7)
+#define		AR8327_FWD_CTRL1_IGMP_S		24
+
+#define	AR8327_REG_PORT_LOOKUP(_i)	(0x660 + (_i) * 0xc)
+#define		AR8327_PORT_LOOKUP_MEMBER	BITS(0, 7)
+#define		AR8327_PORT_LOOKUP_IN_MODE	BITS(8, 2)
+#define		AR8327_PORT_LOOKUP_IN_MODE_S	8
+#define		AR8327_PORT_LOOKUP_STATE	BITS(16, 3)
+#define		AR8327_PORT_LOOKUP_STATE_S	16
+#define		AR8327_PORT_LOOKUP_LEARN	(1 << 20)
+#define		AR8327_PORT_LOOKUP_ING_MIRROR_EN	(1 << 25)
+
+#define	AR8327_REG_PORT_PRIO(_i)	(0x664 + (_i) * 0xc)
+
+#define	AR8327_REG_PORT_HOL_CTRL1(_i)		(0x974 + (_i) * 0x8)
+#define		AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN	(1 << 16)
+
+#define	AR8327_REG_PORT_STATS_BASE(_i)		(0x1000 + (_i) * 0x100)
+
+#endif /* __AR8X16_SWITCHREG_H__ */