Sync the e1000 drivers with what's in head as of r294327, modulo parts

that don't apply to stable/10 (driver API, if_inc_counter(), RSS changes
etc.) and modulo r287465 (which reportedly breaks igb(4)), i. e. assorted
fixes and improvements only:

o MFC r267385 (partial):
  - Don't compare bus_dma map pointers for static DMA allocations against
    NULL to determine if bus_dmamap_unload() or bus_dmamem_free() should be
    called. Instead, check the associated bus and virtual addresses.
  - Don't clear static DMA maps to NULL.
o MFC r284933:
  Delete the refernce to VLAN handling being disabled by default. This is
  no longer the case. [1]
o MFC r285639:
  Add an adapter CORE lock in the DDB hook em_dump_queue to avoid WITNESS
  panic in em_init_locked() while debugging.
o MFC r285879:
  - Remove unused txd_saved.
  - Intialize txd_upper, txd_lower and txd_used at declaration.
o MFC r286162:
  Free mbufs when busdma loading fails.
o MFC r286829:
  Add capability to disable CRC stripping as it breaks IPMI/BMC capabilities
  on certain adatpers. [2]
o MFC r286831: [3]
  - Increase EM_MAX_SCATTER to 64 such that the size of em_xmit()::
    segs[EM_MAX_SCATTER] doesn't get overrun by things like NFS that can
    and do shove more than 32 segs when being used with em(4) and TSO4.
  - Update tso handling code in em_xmit() with update from jhb@
  - Set if_hw_tsomax, if_hw_tsomaxsegcount and if_hw_tsomaxsegsize to
    appropriate values.
  - Define a TSO workaround "magic" number of 4 that is used to avoid an
    alignment issue in hardware.
  - Change a couple of integer values that were used as booleans to actual
    bool types.
  - Ensure that em_enable_intr() enables the appropriate mask of interrupts
    and not just a hardcoded define of values.
o MFC r286832:
  e1000/if_lem.c bump to 1.1.0
o MFC r286833:
  Bump all copywrite dates to 2015.
o MFC r287112:
  Style/whitespace cleanup in shared/common code.
o MFC r293331:
  - Switch em(4) to the extended RX descriptor format.
  - Split rxbuffer and txbuffer apart to support the new RX descriptor
    format structures. Move rxbuffer manipulation to em_setup_rxdesc() to
    unify the new behavior changes.
  - Add a RSSKEYLEN macro for help in generating the RSSKEY data structures
    in the card.
  - Change em_receive_checksum() to process the new rxdescriptor format
    status bit.
o MFC r293332:
  Disable the reuse of checksum offload context descriptors in the case
  of multiple queues in em(4). Document errata in the code.
o MFC r293854:
  Given that em(4), lem(4) and igb(4) hardware doesn't require the
  alignment guarantees provided by m_defrag(9), use m_collapse(9)
  instead for performance reasons.
  While at it, sanitize the statistics softc members, i. e. retire
  unused ones and add SYSCTL nodes missing for actually used ones.

PR:	118693 [1], 161277 [2], 195078 [3], 199174 [3], 200221 [3]

1 files changed, 38 insertions, 38 deletions

diff --git a/sys/dev/e1000/e1000_82541.h b/sys/dev/e1000/e1000_82541.h
index 3b6b961..7a01fd4 100644
--- a/sys/dev/e1000/e1000_82541.h
+++ b/sys/dev/e1000/e1000_82541.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2008, Intel Corporation 
+  Copyright (c) 2001-2015, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -37,55 +37,55 @@
 
 #define NVM_WORD_SIZE_BASE_SHIFT_82541 (NVM_WORD_SIZE_BASE_SHIFT + 1)
 
-#define IGP01E1000_PHY_CHANNEL_NUM                    4
+#define IGP01E1000_PHY_CHANNEL_NUM		4
 
-#define IGP01E1000_PHY_AGC_A                     0x1172
-#define IGP01E1000_PHY_AGC_B                     0x1272
-#define IGP01E1000_PHY_AGC_C                     0x1472
-#define IGP01E1000_PHY_AGC_D                     0x1872
+#define IGP01E1000_PHY_AGC_A			0x1172
+#define IGP01E1000_PHY_AGC_B			0x1272
+#define IGP01E1000_PHY_AGC_C			0x1472
+#define IGP01E1000_PHY_AGC_D			0x1872
 
-#define IGP01E1000_PHY_AGC_PARAM_A               0x1171
-#define IGP01E1000_PHY_AGC_PARAM_B               0x1271
-#define IGP01E1000_PHY_AGC_PARAM_C               0x1471
-#define IGP01E1000_PHY_AGC_PARAM_D               0x1871
+#define IGP01E1000_PHY_AGC_PARAM_A		0x1171
+#define IGP01E1000_PHY_AGC_PARAM_B		0x1271
+#define IGP01E1000_PHY_AGC_PARAM_C		0x1471
+#define IGP01E1000_PHY_AGC_PARAM_D		0x1871
 
-#define IGP01E1000_PHY_EDAC_MU_INDEX             0xC000
-#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS      0x8000
+#define IGP01E1000_PHY_EDAC_MU_INDEX		0xC000
+#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS	0x8000
 
-#define IGP01E1000_PHY_DSP_RESET                 0x1F33
+#define IGP01E1000_PHY_DSP_RESET		0x1F33
 
-#define IGP01E1000_PHY_DSP_FFE                   0x1F35
-#define IGP01E1000_PHY_DSP_FFE_CM_CP             0x0069
-#define IGP01E1000_PHY_DSP_FFE_DEFAULT           0x002A
+#define IGP01E1000_PHY_DSP_FFE			0x1F35
+#define IGP01E1000_PHY_DSP_FFE_CM_CP		0x0069
+#define IGP01E1000_PHY_DSP_FFE_DEFAULT		0x002A
 
-#define IGP01E1000_IEEE_FORCE_GIG                0x0140
-#define IGP01E1000_IEEE_RESTART_AUTONEG          0x3300
+#define IGP01E1000_IEEE_FORCE_GIG		0x0140
+#define IGP01E1000_IEEE_RESTART_AUTONEG		0x3300
 
-#define IGP01E1000_AGC_LENGTH_SHIFT                   7
-#define IGP01E1000_AGC_RANGE                         10
+#define IGP01E1000_AGC_LENGTH_SHIFT		7
+#define IGP01E1000_AGC_RANGE			10
 
-#define FFE_IDLE_ERR_COUNT_TIMEOUT_20                20
-#define FFE_IDLE_ERR_COUNT_TIMEOUT_100              100
+#define FFE_IDLE_ERR_COUNT_TIMEOUT_20		20
+#define FFE_IDLE_ERR_COUNT_TIMEOUT_100		100
 
-#define IGP01E1000_ANALOG_FUSE_STATUS            0x20D0
-#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS      0x20D1
-#define IGP01E1000_ANALOG_FUSE_CONTROL           0x20DC
-#define IGP01E1000_ANALOG_FUSE_BYPASS            0x20DE
+#define IGP01E1000_ANALOG_FUSE_STATUS		0x20D0
+#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS	0x20D1
+#define IGP01E1000_ANALOG_FUSE_CONTROL		0x20DC
+#define IGP01E1000_ANALOG_FUSE_BYPASS		0x20DE
 
-#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED     0x0100
-#define IGP01E1000_ANALOG_FUSE_FINE_MASK         0x0F80
-#define IGP01E1000_ANALOG_FUSE_COARSE_MASK       0x0070
-#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH     0x0040
-#define IGP01E1000_ANALOG_FUSE_COARSE_10         0x0010
-#define IGP01E1000_ANALOG_FUSE_FINE_1            0x0080
-#define IGP01E1000_ANALOG_FUSE_FINE_10           0x0500
-#define IGP01E1000_ANALOG_FUSE_POLY_MASK         0xF000
+#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED	0x0100
+#define IGP01E1000_ANALOG_FUSE_FINE_MASK	0x0F80
+#define IGP01E1000_ANALOG_FUSE_COARSE_MASK	0x0070
+#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH	0x0040
+#define IGP01E1000_ANALOG_FUSE_COARSE_10	0x0010
+#define IGP01E1000_ANALOG_FUSE_FINE_1		0x0080
+#define IGP01E1000_ANALOG_FUSE_FINE_10		0x0500
+#define IGP01E1000_ANALOG_FUSE_POLY_MASK	0xF000
 #define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
 
-#define IGP01E1000_MSE_CHANNEL_D                 0x000F
-#define IGP01E1000_MSE_CHANNEL_C                 0x00F0
-#define IGP01E1000_MSE_CHANNEL_B                 0x0F00
-#define IGP01E1000_MSE_CHANNEL_A                 0xF000
+#define IGP01E1000_MSE_CHANNEL_D		0x000F
+#define IGP01E1000_MSE_CHANNEL_C		0x00F0
+#define IGP01E1000_MSE_CHANNEL_B		0x0F00
+#define IGP01E1000_MSE_CHANNEL_A		0xF000
 
 
 void e1000_init_script_state_82541(struct e1000_hw *hw, bool state);