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authoranholt <anholt@FreeBSD.org>2004-06-11 03:26:59 +0000
committeranholt <anholt@FreeBSD.org>2004-06-11 03:26:59 +0000
commitbe5dc242b6a2d2549e38e77baf82adb7b33b042b (patch)
treedc68be4b837d82c81a81bb2cec14ded275766e76 /sys/dev/drm
parentda6e1707d47446b0f3de71fd5a924233a2168f65 (diff)
downloadFreeBSD-src-be5dc242b6a2d2549e38e77baf82adb7b33b042b.zip
FreeBSD-src-be5dc242b6a2d2549e38e77baf82adb7b33b042b.tar.gz
Merge from DRI CVS as of 2004-05-26. Most of the meat is new PCI IDs and a new
packet for Radeon.
Diffstat (limited to 'sys/dev/drm')
-rw-r--r--sys/dev/drm/drm.h12
-rw-r--r--sys/dev/drm/drmP.h5
-rw-r--r--sys/dev/drm/drm_drv.h23
-rw-r--r--sys/dev/drm/drm_linux_list.h71
-rw-r--r--sys/dev/drm/drm_os_freebsd.h7
-rw-r--r--sys/dev/drm/drm_pciids.h204
-rw-r--r--sys/dev/drm/drm_sarea.h16
-rw-r--r--sys/dev/drm/mga.h8
-rw-r--r--sys/dev/drm/mga_drm.h35
-rw-r--r--sys/dev/drm/r128.h42
-rw-r--r--sys/dev/drm/r128_drm.h61
-rw-r--r--sys/dev/drm/r128_state.c21
-rw-r--r--sys/dev/drm/radeon.h67
-rw-r--r--sys/dev/drm/radeon_drm.h90
-rw-r--r--sys/dev/drm/radeon_drv.h1
-rw-r--r--sys/dev/drm/radeon_mem.c4
-rw-r--r--sys/dev/drm/radeon_state.c166
-rw-r--r--sys/dev/drm/sis.h11
-rw-r--r--sys/dev/drm/sis_drv.c2
-rw-r--r--sys/dev/drm/sis_mm.c4
-rw-r--r--sys/dev/drm/tdfx.h8
21 files changed, 609 insertions, 249 deletions
diff --git a/sys/dev/drm/drm.h b/sys/dev/drm/drm.h
index 9ef223d..36e86b3 100644
--- a/sys/dev/drm/drm.h
+++ b/sys/dev/drm/drm.h
@@ -137,6 +137,18 @@ typedef struct drm_tex_region {
unsigned int age;
} drm_tex_region_t;
+/**
+ * Hardware lock.
+ *
+ * The lock structure is a simple cache-line aligned integer. To avoid
+ * processor bus contention on a multiprocessor system, there should not be any
+ * other data stored in the same cache line.
+ */
+typedef struct drm_hw_lock {
+ __volatile__ unsigned int lock; /**< lock variable */
+ char padding[60]; /**< Pad to cache line */
+} drm_hw_lock_t;
+
/**
* DRM_IOCTL_VERSION ioctl argument type.
diff --git a/sys/dev/drm/drmP.h b/sys/dev/drm/drmP.h
index 7872c79..7753b19 100644
--- a/sys/dev/drm/drmP.h
+++ b/sys/dev/drm/drmP.h
@@ -197,11 +197,6 @@ typedef struct drm_buf_entry {
drm_freelist_t freelist;
} drm_buf_entry_t;
-typedef struct drm_hw_lock {
- __volatile__ unsigned int lock;
- char padding[60]; /* Pad to cache line */
-} drm_hw_lock_t;
-
typedef TAILQ_HEAD(drm_file_list, drm_file) drm_file_list_t;
struct drm_file {
TAILQ_ENTRY(drm_file) link;
diff --git a/sys/dev/drm/drm_drv.h b/sys/dev/drm/drm_drv.h
index 8148ea8..d005ec4 100644
--- a/sys/dev/drm/drm_drv.h
+++ b/sys/dev/drm/drm_drv.h
@@ -79,16 +79,16 @@
#endif
#ifndef DRIVER_PREINIT
-#define DRIVER_PREINIT()
+#define DRIVER_PREINIT(dev) do {} while (0)
#endif
#ifndef DRIVER_POSTINIT
-#define DRIVER_POSTINIT()
+#define DRIVER_POSTINIT(dev) do {} while (0)
#endif
#ifndef DRIVER_PRERELEASE
#define DRIVER_PRERELEASE()
#endif
#ifndef DRIVER_PRETAKEDOWN
-#define DRIVER_PRETAKEDOWN()
+#define DRIVER_PRETAKEDOWN(dev)
#endif
#ifndef DRIVER_POSTCLEANUP
#define DRIVER_POSTCLEANUP()
@@ -212,7 +212,9 @@ const char *DRM(find_description)(int vendor, int device);
#ifdef __FreeBSD__
static struct cdevsw DRM(cdevsw) = {
+#if __FreeBSD_version >= 502103
.d_version = D_VERSION,
+#endif
.d_open = DRM( open ),
.d_close = DRM( close ),
.d_read = DRM( read ),
@@ -220,14 +222,21 @@ static struct cdevsw DRM(cdevsw) = {
.d_poll = DRM( poll ),
.d_mmap = DRM( mmap ),
.d_name = DRIVER_NAME,
+#if __FreeBSD_version >= 502103
.d_flags = D_TRACKCLOSE | D_NEEDGIANT,
+#else
+ .d_maj = 145,
+ .d_flags = D_TRACKCLOSE,
+#endif
#if __FreeBSD_version < 500000
.d_bmaj = -1
#endif
};
+#include "dev/drm/drm_pciids.h"
+
static drm_pci_id_list_t DRM(pciidlist)[] = {
- DRIVER_PCI_IDS
+ DRM(PCI_IDS)
};
static int DRM(probe)(device_t dev)
@@ -511,7 +520,7 @@ static int DRM(takedown)( drm_device_t *dev )
DRM_DEBUG( "\n" );
- DRIVER_PRETAKEDOWN();
+ DRIVER_PRETAKEDOWN(dev);
#if __HAVE_IRQ
if (dev->irq_enabled)
DRM(irq_uninstall)( dev );
@@ -626,7 +635,7 @@ static int DRM(init)( device_t nbdev )
int retcode;
#endif
DRM_DEBUG( "\n" );
- DRIVER_PREINIT();
+ DRIVER_PREINIT(dev);
#ifdef __FreeBSD__
unit = device_get_unit(nbdev);
@@ -704,7 +713,7 @@ static int DRM(init)( device_t nbdev )
DRIVER_DATE,
unit );
- DRIVER_POSTINIT();
+ DRIVER_POSTINIT(dev);
return 0;
diff --git a/sys/dev/drm/drm_linux_list.h b/sys/dev/drm/drm_linux_list.h
new file mode 100644
index 0000000..4fef61c
--- /dev/null
+++ b/sys/dev/drm/drm_linux_list.h
@@ -0,0 +1,71 @@
+/* drm_linux_list.h -- linux list functions for the BSDs.
+ * Created: Mon Apr 7 14:30:16 1999 by anholt@FreeBSD.org
+ *
+ * Copyright 2003 Eric Anholt
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Eric Anholt <anholt@FreeBSD.org>
+ *
+ * $FreeBSD$
+ */
+
+struct list_head {
+ struct list_head *next, *prev;
+};
+
+/* Cheat, assume the list_head is at the start of the struct */
+#define list_entry(entry, type, member) (type *)(entry)
+
+static __inline__ void
+INIT_LIST_HEAD(struct list_head *head) {
+ (head)->next = head;
+ (head)->prev = head;
+}
+
+static __inline__ int
+list_empty(struct list_head *head) {
+ return (head)->next == head;
+}
+
+static __inline__ void
+list_add_tail(struct list_head *entry, struct list_head *head) {
+ (entry)->prev = (head)->prev;
+ (entry)->next = head;
+ (head)->prev->next = entry;
+ (head)->prev = entry;
+}
+
+static __inline__ void
+list_del(struct list_head *entry) {
+ (entry)->next->prev = (entry)->prev;
+ (entry)->prev->next = (entry)->next;
+}
+
+#define list_for_each(entry, head) \
+ for (entry = (head)->next; entry != head; entry = (entry)->next)
+
+#define list_for_each_safe(entry, temp, head) \
+ for (entry = (head)->next, temp = (entry)->next; \
+ temp != head; \
+ entry = temp, temp = temp->next)
+
diff --git a/sys/dev/drm/drm_os_freebsd.h b/sys/dev/drm/drm_os_freebsd.h
index cb4cfe0..24dcd10 100644
--- a/sys/dev/drm/drm_os_freebsd.h
+++ b/sys/dev/drm/drm_os_freebsd.h
@@ -78,6 +78,8 @@
#include <sys/mutex.h>
#endif
+#include "dev/drm/drm_linux_list.h"
+
#if __FreeBSD_version >= 400006
#define __REALLY_HAVE_AGP __HAVE_AGP
#endif
@@ -310,6 +312,11 @@ for ( ret = 0 ; !ret && !(condition) ; ) { \
MALLOC_DECLARE(malloctype);
#undef malloctype
+#if __FreeBSD_version < 502109
+#define bus_alloc_resource_any(dev, type, rid, flags) \
+ bus_alloc_resource(dev, type, rid, 0ul, ~0ul, 1, flags)
+#endif
+
#if __FreeBSD_version >= 480000
#define cpu_to_le32(x) htole32(x)
#define le32_to_cpu(x) le32toh(x)
diff --git a/sys/dev/drm/drm_pciids.h b/sys/dev/drm/drm_pciids.h
new file mode 100644
index 0000000..0a8abc5
--- /dev/null
+++ b/sys/dev/drm/drm_pciids.h
@@ -0,0 +1,204 @@
+/* $FreeBSD$ */
+/*
+ This file is auto-generated from the drm_pciids.txt in the DRM CVS
+ Please contact dri-devel@lists.sf.net to add new cards to this list
+*/
+#define radeon_PCI_IDS \
+ {0x1002, 0x4136, 0, "ATI Radeon RS100 IGP 320M"}, \
+ {0x1002, 0x4137, 0, "ATI Radeon RS200 IGP"}, \
+ {0x1002, 0x4237, 0, "ATI Radeon RS250 IGP"}, \
+ {0x1002, 0x4242, 0, "ATI Radeon BB R200 AIW 8500DV"}, \
+ {0x1002, 0x4242, 0, "ATI Radeon BC R200"}, \
+ {0x1002, 0x4336, 0, "ATI Radeon RS100 Mobility U1"}, \
+ {0x1002, 0x4337, 0, "ATI Radeon RS200 Mobility IGP 340M"}, \
+ {0x1002, 0x4437, 0, "ATI Radeon RS250 Mobility IGP"}, \
+ {0x1002, 0x4964, 0, "ATI Radeon Id R250 9000"}, \
+ {0x1002, 0x4965, 0, "ATI Radeon Ie R250 9000"}, \
+ {0x1002, 0x4966, 0, "ATI Radeon If R250 9000"}, \
+ {0x1002, 0x4967, 0, "ATI Radeon Ig R250 9000"}, \
+ {0x1002, 0x4C57, 0, "ATI Radeon LW Mobility 7500 M7"}, \
+ {0x1002, 0x4C58, 0, "ATI Radeon LX RV200 Mobility FireGL 7800 M7"}, \
+ {0x1002, 0x4C59, 0, "ATI Radeon LY Mobility M6"}, \
+ {0x1002, 0x4C5A, 0, "ATI Radeon LZ Mobility M6"}, \
+ {0x1002, 0x4C64, 0, "ATI Radeon Ld R250 Mobility 9000 M9"}, \
+ {0x1002, 0x4C65, 0, "ATI Radeon Le R250 Mobility 9000 M9"}, \
+ {0x1002, 0x4C66, 0, "ATI Radeon Lf R250 Mobility 9000 M9"}, \
+ {0x1002, 0x4C67, 0, "ATI Radeon Lg R250 Mobility 9000 M9"}, \
+ {0x1002, 0x5144, 0, "ATI Radeon QD R100"}, \
+ {0x1002, 0x5145, 0, "ATI Radeon QE R100"}, \
+ {0x1002, 0x5146, 0, "ATI Radeon QF R100"}, \
+ {0x1002, 0x5147, 0, "ATI Radeon QG R100"}, \
+ {0x1002, 0x5148, 0, "ATI Radeon QH R200 8500"}, \
+ {0x1002, 0x5149, 0, "ATI Radeon QI R200"}, \
+ {0x1002, 0x514A, 0, "ATI Radeon QJ R200"}, \
+ {0x1002, 0x514B, 0, "ATI Radeon QK R200"}, \
+ {0x1002, 0x514C, 0, "ATI Radeon QL R200 8500 LE"}, \
+ {0x1002, 0x514D, 0, "ATI Radeon QM R200 9100"}, \
+ {0x1002, 0x514E, 0, "ATI Radeon QN R200 8500 LE"}, \
+ {0x1002, 0x514F, 0, "ATI Radeon QO R200 8500 LE"}, \
+ {0x1002, 0x5157, 0, "ATI Radeon QW RV200 7500"}, \
+ {0x1002, 0x5158, 0, "ATI Radeon QX RV200 7500"}, \
+ {0x1002, 0x5159, 0, "ATI Radeon QY RV100 7000/VE"}, \
+ {0x1002, 0x515A, 0, "ATI Radeon QZ RV100 7000/VE"}, \
+ {0x1002, 0x5168, 0, "ATI Radeon Qh R200"}, \
+ {0x1002, 0x5169, 0, "ATI Radeon Qi R200"}, \
+ {0x1002, 0x516A, 0, "ATI Radeon Qj R200"}, \
+ {0x1002, 0x516B, 0, "ATI Radeon Qk R200"}, \
+ {0x1002, 0x516C, 0, "ATI Radeon Ql R200"}, \
+ {0x1002, 0x5834, 0, "ATI Radeon RS300 IGP"}, \
+ {0x1002, 0x5835, 0, "ATI Radeon RS300 Mobility IGP"}, \
+ {0x1002, 0x5836, 0, "ATI Radeon RS300 IGP"}, \
+ {0x1002, 0x5837, 0, "ATI Radeon RS300 IGP"}, \
+ {0x1002, 0x5960, 0, "ATI Radeon RV280 9200"}, \
+ {0x1002, 0x5961, 0, "ATI Radeon RV280 9200 SE"}, \
+ {0x1002, 0x5962, 0, "ATI Radeon RV280 9200"}, \
+ {0x1002, 0x5963, 0, "ATI Radeon RV280 9200"}, \
+ {0x1002, 0x5964, 0, "ATI Radeon RV280 9200 SE"}, \
+ {0x1002, 0x5968, 0, "ATI Radeon RV280 9200"}, \
+ {0x1002, 0x5969, 0, "ATI Radeon RV280 9200"}, \
+ {0x1002, 0x596A, 0, "ATI Radeon RV280 9200"}, \
+ {0x1002, 0x596B, 0, "ATI Radeon RV280 9200"}, \
+ {0x1002, 0x5c61, 0, "ATI Radeon RV280 Mobility"}, \
+ {0x1002, 0x5c62, 0, "ATI Radeon RV280"}, \
+ {0x1002, 0x5c63, 0, "ATI Radeon RV280 Mobility"}, \
+ {0x1002, 0x5c64, 0, "ATI Radeon RV280"}, \
+ {0, 0, 0, NULL}
+
+#define r128_PCI_IDS \
+ {0x1002, 0x4c45, 0, "ATI Rage 128 Mobility LE (PCI)"}, \
+ {0x1002, 0x4c46, 0, "ATI Rage 128 Mobility LF (AGP)"}, \
+ {0x1002, 0x4d46, 0, "ATI Rage 128 Mobility MF (AGP)"}, \
+ {0x1002, 0x4d4c, 0, "ATI Rage 128 Mobility ML (AGP)"}, \
+ {0x1002, 0x5041, 0, "ATI Rage 128 Pro PA (PCI)"}, \
+ {0x1002, 0x5042, 0, "ATI Rage 128 Pro PB (AGP)"}, \
+ {0x1002, 0x5043, 0, "ATI Rage 128 Pro PC (AGP)"}, \
+ {0x1002, 0x5044, 0, "ATI Rage 128 Pro PD (PCI)"}, \
+ {0x1002, 0x5045, 0, "ATI Rage 128 Pro PE (AGP)"}, \
+ {0x1002, 0x5046, 0, "ATI Rage 128 Pro PF (AGP)"}, \
+ {0x1002, 0x5047, 0, "ATI Rage 128 Pro PG (PCI)"}, \
+ {0x1002, 0x5048, 0, "ATI Rage 128 Pro PH (AGP)"}, \
+ {0x1002, 0x5049, 0, "ATI Rage 128 Pro PI (AGP)"}, \
+ {0x1002, 0x504A, 0, "ATI Rage 128 Pro PJ (PCI)"}, \
+ {0x1002, 0x504B, 0, "ATI Rage 128 Pro PK (AGP)"}, \
+ {0x1002, 0x504C, 0, "ATI Rage 128 Pro PL (AGP)"}, \
+ {0x1002, 0x504D, 0, "ATI Rage 128 Pro PM (PCI)"}, \
+ {0x1002, 0x504E, 0, "ATI Rage 128 Pro PN (AGP)"}, \
+ {0x1002, 0x504F, 0, "ATI Rage 128 Pro PO (AGP)"}, \
+ {0x1002, 0x5050, 0, "ATI Rage 128 Pro PP (PCI)"}, \
+ {0x1002, 0x5051, 0, "ATI Rage 128 Pro PQ (AGP)"}, \
+ {0x1002, 0x5052, 0, "ATI Rage 128 Pro PR (PCI)"}, \
+ {0x1002, 0x5053, 0, "ATI Rage 128 Pro PS (PCI)"}, \
+ {0x1002, 0x5054, 0, "ATI Rage 128 Pro PT (AGP)"}, \
+ {0x1002, 0x5055, 0, "ATI Rage 128 Pro PU (AGP)"}, \
+ {0x1002, 0x5056, 0, "ATI Rage 128 Pro PV (PCI)"}, \
+ {0x1002, 0x5057, 0, "ATI Rage 128 Pro PW (AGP)"}, \
+ {0x1002, 0x5058, 0, "ATI Rage 128 Pro PX (AGP)"}, \
+ {0x1002, 0x5245, 0, "ATI Rage 128 RE (PCI)"}, \
+ {0x1002, 0x5246, 0, "ATI Rage 128 RF (AGP)"}, \
+ {0x1002, 0x5247, 0, "ATI Rage 128 RG (AGP)"}, \
+ {0x1002, 0x524b, 0, "ATI Rage 128 RK (PCI)"}, \
+ {0x1002, 0x524c, 0, "ATI Rage 128 RL (AGP)"}, \
+ {0x1002, 0x534d, 0, "ATI Rage 128 SM (AGP)"}, \
+ {0x1002, 0x5446, 0, "ATI Rage 128 Pro Ultra TF (AGP)"}, \
+ {0x1002, 0x544C, 0, "ATI Rage 128 Pro Ultra TL (AGP)"}, \
+ {0x1002, 0x5452, 0, "ATI Rage 128 Pro Ultra TR (AGP)"}, \
+ {0, 0, 0, NULL}
+
+#define mga_PCI_IDS \
+ {0x102b, 0x0521, 0, "Matrox G200 (AGP)"}, \
+ {0x102b, 0x0525, 0, "Matrox G400/G450 (AGP)"}, \
+ {0x102b, 0x2527, 0, "Matrox G550 (AGP)"}, \
+ {0, 0, 0, NULL}
+
+#define mach64_PCI_IDS \
+ {0x1002, 0x4749, 0, "3D Rage Pro"}, \
+ {0x1002, 0x4750, 0, "3D Rage Pro 215GP"}, \
+ {0x1002, 0x4751, 0, "3D Rage Pro 215GQ"}, \
+ {0x1002, 0x4742, 0, "3D Rage Pro AGP 1X/2X"}, \
+ {0x1002, 0x4744, 0, "3D Rage Pro AGP 1X"}, \
+ {0x1002, 0x4c49, 0, "3D Rage LT Pro"}, \
+ {0x1002, 0x4c50, 0, "3D Rage LT Pro"}, \
+ {0x1002, 0x4c51, 0, "3D Rage LT Pro"}, \
+ {0x1002, 0x4c42, 0, "3D Rage LT Pro AGP-133"}, \
+ {0x1002, 0x4c44, 0, "3D Rage LT Pro AGP-66"}, \
+ {0x1002, 0x474c, 0, "Rage XC"}, \
+ {0x1002, 0x474f, 0, "Rage XL"}, \
+ {0x1002, 0x4752, 0, "Rage XL"}, \
+ {0x1002, 0x4753, 0, "Rage XC"}, \
+ {0x1002, 0x474d, 0, "Rage XL AGP 2X"}, \
+ {0x1002, 0x474e, 0, "Rage XC AGP"}, \
+ {0x1002, 0x4c52, 0, "Rage Mobility P/M"}, \
+ {0x1002, 0x4c53, 0, "Rage Mobility L"}, \
+ {0x1002, 0x4c4d, 0, "Rage Mobility P/M AGP 2X"}, \
+ {0x1002, 0x4c4e, 0, "Rage Mobility L AGP 2X"}, \
+ {0, 0, 0, NULL}
+
+#define sisdrv_PCI_IDS \
+ {0x1039, 0x0300, 0, "SiS 300/305"}, \
+ {0x1039, 0x5300, 0, "SiS 540"}, \
+ {0x1039, 0x6300, 0, "SiS 630"}, \
+ {0x1039, 0x7300, 0, "SiS 730"}, \
+ {0, 0, 0, NULL}
+
+#define tdfx_PCI_IDS \
+ {0x121a, 0x0003, 0, "3dfx Voodoo Banshee"}, \
+ {0x121a, 0x0004, 0, "3dfx Voodoo3 2000"}, \
+ {0x121a, 0x0005, 0, "3dfx Voodoo3 3000"}, \
+ {0x121a, 0x0007, 0, "3dfx Voodoo4 4500"}, \
+ {0x121a, 0x0009, 0, "3dfx Voodoo5 5500"}, \
+ {0x121a, 0x000b, 0, "3dfx Voodoo4 4200"}, \
+ {0, 0, 0, NULL}
+
+#define viadrv_PCI_IDS \
+ {0x1106, 0x3022, 0, "VIA CLE266 3022"}, \
+ {0x1106, 0x3122, 0, "VIA CLE266"}, \
+ {0x1106, 0x7205, 0, "VIA KM400"}, \
+ {0x1106, 0x7204, 0, "VIA K8M800"}, \
+ {0, 0, 0, NULL}
+
+#define i810_PCI_IDS \
+ {0x8086, 0x7121, 0, "Intel i810 GMCH"}, \
+ {0x8086, 0x7123, 0, "Intel i810-DC100 GMCH"}, \
+ {0x8086, 0x7125, 0, "Intel i810E GMCH"}, \
+ {0x8086, 0x1132, 0, "Intel i815 GMCH"}, \
+ {0, 0, 0, NULL}
+
+#define i830_PCI_IDS \
+ {0x8086, 0x3577, 0, "Intel i830M GMCH"}, \
+ {0x8086, 0x2562, 0, "Intel i845G GMCH"}, \
+ {0x8086, 0x3582, 0, "Intel i852GM/i855GM GMCH"}, \
+ {0x8086, 0x2572, 0, "Intel i865G GMCH"}, \
+ {0, 0, 0, NULL}
+
+#define gamma_PCI_IDS \
+ {0x3d3d, 0x0008, 0, "3DLabs GLINT Gamma G1"}, \
+ {0, 0, 0, NULL}
+
+#define savage_PCI_IDS \
+ {0x5333, 0x8a22, 0, "Savage4"}, \
+ {0x5333, 0x8a23, 0, "Savage4"}, \
+ {0x5333, 0x8c10, 0, "Savage/MX-MV"}, \
+ {0x5333, 0x8c11, 0, "Savage/MX"}, \
+ {0x5333, 0x8c12, 0, "Savage/IX-MV"}, \
+ {0x5333, 0x8c13, 0, "Savage/IX"}, \
+ {0x5333, 0x8c20, 0, "Savage 3D"}, \
+ {0x5333, 0x8c21, 0, "Savage 3D/MV"}, \
+ {0x5333, 0x8c22, 0, "SuperSavage MX/128"}, \
+ {0x5333, 0x8c24, 0, "SuperSavage MX/64"}, \
+ {0x5333, 0x8c26, 0, "SuperSavage MX/64C"}, \
+ {0x5333, 0x8c2a, 0, "SuperSavage IX/128 SDR"}, \
+ {0x5333, 0x8c2b, 0, "SuperSavage IX/128 DDR"}, \
+ {0x5333, 0x8c2c, 0, "SuperSavage IX/64 SDR"}, \
+ {0x5333, 0x8c2d, 0, "SuperSavage IX/64 DDR"}, \
+ {0x5333, 0x8c2e, 0, "SuperSavage IX/C SDR"}, \
+ {0x5333, 0x8c2f, 0, "SuperSavage IX/C DDR"}, \
+ {0x5333, 0x8a25, 0, "ProSavage PM133"}, \
+ {0x5333, 0x8a26, 0, "ProSavage KM133"}, \
+ {0x5333, 0x8d01, 0, "ProSavage PN133"}, \
+ {0x5333, 0x8d02, 0, "ProSavage KN133"}, \
+ {0x5333, 0x8d04, 0, "ProSavage DDR"}, \
+ {0, 0, 0, NULL}
+
+#define ffb_PCI_IDS \
+ {0, 0, 0, NULL}
+
diff --git a/sys/dev/drm/drm_sarea.h b/sys/dev/drm/drm_sarea.h
index 093aca6..45bef82 100644
--- a/sys/dev/drm/drm_sarea.h
+++ b/sys/dev/drm/drm_sarea.h
@@ -2,7 +2,7 @@
* \file drm_sarea.h
* \brief SAREA definitions
*
- * \author Michel Dänzer <michel@daenzer.net>
+ * \author Michel D�zer <michel@daenzer.net>
*/
/*
@@ -34,9 +34,23 @@
#ifndef _DRM_SAREA_H_
#define _DRM_SAREA_H_
+#include "dev/drm/drm.h"
+
+/* SAREA area needs to be at least a page */
+#if defined(__alpha__)
+#define SAREA_MAX 0x2000
+#elif defined(__ia64__)
+#define SAREA_MAX 0x10000 /* 64kB */
+#else
+/* Intel 830M driver needs at least 8k SAREA */
+#define SAREA_MAX 0x2000
+#endif
+
/** Maximum number of drawables in the SAREA */
#define SAREA_MAX_DRAWABLES 256
+#define SAREA_DRAWABLE_CLAIMED_ENTRY 0x80000000
+
/** SAREA drawable */
typedef struct drm_sarea_drawable {
unsigned int stamp;
diff --git a/sys/dev/drm/mga.h b/sys/dev/drm/mga.h
index a9dd031..74a98ac 100644
--- a/sys/dev/drm/mga.h
+++ b/sys/dev/drm/mga.h
@@ -66,12 +66,6 @@
[DRM_IOCTL_NR(DRM_IOCTL_MGA_BLIT)] = { mga_dma_blit, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_MGA_GETPARAM)]= { mga_getparam, 1, 0 },
-#define DRIVER_PCI_IDS \
- {0x102b, 0x0521, 0, "Matrox G200 (AGP)"}, \
- {0x102b, 0x0525, 0, "Matrox G400/G450 (AGP)"}, \
- {0x102b, 0x2527, 0, "Matrox G550 (AGP)"}, \
- {0, 0, 0, NULL}
-
#define __HAVE_COUNTERS 3
#define __HAVE_COUNTER6 _DRM_STAT_IRQ
#define __HAVE_COUNTER7 _DRM_STAT_PRIMARY
@@ -79,7 +73,7 @@
/* Driver customization:
*/
-#define DRIVER_PRETAKEDOWN() do { \
+#define DRIVER_PRETAKEDOWN( dev ) do { \
mga_do_cleanup_dma( dev ); \
} while (0)
diff --git a/sys/dev/drm/mga_drm.h b/sys/dev/drm/mga_drm.h
index d511dac..57ecc16 100644
--- a/sys/dev/drm/mga_drm.h
+++ b/sys/dev/drm/mga_drm.h
@@ -119,6 +119,8 @@
#define MGA_NR_TEX_REGIONS 16
#define MGA_LOG_MIN_TEX_REGION_SIZE 16
+#define DRM_MGA_IDLE_RETRY 2048
+
#endif /* __MGA_SAREA_DEFINES__ */
@@ -232,16 +234,27 @@ typedef struct _drm_mga_sarea {
/* MGA specific ioctls
* The device specific ioctl range is 0x40 to 0x79.
*/
-#define DRM_IOCTL_MGA_INIT DRM_IOW( 0x40, drm_mga_init_t)
-#define DRM_IOCTL_MGA_FLUSH DRM_IOW( 0x41, drm_lock_t)
-#define DRM_IOCTL_MGA_RESET DRM_IO( 0x42)
-#define DRM_IOCTL_MGA_SWAP DRM_IO( 0x43)
-#define DRM_IOCTL_MGA_CLEAR DRM_IOW( 0x44, drm_mga_clear_t)
-#define DRM_IOCTL_MGA_VERTEX DRM_IOW( 0x45, drm_mga_vertex_t)
-#define DRM_IOCTL_MGA_INDICES DRM_IOW( 0x46, drm_mga_indices_t)
-#define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x47, drm_mga_iload_t)
-#define DRM_IOCTL_MGA_BLIT DRM_IOW( 0x48, drm_mga_blit_t)
-#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(0x49, drm_mga_getparam_t)
+#define DRM_MGA_INIT 0x00
+#define DRM_MGA_FLUSH 0x01
+#define DRM_MGA_RESET 0x02
+#define DRM_MGA_SWAP 0x03
+#define DRM_MGA_CLEAR 0x04
+#define DRM_MGA_VERTEX 0x05
+#define DRM_MGA_INDICES 0x06
+#define DRM_MGA_ILOAD 0x07
+#define DRM_MGA_BLIT 0x08
+#define DRM_MGA_GETPARAM 0x09
+
+#define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t)
+#define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, drm_lock_t)
+#define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET)
+#define DRM_IOCTL_MGA_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MGA_SWAP)
+#define DRM_IOCTL_MGA_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t)
+#define DRM_IOCTL_MGA_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t)
+#define DRM_IOCTL_MGA_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t)
+#define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
+#define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
+#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
typedef struct _drm_mga_warp_index {
int installed;
@@ -332,7 +345,7 @@ typedef struct _drm_mga_blit {
typedef struct drm_mga_getparam {
int param;
- int *value;
+ void *value;
} drm_mga_getparam_t;
#endif
diff --git a/sys/dev/drm/r128.h b/sys/dev/drm/r128.h
index 6ed9dea..3a22671 100644
--- a/sys/dev/drm/r128.h
+++ b/sys/dev/drm/r128.h
@@ -81,46 +81,6 @@
[DRM_IOCTL_NR(DRM_IOCTL_R128_INDIRECT)] = { r128_cce_indirect, 1, 1 }, \
[DRM_IOCTL_NR(DRM_IOCTL_R128_GETPARAM)] = { r128_getparam, 1, 0 },
-#define DRIVER_PCI_IDS \
- {0x1002, 0x4c45, 0, "ATI Rage 128 Mobility LE (PCI)"}, \
- {0x1002, 0x4c46, 0, "ATI Rage 128 Mobility LF (AGP)"}, \
- {0x1002, 0x4d46, 0, "ATI Rage 128 Mobility MF (AGP)"}, \
- {0x1002, 0x4d4c, 0, "ATI Rage 128 Mobility ML (AGP)"}, \
- {0x1002, 0x5041, 0, "ATI Rage 128 Pro PA (PCI)"}, \
- {0x1002, 0x5042, 0, "ATI Rage 128 Pro PB (AGP)"}, \
- {0x1002, 0x5043, 0, "ATI Rage 128 Pro PC (AGP)"}, \
- {0x1002, 0x5044, 0, "ATI Rage 128 Pro PD (PCI)"}, \
- {0x1002, 0x5045, 0, "ATI Rage 128 Pro PE (AGP)"}, \
- {0x1002, 0x5046, 0, "ATI Rage 128 Pro PF (AGP)"}, \
- {0x1002, 0x5047, 0, "ATI Rage 128 Pro PG (PCI)"}, \
- {0x1002, 0x5048, 0, "ATI Rage 128 Pro PH (AGP)"}, \
- {0x1002, 0x5049, 0, "ATI Rage 128 Pro PI (AGP)"}, \
- {0x1002, 0x504A, 0, "ATI Rage 128 Pro PJ (PCI)"}, \
- {0x1002, 0x504B, 0, "ATI Rage 128 Pro PK (AGP)"}, \
- {0x1002, 0x504C, 0, "ATI Rage 128 Pro PL (AGP)"}, \
- {0x1002, 0x504D, 0, "ATI Rage 128 Pro PM (PCI)"}, \
- {0x1002, 0x504E, 0, "ATI Rage 128 Pro PN (AGP)"}, \
- {0x1002, 0x504F, 0, "ATI Rage 128 Pro PO (AGP)"}, \
- {0x1002, 0x5050, 0, "ATI Rage 128 Pro PP (PCI)"}, \
- {0x1002, 0x5051, 0, "ATI Rage 128 Pro PQ (AGP)"}, \
- {0x1002, 0x5052, 0, "ATI Rage 128 Pro PR (PCI)"}, \
- {0x1002, 0x5053, 0, "ATI Rage 128 Pro PS (PCI)"}, \
- {0x1002, 0x5054, 0, "ATI Rage 128 Pro PT (AGP)"}, \
- {0x1002, 0x5055, 0, "ATI Rage 128 Pro PU (AGP)"}, \
- {0x1002, 0x5056, 0, "ATI Rage 128 Pro PV (PCI)"}, \
- {0x1002, 0x5057, 0, "ATI Rage 128 Pro PW (AGP)"}, \
- {0x1002, 0x5058, 0, "ATI Rage 128 Pro PX (AGP)"}, \
- {0x1002, 0x5245, 0, "ATI Rage 128 RE (PCI)"}, \
- {0x1002, 0x5246, 0, "ATI Rage 128 RF (AGP)"}, \
- {0x1002, 0x5247, 0, "ATI Rage 128 RG (AGP)"}, \
- {0x1002, 0x524b, 0, "ATI Rage 128 RK (PCI)"}, \
- {0x1002, 0x524c, 0, "ATI Rage 128 RL (AGP)"}, \
- {0x1002, 0x534d, 0, "ATI Rage 128 SM (AGP)"}, \
- {0x1002, 0x5446, 0, "ATI Rage 128 Pro Ultra TF (AGP)"}, \
- {0x1002, 0x544C, 0, "ATI Rage 128 Pro Ultra TL (AGP)"}, \
- {0x1002, 0x5452, 0, "ATI Rage 128 Pro Ultra TR (AGP)"}, \
- {0, 0, 0, NULL}
-
/* Driver customization:
*/
#define DRIVER_PRERELEASE() do { \
@@ -132,7 +92,7 @@
} \
} while (0)
-#define DRIVER_PRETAKEDOWN() do { \
+#define DRIVER_PRETAKEDOWN(dev) do { \
r128_do_cleanup_cce( dev ); \
} while (0)
diff --git a/sys/dev/drm/r128_drm.h b/sys/dev/drm/r128_drm.h
index 45c6bf6..30b8b3e 100644
--- a/sys/dev/drm/r128_drm.h
+++ b/sys/dev/drm/r128_drm.h
@@ -178,24 +178,47 @@ typedef struct drm_r128_sarea {
/* Rage 128 specific ioctls
* The device specific ioctl range is 0x40 to 0x79.
*/
-#define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t)
-#define DRM_IOCTL_R128_CCE_START DRM_IO( 0x41)
-#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( 0x42, drm_r128_cce_stop_t)
-#define DRM_IOCTL_R128_CCE_RESET DRM_IO( 0x43)
-#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( 0x44)
-#define DRM_IOCTL_R128_RESET DRM_IO( 0x46)
-#define DRM_IOCTL_R128_SWAP DRM_IO( 0x47)
-#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x48, drm_r128_clear_t)
-#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x49, drm_r128_vertex_t)
-#define DRM_IOCTL_R128_INDICES DRM_IOW( 0x4a, drm_r128_indices_t)
-#define DRM_IOCTL_R128_BLIT DRM_IOW( 0x4b, drm_r128_blit_t)
-#define DRM_IOCTL_R128_DEPTH DRM_IOW( 0x4c, drm_r128_depth_t)
-#define DRM_IOCTL_R128_STIPPLE DRM_IOW( 0x4d, drm_r128_stipple_t)
-#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(0x4f, drm_r128_indirect_t)
-#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( 0x50, drm_r128_fullscreen_t)
-#define DRM_IOCTL_R128_CLEAR2 DRM_IOW( 0x51, drm_r128_clear2_t)
-#define DRM_IOCTL_R128_GETPARAM DRM_IOW( 0x52, drm_r128_getparam_t)
-#define DRM_IOCTL_R128_FLIP DRM_IO( 0x53)
+#define DRM_R128_INIT 0x00
+#define DRM_R128_CCE_START 0x01
+#define DRM_R128_CCE_STOP 0x02
+#define DRM_R128_CCE_RESET 0x03
+#define DRM_R128_CCE_IDLE 0x04
+/* 0x05 not used */
+#define DRM_R128_RESET 0x06
+#define DRM_R128_SWAP 0x07
+#define DRM_R128_CLEAR 0x08
+#define DRM_R128_VERTEX 0x09
+#define DRM_R128_INDICES 0x0a
+#define DRM_R128_BLIT 0x0b
+#define DRM_R128_DEPTH 0x0c
+#define DRM_R128_STIPPLE 0x0d
+/* 0x0e not used */
+#define DRM_R128_INDIRECT 0x0f
+#define DRM_R128_FULLSCREEN 0x10
+#define DRM_R128_CLEAR2 0x11
+#define DRM_R128_GETPARAM 0x12
+#define DRM_R128_FLIP 0x13
+
+#define DRM_IOCTL_R128_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INIT, drm_r128_init_t)
+#define DRM_IOCTL_R128_CCE_START DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_START)
+#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CCE_STOP, drm_r128_cce_stop_t)
+#define DRM_IOCTL_R128_CCE_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_RESET)
+#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_IDLE)
+/* 0x05 not used */
+#define DRM_IOCTL_R128_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_RESET)
+#define DRM_IOCTL_R128_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_R128_SWAP)
+#define DRM_IOCTL_R128_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR, drm_r128_clear_t)
+#define DRM_IOCTL_R128_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_R128_VERTEX, drm_r128_vertex_t)
+#define DRM_IOCTL_R128_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INDICES, drm_r128_indices_t)
+#define DRM_IOCTL_R128_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_BLIT, drm_r128_blit_t)
+#define DRM_IOCTL_R128_DEPTH DRM_IOW( DRM_COMMAND_BASE + DRM_R128_DEPTH, drm_r128_depth_t)
+#define DRM_IOCTL_R128_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_R128_STIPPLE, drm_r128_stipple_t)
+/* 0x0e not used */
+#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_INDIRECT, drm_r128_indirect_t)
+#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_R128_FULLSCREEN, drm_r128_fullscreen_t)
+#define DRM_IOCTL_R128_CLEAR2 DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t)
+#define DRM_IOCTL_R128_GETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t)
+#define DRM_IOCTL_R128_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_R128_FLIP)
typedef struct drm_r128_init {
enum {
@@ -318,7 +341,7 @@ typedef struct drm_r128_fullscreen {
typedef struct drm_r128_getparam {
int param;
- int *value;
+ void *value;
} drm_r128_getparam_t;
#endif
diff --git a/sys/dev/drm/r128_state.c b/sys/dev/drm/r128_state.c
index 5a97ac0..703d550 100644
--- a/sys/dev/drm/r128_state.c
+++ b/sys/dev/drm/r128_state.c
@@ -917,9 +917,9 @@ static int r128_cce_dispatch_write_span( drm_device_t *dev,
DRM_DEBUG( "\n" );
count = depth->n;
- if ( count > 4096 || count <= 0 ) {
+ if (count > 4096 || count <= 0)
return DRM_ERR(EMSGSIZE);
- }
+
if ( DRM_COPY_FROM_USER( &x, depth->x, sizeof(x) ) ) {
return DRM_ERR(EFAULT);
}
@@ -1013,15 +1013,11 @@ static int r128_cce_dispatch_write_pixels( drm_device_t *dev,
DRM_DEBUG( "\n" );
count = depth->n;
- if ( count > 4096 || count <= 0 ) {
+ if (count > 4096 || count <= 0)
return DRM_ERR(EMSGSIZE);
- }
xbuf_size = count * sizeof(*x);
ybuf_size = count * sizeof(*y);
- if ( xbuf_size <= 0 || ybuf_size <= 0 ) {
- return DRM_ERR(EMSGSIZE);
- }
x = DRM_MALLOC( xbuf_size );
if ( x == NULL ) {
@@ -1137,10 +1133,9 @@ static int r128_cce_dispatch_read_span( drm_device_t *dev,
DRM_DEBUG( "\n" );
count = depth->n;
-
- if ( count > 4096 || count <= 0 ) {
+ if (count > 4096 || count <= 0)
return DRM_ERR(EMSGSIZE);
- }
+
if ( DRM_COPY_FROM_USER( &x, depth->x, sizeof(x) ) ) {
return DRM_ERR(EFAULT);
}
@@ -1183,15 +1178,15 @@ static int r128_cce_dispatch_read_pixels( drm_device_t *dev,
DRM_DEBUG( "%s\n", __FUNCTION__ );
count = depth->n;
+ if (count > 4096 || count <= 0)
+ return DRM_ERR(EMSGSIZE);
+
if ( count > dev_priv->depth_pitch ) {
count = dev_priv->depth_pitch;
}
xbuf_size = count * sizeof(*x);
ybuf_size = count * sizeof(*y);
- if ( xbuf_size <= 0 || ybuf_size <= 0 ) {
- return DRM_ERR(EMSGSIZE);
- }
x = DRM_MALLOC( xbuf_size );
if ( x == NULL ) {
return DRM_ERR(ENOMEM);
diff --git a/sys/dev/drm/radeon.h b/sys/dev/drm/radeon.h
index 6083f26..517d9d2 100644
--- a/sys/dev/drm/radeon.h
+++ b/sys/dev/drm/radeon.h
@@ -53,7 +53,7 @@
#define DRIVER_DATE "20020828"
#define DRIVER_MAJOR 1
-#define DRIVER_MINOR 10
+#define DRIVER_MINOR 11
#define DRIVER_PATCHLEVEL 0
/* Interface history:
@@ -86,6 +86,8 @@
* 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
* clients use to tell the DRM where they think the framebuffer is
* located in the card's address space
+ * 1.11 Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
+ * and GL_EXT_blend_[func|equation]_separate on r200
*/
#define DRIVER_IOCTLS \
[DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { radeon_cp_buffers, 1, 0 }, \
@@ -115,67 +117,6 @@
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_IRQ_WAIT)] = { radeon_irq_wait, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_SETPARAM)] = { radeon_cp_setparam, 1, 0 }, \
-#define DRIVER_PCI_IDS \
- {0x1002, 0x4136, 0, "ATI Radeon RS100 IGP 320M"}, \
- {0x1002, 0x4137, 0, "ATI Radeon RS200 IGP"}, \
- {0x1002, 0x4237, 0, "ATI Radeon RS250 IGP"}, \
- {0x1002, 0x4242, 0, "ATI Radeon BB R200 AIW 8500DV"}, \
- {0x1002, 0x4242, 0, "ATI Radeon BC R200"}, \
- {0x1002, 0x4336, 0, "ATI Radeon RS100 Mobility U1"}, \
- {0x1002, 0x4337, 0, "ATI Radeon RS200 Mobility IGP 340M"}, \
- {0x1002, 0x4437, 0, "ATI Radeon RS250 Mobility IGP"}, \
- {0x1002, 0x4964, 0, "ATI Radeon Id R250 9000"}, \
- {0x1002, 0x4965, 0, "ATI Radeon Ie R250 9000"}, \
- {0x1002, 0x4966, 0, "ATI Radeon If R250 9000"}, \
- {0x1002, 0x4967, 0, "ATI Radeon Ig R250 9000"}, \
- {0x1002, 0x4C57, 0, "ATI Radeon LW Mobility 7500 M7"}, \
- {0x1002, 0x4C58, 0, "ATI Radeon LX RV200 Mobility FireGL 7800 M7"}, \
- {0x1002, 0x4C59, 0, "ATI Radeon LY Mobility M6"}, \
- {0x1002, 0x4C5A, 0, "ATI Radeon LZ Mobility M6"}, \
- {0x1002, 0x4C64, 0, "ATI Radeon Ld R250 Mobility 9000 M9"}, \
- {0x1002, 0x4C65, 0, "ATI Radeon Le R250 Mobility 9000 M9"}, \
- {0x1002, 0x4C66, 0, "ATI Radeon Lf R250 Mobility 9000 M9"}, \
- {0x1002, 0x4C67, 0, "ATI Radeon Lg R250 Mobility 9000 M9"}, \
- {0x1002, 0x5144, 0, "ATI Radeon QD R100"}, \
- {0x1002, 0x5145, 0, "ATI Radeon QE R100"}, \
- {0x1002, 0x5146, 0, "ATI Radeon QF R100"}, \
- {0x1002, 0x5147, 0, "ATI Radeon QG R100"}, \
- {0x1002, 0x5148, 0, "ATI Radeon QH R200 8500"}, \
- {0x1002, 0x5149, 0, "ATI Radeon QI R200"}, \
- {0x1002, 0x514A, 0, "ATI Radeon QJ R200"}, \
- {0x1002, 0x514B, 0, "ATI Radeon QK R200"}, \
- {0x1002, 0x514C, 0, "ATI Radeon QL R200 8500 LE"}, \
- {0x1002, 0x514D, 0, "ATI Radeon QM R200 9100"}, \
- {0x1002, 0x514E, 0, "ATI Radeon QN R200 8500 LE"}, \
- {0x1002, 0x514F, 0, "ATI Radeon QO R200 8500 LE"}, \
- {0x1002, 0x5157, 0, "ATI Radeon QW RV200 7500"}, \
- {0x1002, 0x5158, 0, "ATI Radeon QX RV200 7500"}, \
- {0x1002, 0x5159, 0, "ATI Radeon QY RV100 7000/VE"}, \
- {0x1002, 0x515A, 0, "ATI Radeon QZ RV100 7000/VE"}, \
- {0x1002, 0x5168, 0, "ATI Radeon Qh R200"}, \
- {0x1002, 0x5169, 0, "ATI Radeon Qi R200"}, \
- {0x1002, 0x516A, 0, "ATI Radeon Qj R200"}, \
- {0x1002, 0x516B, 0, "ATI Radeon Qk R200"}, \
- {0x1002, 0x516C, 0, "ATI Radeon Ql R200"}, \
- {0x1002, 0x5834, 0, "ATI Radeon RS300 IGP"}, \
- {0x1002, 0x5835, 0, "ATI Radeon RS300 Mobility IGP"}, \
- {0x1002, 0x5836, 0, "ATI Radeon RS300 IGP"}, \
- {0x1002, 0x5837, 0, "ATI Radeon RS300 IGP"}, \
- {0x1002, 0x5960, 0, "ATI Radeon RV280 9200"}, \
- {0x1002, 0x5961, 0, "ATI Radeon RV280 9200 SE"}, \
- {0x1002, 0x5962, 0, "ATI Radeon RV280 9200"}, \
- {0x1002, 0x5963, 0, "ATI Radeon RV280 9200"}, \
- {0x1002, 0x5964, 0, "ATI Radeon RV280 9200 SE"}, \
- {0x1002, 0x5968, 0, "ATI Radeon RV280 9200"}, \
- {0x1002, 0x5969, 0, "ATI Radeon RV280 9200"}, \
- {0x1002, 0x596A, 0, "ATI Radeon RV280 9200"}, \
- {0x1002, 0x596B, 0, "ATI Radeon RV280 9200"}, \
- {0x1002, 0x5c61, 0, "ATI Radeon RV280 Mobility"}, \
- {0x1002, 0x5c62, 0, "ATI Radeon RV280"}, \
- {0x1002, 0x5c63, 0, "ATI Radeon RV280 Mobility"}, \
- {0x1002, 0x5c64, 0, "ATI Radeon RV280"}, \
- {0, 0, 0, NULL}
-
#define DRIVER_FILE_FIELDS \
int64_t radeon_fb_delta; \
@@ -209,7 +150,7 @@ do { \
/* When the last client dies, shut down the CP and free dev->dev_priv.
*/
/* #define __HAVE_RELEASE 1 */
-#define DRIVER_PRETAKEDOWN() \
+#define DRIVER_PRETAKEDOWN( dev ) \
do { \
radeon_do_release( dev ); \
} while (0)
diff --git a/sys/dev/drm/radeon_drm.h b/sys/dev/drm/radeon_drm.h
index bd4dde3..51bbacf 100644
--- a/sys/dev/drm/radeon_drm.h
+++ b/sys/dev/drm/radeon_drm.h
@@ -146,7 +146,8 @@
#define RADEON_EMIT_PP_TEX_SIZE_0 73
#define RADEON_EMIT_PP_TEX_SIZE_1 74
#define RADEON_EMIT_PP_TEX_SIZE_2 75
-#define RADEON_MAX_STATE_PACKETS 76
+#define R200_EMIT_RB3D_BLENDCOLOR 76
+#define RADEON_MAX_STATE_PACKETS 77
/* Commands understood by cmd_buffer ioctl. More can be added but
@@ -228,6 +229,13 @@ typedef union {
#define RADEON_MAX_TEXTURE_LEVELS 12
#define RADEON_MAX_TEXTURE_UNITS 3
+/* Blits have strict offset rules. All blit offset must be aligned on
+ * a 1K-byte boundary.
+ */
+#define RADEON_OFFSET_SHIFT 10
+#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)
+#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
+
#endif /* __RADEON_SAREA_DEFINES__ */
typedef struct {
@@ -367,32 +375,58 @@ typedef struct {
/* Radeon specific ioctls
* The device specific ioctl range is 0x40 to 0x79.
*/
-#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( 0x40, drm_radeon_init_t)
-#define DRM_IOCTL_RADEON_CP_START DRM_IO( 0x41)
-#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( 0x42, drm_radeon_cp_stop_t)
-#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( 0x43)
-#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( 0x44)
-#define DRM_IOCTL_RADEON_RESET DRM_IO( 0x45)
-#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( 0x46, drm_radeon_fullscreen_t)
-#define DRM_IOCTL_RADEON_SWAP DRM_IO( 0x47)
-#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( 0x48, drm_radeon_clear_t)
-#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( 0x49, drm_radeon_vertex_t)
-#define DRM_IOCTL_RADEON_INDICES DRM_IOW( 0x4a, drm_radeon_indices_t)
-#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( 0x4c, drm_radeon_stipple_t)
-#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(0x4d, drm_radeon_indirect_t)
-#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(0x4e, drm_radeon_texture_t)
-#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( 0x4f, drm_radeon_vertex2_t)
-#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( 0x50, drm_radeon_cmd_buffer_t)
-#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(0x51, drm_radeon_getparam_t)
-#define DRM_IOCTL_RADEON_FLIP DRM_IO( 0x52)
-#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR( 0x53, drm_radeon_mem_alloc_t)
-#define DRM_IOCTL_RADEON_FREE DRM_IOW( 0x54, drm_radeon_mem_free_t)
-#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( 0x55, drm_radeon_mem_init_heap_t)
-#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR( 0x56, drm_radeon_irq_emit_t)
-#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( 0x57, drm_radeon_irq_wait_t)
-/* added by Charl P. Botha - see radeon_cp.c for details */
-#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO(0x58)
-#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW(0x59, drm_radeon_setparam_t)
+#define DRM_RADEON_CP_INIT 0x00
+#define DRM_RADEON_CP_START 0x01
+#define DRM_RADEON_CP_STOP 0x02
+#define DRM_RADEON_CP_RESET 0x03
+#define DRM_RADEON_CP_IDLE 0x04
+#define DRM_RADEON_RESET 0x05
+#define DRM_RADEON_FULLSCREEN 0x06
+#define DRM_RADEON_SWAP 0x07
+#define DRM_RADEON_CLEAR 0x08
+#define DRM_RADEON_VERTEX 0x09
+#define DRM_RADEON_INDICES 0x0A
+#define DRM_RADEON_NOT_USED
+#define DRM_RADEON_STIPPLE 0x0C
+#define DRM_RADEON_INDIRECT 0x0D
+#define DRM_RADEON_TEXTURE 0x0E
+#define DRM_RADEON_VERTEX2 0x0F
+#define DRM_RADEON_CMDBUF 0x10
+#define DRM_RADEON_GETPARAM 0x11
+#define DRM_RADEON_FLIP 0x12
+#define DRM_RADEON_ALLOC 0x13
+#define DRM_RADEON_FREE 0x14
+#define DRM_RADEON_INIT_HEAP 0x15
+#define DRM_RADEON_IRQ_EMIT 0x16
+#define DRM_RADEON_IRQ_WAIT 0x17
+#define DRM_RADEON_CP_RESUME 0x18
+#define DRM_RADEON_SETPARAM 0x19
+
+#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
+#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
+#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
+#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
+#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
+#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET)
+#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
+#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP)
+#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
+#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
+#define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
+#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
+#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
+#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
+#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
+#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
+#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
+#define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP)
+#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
+#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
+#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
+#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
+#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
+#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
+#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
typedef struct drm_radeon_init {
enum {
@@ -544,7 +578,7 @@ typedef struct drm_radeon_indirect {
typedef struct drm_radeon_getparam {
int param;
- int *value;
+ void *value;
} drm_radeon_getparam_t;
/* 1.6: Set up a memory manager for regions of shared memory:
diff --git a/sys/dev/drm/radeon_drv.h b/sys/dev/drm/radeon_drv.h
index 3794db9..d14d342 100644
--- a/sys/dev/drm/radeon_drv.h
+++ b/sys/dev/drm/radeon_drv.h
@@ -692,6 +692,7 @@ extern void radeon_do_release(drm_device_t *dev);
#define R200_SE_VTX_FMT_1 0x208c
#define R200_RE_CNTL 0x1c50
+#define R200_RB3D_BLENDCOLOR 0x3218
/* Constants */
#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
diff --git a/sys/dev/drm/radeon_mem.c b/sys/dev/drm/radeon_mem.c
index ed72dd6..3238c27 100644
--- a/sys/dev/drm/radeon_mem.c
+++ b/sys/dev/drm/radeon_mem.c
@@ -141,12 +141,12 @@ static int init_heap(struct mem_block **heap, int start, int size)
struct mem_block *blocks = DRM_MALLOC(sizeof(*blocks));
if (!blocks)
- return -ENOMEM;
+ return DRM_ERR(ENOMEM);
*heap = DRM_MALLOC(sizeof(**heap));
if (!*heap) {
DRM_FREE( blocks, sizeof(*blocks) );
- return -ENOMEM;
+ return DRM_ERR(ENOMEM);
}
blocks->start = start;
diff --git a/sys/dev/drm/radeon_state.c b/sys/dev/drm/radeon_state.c
index 8f61005..950a8ee 100644
--- a/sys/dev/drm/radeon_state.c
+++ b/sys/dev/drm/radeon_state.c
@@ -82,37 +82,58 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
drm_file_t *filp_priv,
int id,
u32 *data ) {
- if ( id == RADEON_EMIT_PP_MISC &&
- radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
- &data[( RADEON_RB3D_DEPTHOFFSET
- - RADEON_PP_MISC ) / 4] ) ) {
- DRM_ERROR( "Invalid depth buffer offset\n" );
- return DRM_ERR( EINVAL );
- } else if ( id == RADEON_EMIT_PP_CNTL &&
- radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
- &data[( RADEON_RB3D_COLOROFFSET
- - RADEON_PP_CNTL ) / 4] ) ) {
- DRM_ERROR( "Invalid colour buffer offset\n" );
- return DRM_ERR( EINVAL );
- } else if ( id >= R200_EMIT_PP_TXOFFSET_0 &&
- id <= R200_EMIT_PP_TXOFFSET_5 &&
- radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
- &data[0] ) ) {
- DRM_ERROR( "Invalid R200 texture offset\n" );
- return DRM_ERR( EINVAL );
- } else if ( ( id == RADEON_EMIT_PP_TXFILTER_0 || id == RADEON_EMIT_PP_TXFILTER_1 ||
- id == RADEON_EMIT_PP_TXFILTER_2 /*|| id == RADEON_EMIT_PP_TXFILTER_3 ||
- id == RADEON_EMIT_PP_TXFILTER_4 || id == RADEON_EMIT_PP_TXFILTER_5*/ ) &&
- radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
- &data[( RADEON_PP_TXOFFSET_0
- - RADEON_PP_TXFILTER_0 ) / 4] ) ) {
- DRM_ERROR( "Invalid R100 texture offset\n" );
- return DRM_ERR( EINVAL );
- } else if ( id == R200_PP_CUBIC_OFFSET_F1_0 || id == R200_PP_CUBIC_OFFSET_F1_1 ||
- id == R200_PP_CUBIC_OFFSET_F1_2 || id == R200_PP_CUBIC_OFFSET_F1_3 ||
- id == R200_PP_CUBIC_OFFSET_F1_4 || id == R200_PP_CUBIC_OFFSET_F1_5 ) {
+ switch ( id ) {
+
+ case RADEON_EMIT_PP_MISC:
+ if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
+ &data[( RADEON_RB3D_DEPTHOFFSET
+ - RADEON_PP_MISC ) / 4] ) ) {
+ DRM_ERROR( "Invalid depth buffer offset\n" );
+ return DRM_ERR( EINVAL );
+ }
+ break;
+
+ case RADEON_EMIT_PP_CNTL:
+ if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
+ &data[( RADEON_RB3D_COLOROFFSET
+ - RADEON_PP_CNTL ) / 4] ) ) {
+ DRM_ERROR( "Invalid colour buffer offset\n" );
+ return DRM_ERR( EINVAL );
+ }
+ break;
+
+ case R200_EMIT_PP_TXOFFSET_0:
+ case R200_EMIT_PP_TXOFFSET_1:
+ case R200_EMIT_PP_TXOFFSET_2:
+ case R200_EMIT_PP_TXOFFSET_3:
+ case R200_EMIT_PP_TXOFFSET_4:
+ case R200_EMIT_PP_TXOFFSET_5:
+ if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
+ &data[0] ) ) {
+ DRM_ERROR( "Invalid R200 texture offset\n" );
+ return DRM_ERR( EINVAL );
+ }
+ break;
+
+ case RADEON_EMIT_PP_TXFILTER_0:
+ case RADEON_EMIT_PP_TXFILTER_1:
+ case RADEON_EMIT_PP_TXFILTER_2:
+ if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
+ &data[( RADEON_PP_TXOFFSET_0
+ - RADEON_PP_TXFILTER_0 ) / 4] ) ) {
+ DRM_ERROR( "Invalid R100 texture offset\n" );
+ return DRM_ERR( EINVAL );
+ }
+ break;
+
+ case R200_EMIT_PP_CUBIC_OFFSETS_0:
+ case R200_EMIT_PP_CUBIC_OFFSETS_1:
+ case R200_EMIT_PP_CUBIC_OFFSETS_2:
+ case R200_EMIT_PP_CUBIC_OFFSETS_3:
+ case R200_EMIT_PP_CUBIC_OFFSETS_4:
+ case R200_EMIT_PP_CUBIC_OFFSETS_5: {
int i;
- for ( i = 0; i < 6; i++ ) {
+ for ( i = 0; i < 5; i++ ) {
if ( radeon_check_and_fixup_offset_user( dev_priv,
filp_priv,
&data[i] ) ) {
@@ -120,6 +141,75 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
return DRM_ERR( EINVAL );
}
}
+ break;
+ }
+
+ case RADEON_EMIT_RB3D_COLORPITCH:
+ case RADEON_EMIT_RE_LINE_PATTERN:
+ case RADEON_EMIT_SE_LINE_WIDTH:
+ case RADEON_EMIT_PP_LUM_MATRIX:
+ case RADEON_EMIT_PP_ROT_MATRIX_0:
+ case RADEON_EMIT_RB3D_STENCILREFMASK:
+ case RADEON_EMIT_SE_VPORT_XSCALE:
+ case RADEON_EMIT_SE_CNTL:
+ case RADEON_EMIT_SE_CNTL_STATUS:
+ case RADEON_EMIT_RE_MISC:
+ case RADEON_EMIT_PP_BORDER_COLOR_0:
+ case RADEON_EMIT_PP_BORDER_COLOR_1:
+ case RADEON_EMIT_PP_BORDER_COLOR_2:
+ case RADEON_EMIT_SE_ZBIAS_FACTOR:
+ case RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT:
+ case RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED:
+ case R200_EMIT_PP_TXCBLEND_0:
+ case R200_EMIT_PP_TXCBLEND_1:
+ case R200_EMIT_PP_TXCBLEND_2:
+ case R200_EMIT_PP_TXCBLEND_3:
+ case R200_EMIT_PP_TXCBLEND_4:
+ case R200_EMIT_PP_TXCBLEND_5:
+ case R200_EMIT_PP_TXCBLEND_6:
+ case R200_EMIT_PP_TXCBLEND_7:
+ case R200_EMIT_TCL_LIGHT_MODEL_CTL_0:
+ case R200_EMIT_TFACTOR_0:
+ case R200_EMIT_VTX_FMT_0:
+ case R200_EMIT_VAP_CTL:
+ case R200_EMIT_MATRIX_SELECT_0:
+ case R200_EMIT_TEX_PROC_CTL_2:
+ case R200_EMIT_TCL_UCP_VERT_BLEND_CTL:
+ case R200_EMIT_PP_TXFILTER_0:
+ case R200_EMIT_PP_TXFILTER_1:
+ case R200_EMIT_PP_TXFILTER_2:
+ case R200_EMIT_PP_TXFILTER_3:
+ case R200_EMIT_PP_TXFILTER_4:
+ case R200_EMIT_PP_TXFILTER_5:
+ case R200_EMIT_VTE_CNTL:
+ case R200_EMIT_OUTPUT_VTX_COMP_SEL:
+ case R200_EMIT_PP_TAM_DEBUG3:
+ case R200_EMIT_PP_CNTL_X:
+ case R200_EMIT_RB3D_DEPTHXY_OFFSET:
+ case R200_EMIT_RE_AUX_SCISSOR_CNTL:
+ case R200_EMIT_RE_SCISSOR_TL_0:
+ case R200_EMIT_RE_SCISSOR_TL_1:
+ case R200_EMIT_RE_SCISSOR_TL_2:
+ case R200_EMIT_SE_VAP_CNTL_STATUS:
+ case R200_EMIT_SE_VTX_STATE_CNTL:
+ case R200_EMIT_RE_POINTSIZE:
+ case R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0:
+ case R200_EMIT_PP_CUBIC_FACES_0:
+ case R200_EMIT_PP_CUBIC_FACES_1:
+ case R200_EMIT_PP_CUBIC_FACES_2:
+ case R200_EMIT_PP_CUBIC_FACES_3:
+ case R200_EMIT_PP_CUBIC_FACES_4:
+ case R200_EMIT_PP_CUBIC_FACES_5:
+ case RADEON_EMIT_PP_TEX_SIZE_0:
+ case RADEON_EMIT_PP_TEX_SIZE_1:
+ case RADEON_EMIT_PP_TEX_SIZE_2:
+ case R200_EMIT_RB3D_BLENDCOLOR:
+ /* These packets don't contain memory offsets */
+ break;
+
+ default:
+ DRM_ERROR( "Unknown state packet ID %d\n", id );
+ return DRM_ERR( EINVAL );
}
return 0;
@@ -475,7 +565,8 @@ static struct {
{ R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" },
{ RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
{ RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" },
- { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_1" },
+ { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" },
+ { R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR" },
};
@@ -1410,7 +1501,7 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
/* Update the input parameters for next time */
image->y += height;
image->height -= height;
- (const u8 *)image->data += size;
+ image->data = (const u8 *)image->data + size;
} while (image->height > 0);
/* Flush the pixel cache after the blit completes. This ensures
@@ -2398,10 +2489,21 @@ int radeon_cp_getparam( DRM_IOCTL_ARGS )
case RADEON_PARAM_STATUS_HANDLE:
value = dev_priv->ring_rptr_offset;
break;
+#if BITS_PER_LONG == 32
+ /*
+ * This ioctl() doesn't work on 64-bit platforms because hw_lock is a
+ * pointer which can't fit into an int-sized variable. According to
+ * Michel Dänzer, the ioctl() is only used on embedded platforms, so
+ * not supporting it shouldn't be a problem. If the same functionality
+ * is needed on 64-bit platforms, a new ioctl() would have to be added,
+ * so backwards-compatibility for the embedded platforms can be
+ * maintained. --davidm 4-Feb-2004.
+ */
case RADEON_PARAM_SAREA_HANDLE:
/* The lock is the first dword in the sarea. */
value = (long)dev->lock.hw_lock;
break;
+#endif
case RADEON_PARAM_GART_TEX_HANDLE:
value = dev_priv->gart_textures_offset;
break;
diff --git a/sys/dev/drm/sis.h b/sys/dev/drm/sis.h
index 59a439f..0349818 100644
--- a/sys/dev/drm/sis.h
+++ b/sys/dev/drm/sis.h
@@ -34,11 +34,7 @@
* Name it sisdrv_##x as there's a conflict with sis_free/malloc in the kernel
* that's used for fb devices
*/
-#ifdef __linux__
#define DRM(x) sisdrv_##x
-#else
-#define DRM(x) sis_##x
-#endif
/* General customization:
*/
@@ -63,13 +59,6 @@
[DRM_IOCTL_NR(DRM_IOCTL_SIS_AGP_FREE)] = { sis_ioctl_agp_free, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_SIS_FB_INIT)] = { sis_fb_init, 1, 1 }
-#define DRIVER_PCI_IDS \
- {0x1039, 0x0300, 0, "SiS 300/305"}, \
- {0x1039, 0x5300, 0, "SiS 540"}, \
- {0x1039, 0x6300, 0, "SiS 630"}, \
- {0x1039, 0x7300, 0, "SiS 730"}, \
- {0, 0, 0, NULL}
-
#define __HAVE_COUNTERS 5
/* Buffer customization:
diff --git a/sys/dev/drm/sis_drv.c b/sys/dev/drm/sis_drv.c
index c6aae19..ae6615b 100644
--- a/sys/dev/drm/sis_drv.c
+++ b/sys/dev/drm/sis_drv.c
@@ -47,7 +47,7 @@
#ifdef __FreeBSD__
/* Avoid clash with sis ethernet */
-DRIVER_MODULE(sisdrm, pci, sis_driver, sis_devclass, 0, 0);
+DRIVER_MODULE(sisdrm, pci, sisdrv_driver, sisdrv_devclass, 0, 0);
#elif defined(__NetBSD__)
CFDRIVER_DECL(sis, DV_TTY, NULL);
#endif /* __FreeBSD__ */
diff --git a/sys/dev/drm/sis_mm.c b/sys/dev/drm/sis_mm.c
index 837e224..6f29974 100644
--- a/sys/dev/drm/sis_mm.c
+++ b/sys/dev/drm/sis_mm.c
@@ -35,8 +35,12 @@
#include "dev/drm/sis_drv.h"
#include "dev/drm/sis_ds.h"
#if defined(__linux__) && defined(CONFIG_FB_SIS)
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+#include <video/sisfb.h>
+#else
#include <linux/sisfb.h>
#endif
+#endif
#define MAX_CONTEXT 100
#define VIDEO_TYPE 0
diff --git a/sys/dev/drm/tdfx.h b/sys/dev/drm/tdfx.h
index f9b91a9..cc2b720 100644
--- a/sys/dev/drm/tdfx.h
+++ b/sys/dev/drm/tdfx.h
@@ -51,12 +51,4 @@
#define DRIVER_MINOR 0
#define DRIVER_PATCHLEVEL 0
-#define DRIVER_PCI_IDS \
- {0x121a, 0x0003, 0, "3dfx Voodoo Banshee"}, \
- {0x121a, 0x0004, 0, "3dfx Voodoo3 2000"}, \
- {0x121a, 0x0005, 0, "3dfx Voodoo3 3000"}, \
- {0x121a, 0x0007, 0, "3dfx Voodoo4"}, \
- {0x121a, 0x0009, 0, "3dfx Voodoo5"}, \
- {0, 0, 0, NULL}
-
#endif
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