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| author | anholt <anholt@FreeBSD.org> | 2003-08-19 02:57:31 +0000 |
|---|---|---|
| committer | anholt <anholt@FreeBSD.org> | 2003-08-19 02:57:31 +0000 |
| commit | 55fc74037ce1fed2313813918c5380b1c642828e (patch) | |
| tree | e45c260fa868be8644bf3d316e3c7cc3cdc5a0eb /sys/dev/drm/radeon_drv.h | |
| parent | f9627255eea8f589c728f37d9a3a6e0040a24291 (diff) | |
| download | FreeBSD-src-55fc74037ce1fed2313813918c5380b1c642828e.zip FreeBSD-src-55fc74037ce1fed2313813918c5380b1c642828e.tar.gz | |
Update DRM from DRI CVS as of today. Notable changes include Radeon
suspend/resume support and Rage 128 pageflipping support (both of which require
XFree86 from CVS), along with miscellaneous cleanups.
Diffstat (limited to 'sys/dev/drm/radeon_drv.h')
| -rw-r--r-- | sys/dev/drm/radeon_drv.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/sys/dev/drm/radeon_drv.h b/sys/dev/drm/radeon_drv.h index 0276ebd..e23ec0f 100644 --- a/sys/dev/drm/radeon_drv.h +++ b/sys/dev/drm/radeon_drv.h @@ -161,6 +161,7 @@ extern int radeon_cp_start( DRM_IOCTL_ARGS ); extern int radeon_cp_stop( DRM_IOCTL_ARGS ); extern int radeon_cp_reset( DRM_IOCTL_ARGS ); extern int radeon_cp_idle( DRM_IOCTL_ARGS ); +extern int radeon_cp_resume( DRM_IOCTL_ARGS ); extern int radeon_engine_reset( DRM_IOCTL_ARGS ); extern int radeon_fullscreen( DRM_IOCTL_ARGS ); extern int radeon_cp_buffers( DRM_IOCTL_ARGS ); @@ -583,6 +584,7 @@ extern void radeon_do_release(drm_device_t *dev); #define RADEON_TXFORMAT_ARGB4444 5 #define RADEON_TXFORMAT_ARGB8888 6 #define RADEON_TXFORMAT_RGBA8888 7 +#define RADEON_TXFORMAT_Y8 8 #define RADEON_TXFORMAT_VYUY422 10 #define RADEON_TXFORMAT_YVYU422 11 #define RADEON_TXFORMAT_DXT1 12 @@ -669,6 +671,10 @@ extern void radeon_do_release(drm_device_t *dev); #define R200_RE_POINTSIZE 0x2648 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 +#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ +#define RADEON_PP_TEX_SIZE_1 0x1d0c +#define RADEON_PP_TEX_SIZE_2 0x1d14 + #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 @@ -854,7 +860,7 @@ do { \ #define COMMIT_RING() do { \ /* Flush writes to ring */ \ - DRM_READMEMORYBARRIER( dev_priv->mmio ); \ + DRM_MEMORYBARRIER(); \ GET_RING_HEAD( dev_priv ); \ RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \ /* read from PCI bus to ensure correct posting */ \ |
