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| author | rnoland <rnoland@FreeBSD.org> | 2008-10-13 17:43:39 +0000 |
|---|---|---|
| committer | rnoland <rnoland@FreeBSD.org> | 2008-10-13 17:43:39 +0000 |
| commit | 068d210a752c29c0e7606cce22c3315e2c39c65e (patch) | |
| tree | 9e397b595a87c63d15a10c6573bfae1f3b13e88f /sys/dev/drm/radeon_drv.h | |
| parent | f804ba14eb10285d959361160d71d2367815ccf7 (diff) | |
| download | FreeBSD-src-068d210a752c29c0e7606cce22c3315e2c39c65e.zip FreeBSD-src-068d210a752c29c0e7606cce22c3315e2c39c65e.tar.gz | |
Several of the newer radeon cards have moved around the registers for enabling
busmastering support. This also adds register definitions for MSI support,
which we will be using shortly.
Approved by: jhb (mentor)
Obtained from: drm git master
Diffstat (limited to 'sys/dev/drm/radeon_drv.h')
| -rw-r--r-- | sys/dev/drm/radeon_drv.h | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/sys/dev/drm/radeon_drv.h b/sys/dev/drm/radeon_drv.h index 1f04e46..5c4944a 100644 --- a/sys/dev/drm/radeon_drv.h +++ b/sys/dev/drm/radeon_drv.h @@ -126,6 +126,7 @@ enum radeon_family { CHIP_RV350, CHIP_RV380, CHIP_R420, + CHIP_R423, CHIP_RV410, CHIP_RS400, CHIP_RS480, @@ -434,8 +435,31 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev, # define RADEON_SCISSOR_1_ENABLE (1 << 29) # define RADEON_SCISSOR_2_ENABLE (1 << 30) +/* + * PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx) + * don't have an explicit bus mastering disable bit. It's handled + * by the PCI D-states. PMI_BM_DIS disables D-state bus master + * handling, not bus mastering itself. + */ #define RADEON_BUS_CNTL 0x0030 +/* r1xx, r2xx, r300, r(v)350, r420/r481, rs480 */ # define RADEON_BUS_MASTER_DIS (1 << 6) +/* rs400, rs690/rs740 */ +# define RS400_BUS_MASTER_DIS (1 << 14) +# define RS400_MSI_REARM (1 << 20) +/* see RS480_MSI_REARM in AIC_CNTL for rs480 */ + +#define RADEON_BUS_CNTL1 0x0034 +# define RADEON_PMI_BM_DIS (1 << 2) +# define RADEON_PMI_INT_DIS (1 << 3) + +#define RV370_BUS_CNTL 0x004c +# define RV370_PMI_BM_DIS (1 << 5) +# define RV370_PMI_INT_DIS (1 << 6) + +#define RADEON_MSI_REARM_EN 0x0160 +/* rv370/rv380, rv410, r423/r430/r480, r5xx */ +# define RV370_MSI_REARM_EN (1 << 0) #define RADEON_CLOCK_CNTL_DATA 0x000c # define RADEON_PLL_WR_EN (1 << 7) @@ -915,6 +939,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev, #define RADEON_AIC_CNTL 0x01d0 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0) +# define RS480_MSI_REARM (1 << 3) #define RADEON_AIC_STAT 0x01d4 #define RADEON_AIC_PT_BASE 0x01d8 #define RADEON_AIC_LO_ADDR 0x01dc |
