- Convert dpt_pci.c to newbus.

- Add support for ISA based DPT adapters (this doesn't quite work yet).
- Sync dpt_eisa.c with my local copy.
  - Simplify how EISA IDs are matched.
  - Prototype.
  - Formatting nits.
  - Conform to how I do things in dpt_pci.c/dpt_isa.c.
- Modify dpt_scsi.c:dpt_alloc() to DTRT with newbus.
- Add some comments to dpt_scsi.c:dpt_pio_get_conf().
- Add additional check to dpt_scsi.c:dpt_get_conf().
- Add some useful error messages to dpt_scsi.c:dpt_init().

6 files changed, 431 insertions, 457 deletions

diff --git a/sys/dev/dpt/dpt.h b/sys/dev/dpt/dpt.h
index f2d1c22..6d6230e 100644
--- a/sys/dev/dpt/dpt.h
+++ b/sys/dev/dpt/dpt.h
@@ -1270,8 +1270,9 @@ extern TAILQ_HEAD(dpt_softc_list, dpt_softc) dpt_softcs;
 
 extern int		dpt_controllers_present;
 
-struct dpt_softc*	dpt_alloc(u_int unit, bus_space_tag_t tag,
-				  bus_space_handle_t bsh);
+#ifdef _KERNEL
+dpt_softc_t *		dpt_alloc(device_t, bus_space_tag_t, bus_space_handle_t);
+#endif
 void			dpt_free(struct dpt_softc *dpt);
 int			dpt_init(struct dpt_softc *dpt);
 int			dpt_attach(dpt_softc_t * dpt);
diff --git a/sys/dev/dpt/dpt_eisa.c b/sys/dev/dpt/dpt_eisa.c
index 9fc558b..7dae870 100644
--- a/sys/dev/dpt/dpt_eisa.c
+++ b/sys/dev/dpt/dpt_eisa.c
@@ -1,48 +1,33 @@
-/*
- *       Copyright (c) 1997 by Matthew N. Dodd <winter@jurai.net>
- *       All Rights Reserved
+/*-
+ * Copyright (c) 1997, 2000 Matthew N. Dodd <winter@jurai.net>
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions, and the following disclaimer,
- *    without modification, immediately at the beginning of the file.
+ *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
+ *	$FreeBSD$
  */
 
-/*
- * Credits:  Based on and part of the DPT driver for FreeBSD written and
- *           maintained by Simon Shapiro <shimon@simon-shapiro.org>
- */
-
-/*
- * $FreeBSD$
- */
-
-#include "opt_dpt.h"
-
 #include <sys/param.h>
 #include <sys/systm.h>
-#include <sys/malloc.h>
-#include <sys/buf.h>
-#include <sys/proc.h>
 #include <sys/kernel.h>
 #include <sys/module.h>
 #include <sys/bus.h>
@@ -52,42 +37,39 @@
 #include <machine/resource.h>
 #include <sys/rman.h>
 
-#include <cam/scsi/scsi_all.h>
-
-#include <dev/dpt/dpt.h>
-
 #include <dev/eisa/eisaconf.h>
 
-#include <machine/clock.h>
+#include <cam/scsi/scsi_all.h>
 
-#include <vm/vm.h>
-#include <vm/vm_param.h>
-#include <vm/pmap.h>
+#include <dev/dpt/dpt.h>
 
 #define DPT_EISA_IOSIZE			0x100
 #define DPT_EISA_SLOT_OFFSET		0x0c00
 #define DPT_EISA_EATA_REG_OFFSET	0x0088
 
-#define	DPT_EISA_DPT2402		0x12142402
-#define	DPT_EISA_DPTA401		0x1214A401
-#define	DPT_EISA_DPTA402		0x1214A402
-#define	DPT_EISA_DPTA410		0x1214A410
-#define	DPT_EISA_DPTA411		0x1214A411
-#define	DPT_EISA_DPTA412		0x1214A412
-#define	DPT_EISA_DPTA420		0x1214A420
-#define	DPT_EISA_DPTA501		0x1214A501
-#define	DPT_EISA_DPTA502		0x1214A502
-#define	DPT_EISA_DPTA701		0x1214A701
-#define	DPT_EISA_DPTBC01		0x1214BC01
-#define	DPT_EISA_NEC8200		0x12148200
-#define	DPT_EISA_ATT2408		0x12142408
+#define	DPT_EISA_DPT2402	0x12142402	/* DPT PM2012A/9X	*/
+#define	DPT_EISA_DPTA401	0x1214A401	/* DPT PM2012B/9X	*/
+#define	DPT_EISA_DPTA402	0x1214A402	/* DPT PM2012B2/9X	*/
+#define	DPT_EISA_DPTA410	0x1214A410	/* DPT PM2x22A/9X	*/
+#define	DPT_EISA_DPTA411	0x1214A411	/* DPT Spectre		*/
+#define	DPT_EISA_DPTA412	0x1214A412	/* DPT PM2021A/9X	*/
+#define	DPT_EISA_DPTA420	0x1214A420	/* DPT Smart Cache IV (PM2042) */
+#define	DPT_EISA_DPTA501	0x1214A501	/* DPT PM2012B1/9X"	*/
+#define	DPT_EISA_DPTA502	0x1214A502	/* DPT PM2012Bx/9X	*/
+#define	DPT_EISA_DPTA701	0x1214A701	/* DPT PM2011B1/9X	*/
+#define	DPT_EISA_DPTBC01	0x1214BC01	/* DPT PM3011/7X ESDI	*/ 
+#define	DPT_EISA_DPT8200	0x12148200	/* NEC EATA SCSI	*/
+#define	DPT_EISA_DPT2408	0x12142408	/* ATT EATA SCSI	*/
 
 /* Function Prototypes */
 
-static const char	*dpt_eisa_match(eisa_id_t);
+static const char *	dpt_eisa_match	(eisa_id_t);
+static int		dpt_eisa_probe	(device_t);
+static int		dpt_eisa_attach	(device_t);
+
 
 static int
-dpt_eisa_probe(device_t dev)
+dpt_eisa_probe (device_t dev)
 {
 	const char *	desc;
 	u_int32_t	io_base;
@@ -114,71 +96,86 @@ dpt_eisa_probe(device_t dev)
 }
 
 static int
-dpt_eisa_attach(device_t dev)
+dpt_eisa_attach (device_t dev)
 {
-	dpt_softc_t	*dpt;
+	dpt_softc_t * dpt;
 	struct resource *io = 0;
 	struct resource *irq = 0;
-        int		unit = device_get_unit(dev);
 	int		s;
 	int		rid;
-	void		*ih;
+	void *		ih;
+	int		error = 0;
 
 	rid = 0;
-	io = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
-				0, ~0, 1, RF_ACTIVE);
+	io = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 1, RF_ACTIVE);
 	if (!io) {
 		device_printf(dev, "No I/O space?!\n");
-		return ENOMEM;
+		error = ENOMEM;
+		goto bad;
 	}
 
-	dpt = dpt_alloc(unit, rman_get_bustag(io),
+	rid = 0;
+	irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, RF_ACTIVE);
+	if (!irq) {
+		device_printf(dev, "No irq?!\n");
+		error = ENOMEM;
+		goto bad;
+	}
+
+	dpt = dpt_alloc(dev, rman_get_bustag(io),
 			rman_get_bushandle(io) + DPT_EISA_EATA_REG_OFFSET);
-	if (dpt == NULL)
+	if (dpt == NULL) {
+		error = ENOMEM;
 		goto bad;
+	}
 
 	/* Allocate a dmatag representing the capabilities of this attachment */
 	/* XXX Should be a child of the EISA bus dma tag */
-	if (bus_dma_tag_create(/*parent*/NULL, /*alignemnt*/1, /*boundary*/0,
-			       /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
-			       /*highaddr*/BUS_SPACE_MAXADDR,
-			       /*filter*/NULL, /*filterarg*/NULL,
-			       /*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
-			       /*nsegments*/BUS_SPACE_UNRESTRICTED,
-			       /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
-			       /*flags*/0, &dpt->parent_dmat) != 0) {
+	if (bus_dma_tag_create(	/* parent    */	NULL,
+				/* alignemnt */	1,
+				/* boundary  */	0,
+				/* lowaddr   */	BUS_SPACE_MAXADDR_32BIT,
+				/* highaddr  */	BUS_SPACE_MAXADDR,
+				/* filter    */	NULL,
+				/* filterarg */	NULL,
+				/* maxsize   */	BUS_SPACE_MAXSIZE_32BIT,
+				/* nsegments */	BUS_SPACE_UNRESTRICTED,
+				/* maxsegsz  */	BUS_SPACE_MAXSIZE_32BIT,
+				/* flags     */0,
+				&dpt->parent_dmat) != 0) {
 		dpt_free(dpt);
-		goto bad;
-	}
-
-	rid = 0;
-	irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
-				 0, ~0, 1, RF_ACTIVE);
-	if (!irq) {
-		device_printf(dev, "No irq?!\n");
+		error = ENXIO;
 		goto bad;
 	}
 
 	s = splcam();
+
 	if (dpt_init(dpt) != 0) {
 		dpt_free(dpt);
+		error = ENXIO;
 		goto bad;
 	}
 
 	/* Register with the XPT */
 	dpt_attach(dpt);
-	bus_setup_intr(dev, irq, INTR_TYPE_CAM, dpt_intr, dpt, &ih);
 
 	splx(s);
 
-	return 0;
+	if (bus_setup_intr(dev, irq, INTR_TYPE_CAM, dpt_intr, dpt, &ih)) {
+		device_printf(dev, "Unable to register interrupt handler\n");
+		error = ENXIO;
+		goto bad;
+	}
+
+	return (error);
 
  bad:
 	if (io)
 		bus_release_resource(dev, SYS_RES_IOPORT, 0, io);
 	if (irq)
 		bus_release_resource(dev, SYS_RES_IRQ, 0, irq);
-	return -1;
+
+	return (error);
 }
 
 static const char	*
@@ -186,44 +183,20 @@ dpt_eisa_match(type)
 	eisa_id_t	type;
 {
 	switch (type) {
-		case DPT_EISA_DPT2402 :
-			return ("DPT PM2012A/9X");
-			break;
-		case DPT_EISA_DPTA401 :
-			return ("DPT PM2012B/9X");
-			break;
-		case DPT_EISA_DPTA402 :
-			return ("DPT PM2012B2/9X");
-			break;
-		case DPT_EISA_DPTA410 :
-			return ("DPT PM2x22A/9X");
-			break;
-		case DPT_EISA_DPTA411 :
-			return ("DPT Spectre");
-			break;
-		case DPT_EISA_DPTA412 :
-			return ("DPT PM2021A/9X");
-			break;
-		case DPT_EISA_DPTA420 :
-			return ("DPT Smart Cache IV (PM2042)");
-			break;
-		case DPT_EISA_DPTA501 :
-			return ("DPT PM2012B1/9X");
-			break;
-		case DPT_EISA_DPTA502 :
-			return ("DPT PM2012Bx/9X");
-			break;
-		case DPT_EISA_DPTA701 :
-			return ("DPT PM2011B1/9X");
-			break;
-		case DPT_EISA_DPTBC01 :
-			return ("DPT PM3011/7X ESDI");
-			break;
-		case DPT_EISA_NEC8200 :
-			return ("NEC EATA SCSI");
-			break;
-		case DPT_EISA_ATT2408 :
-			return ("ATT EATA SCSI");
+		case DPT_EISA_DPT2402:
+		case DPT_EISA_DPTA401:
+		case DPT_EISA_DPTA402:
+		case DPT_EISA_DPTA410:
+		case DPT_EISA_DPTA411:
+		case DPT_EISA_DPTA412:
+		case DPT_EISA_DPTA420:
+		case DPT_EISA_DPTA501:
+		case DPT_EISA_DPTA502:
+		case DPT_EISA_DPTA701:
+		case DPT_EISA_DPTBC01:
+		case DPT_EISA_DPT8200:
+		case DPT_EISA_DPT2408:
+			return ("DPT SCSI Host Bus Adapter");
 			break;
 		default:
 			break;
@@ -243,7 +216,7 @@ static device_method_t dpt_eisa_methods[] = {
 static driver_t dpt_eisa_driver = {
 	"dpt",
 	dpt_eisa_methods,
-	1,			/* unused */
+	sizeof(dpt_softc_t),
 };
 
 static devclass_t dpt_devclass;
diff --git a/sys/dev/dpt/dpt_isa.c b/sys/dev/dpt/dpt_isa.c
new file mode 100644
index 0000000..bb34534
--- /dev/null
+++ b/sys/dev/dpt/dpt_isa.c
@@ -0,0 +1,186 @@
+/*-
+ * Copyright (c) 2000 Matthew N. Dodd <winter@jurai.net>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	$FreeBSD$
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/bus.h>
+
+#include <machine/bus_pio.h>
+#include <machine/bus.h>
+#include <machine/resource.h>
+#include <sys/rman.h>
+
+#include <isa/isavar.h>
+
+#include <cam/scsi/scsi_all.h>
+
+#include <dev/dpt/dpt.h>
+
+static int	dpt_isa_probe		(device_t);
+static int	dpt_isa_attach		(device_t);
+
+static int
+dpt_isa_probe (device_t dev)
+{
+	dpt_conf_t *	conf;
+	u_int32_t	io_base;
+
+	/* No pnp support */
+	if (isa_get_vendorid(dev))
+		return (ENXIO);
+
+	if ((io_base = bus_get_resource_start(dev, SYS_RES_IOPORT, 0)) == 0)
+		return (ENXIO);
+
+	conf = dpt_pio_get_conf(io_base);
+        if (!conf) {
+                printf("dpt: dpt_pio_get_conf() failed.\n");
+                return (ENXIO);
+        }
+
+	device_set_desc(dev, "ISA DPT SCSI controller");
+	bus_set_resource(dev, SYS_RES_IRQ, 0, conf->IRQ, 1);
+	bus_set_resource(dev, SYS_RES_DRQ, 0, ((8 - conf->DMA_channel) & 7), 1);
+
+	return 0;
+}
+
+static int
+dpt_isa_attach (device_t dev)
+{
+	dpt_softc_t *	dpt = NULL;
+	struct resource *io = 0;
+	struct resource *irq = 0;
+	struct resource *drq = 0;
+	int		s;
+	int		rid;
+	void *		ih;
+	int		error = 0;
+
+	rid = 0;
+	io = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 1, RF_ACTIVE);
+	if (!io) {
+		device_printf(dev, "No I/O space?!\n");
+		error = ENOMEM;
+		goto bad;
+	}
+
+	rid = 0;
+	irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, RF_ACTIVE);
+	if (!irq) {
+		device_printf(dev, "No IRQ!\n");
+		error = ENOMEM;
+		goto bad;
+	}
+
+	rid = 0;
+	drq = bus_alloc_resource(dev, SYS_RES_DRQ, &rid, 0, ~0, 1, RF_ACTIVE);
+	if (!drq) {
+		device_printf(dev, "No DRQ?!\n");
+		error = ENOMEM;
+		goto bad;
+	}
+
+	dpt = dpt_alloc(dev, rman_get_bustag(io), rman_get_bushandle(io));
+	if (dpt == NULL) {
+		error = ENXIO;
+		goto bad;
+	}
+
+	isa_dmacascade(rman_get_start(drq));
+
+	/* Allocate a dmatag representing the capabilities of this attachment */
+	if (bus_dma_tag_create( /* parent    */	NULL,
+				/* alignemnt */	1,
+				/* boundary  */	0,
+				/* lowaddr   */	BUS_SPACE_MAXADDR_24BIT,
+				/* highaddr  */	BUS_SPACE_MAXADDR,
+				/* filter    */	NULL,
+				/* filterarg */	NULL,
+				/* maxsize   */	BUS_SPACE_MAXSIZE_32BIT,
+				/* nsegments */	BUS_SPACE_UNRESTRICTED,
+				/* maxsegsz  */	BUS_SPACE_MAXSIZE_32BIT,
+				/* flags     */	0,
+				&dpt->parent_dmat) != 0) {
+		error = ENXIO;
+		goto bad;
+	}
+
+	s = splcam();
+
+	if (dpt_init(dpt) != 0) {
+		splx(s);
+		error = ENXIO;
+		goto bad;
+	}
+
+	/* Register with the XPT */
+	dpt_attach(dpt);
+
+	splx(s);
+
+	if (bus_setup_intr(dev, irq, INTR_TYPE_CAM, dpt_intr, dpt, &ih)) {
+		device_printf(dev, "Unable to register interrupt handler\n");
+		error = ENXIO;
+		goto bad;
+	}
+
+	return (error);
+
+ bad:
+	if (dpt)
+		dpt_free(dpt);
+	if (io)
+		bus_release_resource(dev, SYS_RES_IOPORT, 0, io);
+	if (irq)
+		bus_release_resource(dev, SYS_RES_IRQ, 0, irq);
+	if (drq)
+		bus_release_resource(dev, SYS_RES_DRQ, 0, drq);
+
+	return (error);
+}
+
+static device_method_t dpt_isa_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		dpt_isa_probe),
+	DEVMETHOD(device_attach,	dpt_isa_attach),
+
+	{ 0, 0 }
+};
+
+static driver_t dpt_isa_driver = {
+	"dpt",
+	dpt_isa_methods,
+	sizeof(dpt_softc_t),
+};
+
+static devclass_t dpt_devclass;
+
+DRIVER_MODULE(dpt, isa, dpt_isa_driver, dpt_devclass, 0, 0);
diff --git a/sys/dev/dpt/dpt_pci.c b/sys/dev/dpt/dpt_pci.c
index 884b6b6..3bb3ee6 100644
--- a/sys/dev/dpt/dpt_pci.c
+++ b/sys/dev/dpt/dpt_pci.c
@@ -1,24 +1,24 @@
-/*
- *       Copyright (c) 1997 by Simon Shapiro
- *       All Rights Reserved
+/*-
+ * Copyright (c) 2000 Matthew N. Dodd <winter@jurai.net>
+ * All rights reserved.
+ *
+ * Copyright (c) 1997 Simon Shapiro
+ * All Rights Reserved
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions, and the following disclaimer,
- *    without modification, immediately at the beginning of the file.
+ *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
@@ -26,161 +26,175 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
+ *	$FreeBSD$
  */
 
-/*
- *  dptpci.c:  PCI Bus Attachment for DPT SCSI HBAs
- */
-
-#ident "$FreeBSD$"
-
-#include "opt_dpt.h"
-
 #include <sys/param.h>
 #include <sys/systm.h>
-#include <sys/malloc.h>
-#include <sys/buf.h>
 #include <sys/kernel.h>
-
-#include <pci/pcireg.h>
-#include <pci/pcivar.h>
+#include <sys/module.h>
+#include <sys/bus.h>
 
 #include <machine/bus_memio.h>
 #include <machine/bus_pio.h>
 #include <machine/bus.h>
+#include <machine/resource.h>
+#include <sys/rman.h>
+
+#include <pci/pcireg.h>
+#include <pci/pcivar.h>
 
 #include <cam/scsi/scsi_all.h>
 
 #include <dev/dpt/dpt.h>
-#include <dev/dpt/dpt_pci.h>
-
-#define PCI_BASEADR0  PCI_MAP_REG_START      /* I/O Address */
-#define PCI_BASEADR1  PCI_MAP_REG_START + 4  /* Mem I/O Address */
-
-#define ISA_PRIMARY_WD_ADDRESS    0x1f8
 
-/* Global variables */
+#define	DPT_VENDOR_ID		0x1044
+#define	DPT_DEVICE_ID		0xa400
 
-/* Function Prototypes */
+#define	DPT_PCI_IOADDR		PCIR_MAPS		/* I/O Address */
+#define	DPT_PCI_MEMADDR		(PCIR_MAPS + 4)		/* Mem I/O Address */
 
-static const char    *dpt_pci_probe(pcici_t tag, pcidi_t type);
-static void     dpt_pci_attach(pcici_t config_id, int unit);
+#define	ISA_PRIMARY_WD_ADDRESS	0x1f8
 
-extern struct cdevsw dpt_cdevsw;
+static int	dpt_pci_probe	(device_t);
+static int	dpt_pci_attach	(device_t);
 
-static  struct pci_device dpt_pci_driver =
+static int
+dpt_pci_probe (device_t dev)
 {
-	"dpt",
-	dpt_pci_probe,
-	dpt_pci_attach,
-	&dpt_unit,
-	NULL
-};
-
-COMPAT_PCI_DRIVER(dpt_pci, dpt_pci_driver);
-
-/*
- * Probe the PCI device.
- * Some of this work will have to be duplicated in _attach
- * because we do not know for sure how the two relate.
- */
+	if ((pci_get_vendor(dev) == DPT_VENDOR_ID) &&
+	    (pci_get_device(dev) == DPT_DEVICE_ID)) {
+		device_set_desc(dev, "DPT Caching SCSI RAID Controller");
+		return (0);
+	}
+	return (ENXIO);
+}
 
-static const char *
-dpt_pci_probe(pcici_t tag, pcidi_t type)
+static int
+dpt_pci_attach (device_t dev)
 {
-	u_int32_t  class;
-
-#ifndef PCI_COMMAND_MASTER_ENABLE
-#define PCI_COMMAND_MASTER_ENABLE 0x00000004
+	dpt_softc_t *	dpt;
+	struct resource *io = 0;
+	struct resource *irq = 0;
+	int		s;
+	int		rid;
+	void *		ih;
+	int		error = 0;
+
+	int		iotype = 0;
+	u_int32_t	command;
+
+	command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1);
+
+#ifdef DPT_ALLOW_MMIO
+	if ((command & PCIM_CMD_MEMEN) != 0) {
+		rid = DPT_PCI_MEMADDR;
+		iotype = SYS_RES_MEMORY;
+		io = bus_alloc_resource(dev, iotype, &rid, 0, ~0, 1, RF_ACTIVE);
+	}
 #endif
+	if (io == NULL && (command & PCI_COMMAND_IO_ENABLE) != 0) {
+		rid = DPT_PCI_IOADDR;
+		iotype = SYS_RES_IOPORT;
+		io = bus_alloc_resource(dev, iotype, &rid, 0, ~0, 1, RF_ACTIVE);
+	}
 
-#ifndef PCI_SUBCLASS_MASS_STORAGE_SCSI
-#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00000000
-#endif
+	if (io == NULL) {
+		device_printf(dev, "can't allocate register resources\n");
+		error = ENOMEM;
+		goto bad;
+	}
 
-	class = pci_conf_read(tag, PCI_CLASS_REG);
-	if (((type & 0xffff0000) >> 16) == DPT_DEVICE_ID
-	 && (class & PCI_CLASS_MASK) == PCI_CLASS_MASS_STORAGE
-	 && (class & PCI_SUBCLASS_MASK) == PCI_SUBCLASS_MASS_STORAGE_SCSI)
-		return ("DPT Caching SCSI RAID Controller");
-	return (NULL);
-}
+	rid = 0;
+	irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, RF_ACTIVE);
+	if (!irq) {
+		device_printf(dev, "No irq?!\n");
+		error = ENOMEM;
+		goto bad;
+	}
 
-static void
-dpt_pci_attach(pcici_t config_id, int unit)
-{
-	dpt_softc_t	   *dpt;
-	vm_offset_t	    vaddr;
-#ifdef DPT_ALLOW_MEMIO
-	vm_offset_t	    paddr;
-#endif
-	u_int16_t	    io_base;
-	bus_space_tag_t     tag;
-	bus_space_handle_t  bsh;
-	u_int32_t	    command;
-	int		    s;
-
-	vaddr = NULL;
-	command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
-#ifdef DPT_ALLOW_MEMIO
-	if ((command & PCI_COMMAND_MEM_ENABLE) == 0
-	 || (pci_map_mem(config_id, PCI_BASEADR1, &vaddr, &paddr)) == 0)
-#endif
-		if ((command & PCI_COMMAND_IO_ENABLE) == 0
-		 || (pci_map_port(config_id, PCI_BASEADR0, &io_base)) == 0)
-			return;
-
-	/*
-	 * If the DPT is mapped as an IDE controller,
-	 * let it be IDE controller
-	 */
-	if (io_base == ISA_PRIMARY_WD_ADDRESS - 0x10) {
+	/* Ensure busmastering is enabled */
+	command |= PCIM_CMD_BUSMASTEREN;
+	pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1);
+
+	if (rman_get_start(io) == (ISA_PRIMARY_WD_ADDRESS - 0x10)) {
 #ifdef DPT_DEBUG_WARN
-		printf("dpt%d: Mapped as an IDE controller.  "
-		       "Disabling SCSI setup\n", unit);
+		device_printf(dev, "Mapped as an IDE controller.  "
+				   "Disabling SCSI setup\n");
 #endif
-		return;
+		error = ENXIO;
+		goto bad;
 	}
 
-	/* XXX Should be passed in by parent bus */
-	/* XXX Why isn't the 0x10 offset incorporated into the reg defs? */
-	if (vaddr != 0) {
-		tag = I386_BUS_SPACE_MEM;
-		bsh = vaddr + 0x10;
-	} else {
-		tag = I386_BUS_SPACE_IO;
-		bsh = io_base + 0x10;
+	dpt = dpt_alloc(dev, rman_get_bustag(io), rman_get_bushandle(io));
+	if (dpt == NULL) {
+		error = ENXIO;
+		goto bad;
 	}
 
-	if ((dpt = dpt_alloc(unit, tag, bsh)) == NULL)
-		return;  /* XXX PCI code should take return status */
-	
 	/* Allocate a dmatag representing the capabilities of this attachment */
 	/* XXX Should be a child of the PCI bus dma tag */
-	if (bus_dma_tag_create(/*parent*/NULL, /*alignemnt*/1, /*boundary*/0,
-			       /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
-			       /*highaddr*/BUS_SPACE_MAXADDR,
-			       /*filter*/NULL, /*filterarg*/NULL,
-			       /*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
-			       /*nsegments*/BUS_SPACE_UNRESTRICTED,
-			       /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
-			       /*flags*/0, &dpt->parent_dmat) != 0) {
+	if (bus_dma_tag_create(	/* parent    */	NULL,
+				/* alignemnt */	1,
+				/* boundary  */	0,
+				/* lowaddr   */	BUS_SPACE_MAXADDR_32BIT,
+				/* highaddr  */	BUS_SPACE_MAXADDR,
+				/* filter    */	NULL,
+				/* filterarg */	NULL,
+				/* maxsize   */	BUS_SPACE_MAXSIZE_32BIT,
+				/* nsegments */	BUS_SPACE_UNRESTRICTED,
+				/* maxsegsz  */	BUS_SPACE_MAXSIZE_32BIT,
+				/* flags     */	0,
+				&dpt->parent_dmat) != 0) {
 		dpt_free(dpt);
-		return;
-	}
-
-	if (pci_map_int(config_id, dpt_intr, (void *)dpt, &cam_imask) == 0) {
-		dpt_free(dpt);
-		return;
+		error = ENXIO;
+		goto bad;
 	}
 
 	s = splcam();
+
 	if (dpt_init(dpt) != 0) {
 		dpt_free(dpt);
-		return;
+		error = ENXIO;
+		goto bad;
 	}
 
 	/* Register with the XPT */
 	dpt_attach(dpt);
+
 	splx(s);
+
+	if (bus_setup_intr(dev, irq, INTR_TYPE_CAM, dpt_intr, dpt, &ih)) {
+		device_printf(dev, "Unable to register interrupt handler\n");
+		error = ENXIO;
+		goto bad;
+	}
+
+	return (error);
+
+bad:
+	if (io)
+		bus_release_resource(dev, iotype, 0, io);
+	if (irq)
+		bus_release_resource(dev, SYS_RES_IRQ, 0, irq);
+
+	return (error);
 }
+
+static device_method_t dpt_pci_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,         dpt_pci_probe),
+	DEVMETHOD(device_attach,        dpt_pci_attach),
+
+	{ 0, 0 }
+};
+
+static driver_t dpt_pci_driver = {
+	"dpt",
+	dpt_pci_methods,
+	sizeof(dpt_softc_t),
+};
+
+static devclass_t dpt_devclass;
+
+DRIVER_MODULE(dpt, pci, dpt_pci_driver, dpt_devclass, 0, 0);
diff --git a/sys/dev/dpt/dpt_pci.h b/sys/dev/dpt/dpt_pci.h
deleted file mode 100644
index fe7206a..0000000
--- a/sys/dev/dpt/dpt_pci.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- *       Copyright (c) 1997 by Simon Shapiro
- *       All Rights Reserved
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions, and the following disclaimer,
- *    without modification, immediately at the beginning of the file.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- */
-
-#ident "$FreeBSD$"
-
-#define DPT_VENDOR_ID             0x00001044
-#define DPT_DEVICE_ID             0x0000a400
-
-/* The following are taken, shamelessly from Linux include/linux/pci.h */
-
-/*
- * Under PCI, each device has 256 bytes of configuration address space,
- * of which the first 64 bytes are standardized as follows:
- */
-#define PCI_VENDOR_ID		0x00	/* 16 bits */
-#define PCI_DEVICE_ID		0x02	/* 16 bits */
-#define PCI_COMMAND		0x04	/* 16 bits */
-#define  PCI_COMMAND_IO		0x1	/* Enable response in I/O space */
-#define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */
-#define  PCI_COMMAND_MASTER	0x4	/* Enable bus mastering */
-#define  PCI_COMMAND_SPECIAL	0x8	/* Enable response to special cycles */
-#define  PCI_COMMAND_INVALIDATE	0x10	/* Use memory write and invalidate */
-#define  PCI_COMMAND_VGA_PALETTE 0x20	/* Enable palette snooping */
-#define  PCI_COMMAND_PARITY	0x40	/* Enable parity checking */
-#define  PCI_COMMAND_WAIT 	0x80	/* Enable address/data stepping */
-#define  PCI_COMMAND_SERR	0x100	/* Enable SERR */
-#define  PCI_COMMAND_FAST_BACK	0x200	/* Enable back-to-back writes */
-
-#define PCI_STATUS		0x06	/* 16 bits */
-#define  PCI_STATUS_66MHZ	0x20	/* Support 66 Mhz PCI 2.1 bus */
-#define  PCI_STATUS_UDF		0x40	/* Support User Definable Features */
-
-#define  PCI_STATUS_FAST_BACK	0x80	/* Accept fast-back to back */
-#define  PCI_STATUS_PARITY	0x100	/* Detected parity error */
-#ifndef PCI_STATUS_DEVSEL_MASK
-#define  PCI_STATUS_DEVSEL_MASK	0x600	/* DEVSEL timing */
-#define  PCI_STATUS_DEVSEL_FAST	0x000
-#define  PCI_STATUS_DEVSEL_MEDIUM 0x200
-#define  PCI_STATUS_DEVSEL_SLOW 0x400
-#endif
-#define  PCI_STATUS_SIG_TARGET_ABORT 0x800	/* Set on target abort */
-#define  PCI_STATUS_REC_TARGET_ABORT 0x1000	/* Master ack of " */
-#define  PCI_STATUS_REC_MASTER_ABORT 0x2000	/* Set on master abort */
-#define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000	/* Set when we drive SERR */
-#define  PCI_STATUS_DETECTED_PARITY 0x8000	/* Set on parity error */
-
-#define PCI_CLASS_REVISION	0x08	/* High 24 bits are class, low 8
-					 * revision */
-#define PCI_REVISION_ID         0x08	/* Revision ID */
-#define PCI_CLASS_PROG          0x09	/* Reg. Level Programming Interface */
-#define PCI_CLASS_DEVICE        0x0a	/* Device class */
-
-#define PCI_CACHE_LINE_SIZE	0x0c	/* 8 bits */
-#define PCI_LATENCY_TIMER	0x0d	/* 8 bits */
-#define PCI_HEADER_TYPE		0x0e	/* 8 bits */
-#define PCI_BIST		0x0f	/* 8 bits */
-#define PCI_BIST_CODE_MASK	0x0f	/* Return result */
-#define PCI_BIST_START		0x40	/* 1 to start BIST, 2 secs or less */
-#define PCI_BIST_CAPABLE	0x80	/* 1 if BIST capable */
-
-/*
- * Base addresses specify locations in memory or I/O space.
- * Decoded size can be determined by writing a value of
- * 0xffffffff to the register, and reading it back.  Only
- * 1 bits are decoded.
- */
-#define PCI_BASE_ADDRESS_0	0x10	/* 32 bits */
-#define PCI_BASE_ADDRESS_1	0x14	/* 32 bits */
-#define PCI_BASE_ADDRESS_2	0x18	/* 32 bits */
-#define PCI_BASE_ADDRESS_3	0x1c	/* 32 bits */
-#define PCI_BASE_ADDRESS_4	0x20	/* 32 bits */
-#define PCI_BASE_ADDRESS_5	0x24	/* 32 bits */
-#define  PCI_BASE_ADDRESS_SPACE	0x01	/* 0 = memory, 1 = I/O */
-#define  PCI_BASE_ADDRESS_SPACE_IO 0x01
-#define  PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
-#define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
-#define  PCI_BASE_ADDRESS_MEM_TYPE_32	0x00	/* 32 bit address */
-#define  PCI_BASE_ADDRESS_MEM_TYPE_1M	0x02	/* Below 1M */
-#define  PCI_BASE_ADDRESS_MEM_TYPE_64	0x04	/* 64 bit address */
-#define  PCI_BASE_ADDRESS_MEM_PREFETCH	0x08	/* prefetchable? */
-#define  PCI_BASE_ADDRESS_MEM_MASK	(~0x0f)
-#define  PCI_BASE_ADDRESS_IO_MASK	(~0x03)
-/* bit 1 is reserved if address_space = 1 */
-
-#define PCI_CARDBUS_CIS		0x28
-#define PCI_SUBSYSTEM_ID	0x2c
-#define PCI_SUBSYSTEM_VENDOR_ID	0x2e
-#define PCI_ROM_ADDRESS		0x30	/* 32 bits */
-#define  PCI_ROM_ADDRESS_ENABLE	0x01	/* Write 1 to enable ROM, bits 31..11
-					 * are address, 10..2 are reserved */
-
-/* 0x34-0x3b are reserved */
-#define PCI_INTERRUPT_LINE	0x3c	/* 8 bits */
-#define PCI_INTERRUPT_PIN	0x3d	/* 8 bits */
-#define PCI_MIN_GNT		0x3e	/* 8 bits */
-#define PCI_MAX_LAT		0x3f	/* 8 bits */
-
-#define PCI_CLASS_NOT_DEFINED		0x0000
-#define PCI_CLASS_NOT_DEFINED_VGA	0x0001
-
-#define PCI_BASE_CLASS_STORAGE		0x01
-#define PCI_CLASS_STORAGE_SCSI		0x0100
-#define PCI_CLASS_STORAGE_IDE		0x0101
-#define PCI_CLASS_STORAGE_FLOPPY	0x0102
-#define PCI_CLASS_STORAGE_IPI		0x0103
-#define PCI_CLASS_STORAGE_RAID		0x0104
-#define PCI_CLASS_STORAGE_OTHER		0x0180
-
-#define PCI_BASE_CLASS_NETWORK		0x02
-#define PCI_CLASS_NETWORK_ETHERNET	0x0200
-#define PCI_CLASS_NETWORK_TOKEN_RING	0x0201
-#define PCI_CLASS_NETWORK_FDDI		0x0202
-#define PCI_CLASS_NETWORK_ATM		0x0203
-#define PCI_CLASS_NETWORK_OTHER		0x0280
-
-#define PCI_BASE_CLASS_DISPLAY		0x03
-#define PCI_CLASS_DISPLAY_VGA		0x0300
-#define PCI_CLASS_DISPLAY_XGA		0x0301
-#define PCI_CLASS_DISPLAY_OTHER		0x0380
-
-#define PCI_BASE_CLASS_MULTIMEDIA	0x04
-#define PCI_CLASS_MULTIMEDIA_VIDEO	0x0400
-#define PCI_CLASS_MULTIMEDIA_AUDIO	0x0401
-#define PCI_CLASS_MULTIMEDIA_OTHER	0x0480
-
-#define PCI_BASE_CLASS_MEMORY		0x05
-#define  PCI_CLASS_MEMORY_RAM		0x0500
-#define  PCI_CLASS_MEMORY_FLASH		0x0501
-#define  PCI_CLASS_MEMORY_OTHER		0x0580
-
-#define PCI_BASE_CLASS_BRIDGE		0x06
-#define  PCI_CLASS_BRIDGE_HOST		0x0600
-#define  PCI_CLASS_BRIDGE_ISA		0x0601
-#define  PCI_CLASS_BRIDGE_EISA		0x0602
-#define  PCI_CLASS_BRIDGE_MC		0x0603
-#define  PCI_CLASS_BRIDGE_PCI		0x0604
-#define  PCI_CLASS_BRIDGE_PCMCIA	0x0605
-#define  PCI_CLASS_BRIDGE_NUBUS		0x0606
-#define  PCI_CLASS_BRIDGE_CARDBUS	0x0607
-#define  PCI_CLASS_BRIDGE_OTHER		0x0680
-
-
-#define PCI_BASE_CLASS_COMMUNICATION	0x07
-#define PCI_CLASS_COMMUNICATION_SERIAL	0x0700
-#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
-#define PCI_CLASS_COMMUNICATION_OTHER	0x0780
-
-#define PCI_BASE_CLASS_SYSTEM		0x08
-#define PCI_CLASS_SYSTEM_PIC		0x0800
-#define PCI_CLASS_SYSTEM_DMA		0x0801
-#define PCI_CLASS_SYSTEM_TIMER		0x0802
-#define PCI_CLASS_SYSTEM_RTC		0x0803
-#define PCI_CLASS_SYSTEM_OTHER		0x0880
-
-#define PCI_BASE_CLASS_INPUT		0x09
-#define PCI_CLASS_INPUT_KEYBOARD	0x0900
-#define PCI_CLASS_INPUT_PEN		0x0901
-#define PCI_CLASS_INPUT_MOUSE		0x0902
-#define PCI_CLASS_INPUT_OTHER		0x0980
-
-#define PCI_BASE_CLASS_DOCKING		0x0a
-#define PCI_CLASS_DOCKING_GENERIC	0x0a00
-#define PCI_CLASS_DOCKING_OTHER		0x0a01
-
-#define PCI_BASE_CLASS_PROCESSOR	0x0b
-#define PCI_CLASS_PROCESSOR_386		0x0b00
-#define PCI_CLASS_PROCESSOR_486		0x0b01
-#define PCI_CLASS_PROCESSOR_PENTIUM	0x0b02
-#define PCI_CLASS_PROCESSOR_ALPHA	0x0b10
-#define PCI_CLASS_PROCESSOR_POWERPC	0x0b20
-#define PCI_CLASS_PROCESSOR_CO		0x0b40
-
-#define PCI_BASE_CLASS_SERIAL		0x0c
-#define PCI_CLASS_SERIAL_FIREWIRE	0x0c00
-#define PCI_CLASS_SERIAL_ACCESS		0x0c01
-#define PCI_CLASS_SERIAL_SSA		0x0c02
-#define PCI_CLASS_SERIAL_USB		0x0c03
-#define PCI_CLASS_SERIAL_FIBER		0x0c04
-
-#define PCI_CLASS_OTHERS		0xff
diff --git a/sys/dev/dpt/dpt_scsi.c b/sys/dev/dpt/dpt_scsi.c
index 86449f0..090f008 100644
--- a/sys/dev/dpt/dpt_scsi.c
+++ b/sys/dev/dpt/dpt_scsi.c
@@ -57,9 +57,12 @@
 
 #include <stddef.h>	/* For offsetof */
 
+#include <sys/bus.h>
+
 #include <machine/bus_memio.h>
 #include <machine/bus_pio.h>
 #include <machine/bus.h>
+
 #include <machine/clock.h>
 
 #include <cam/cam.h>
@@ -423,6 +426,8 @@ dpt_pio_get_conf (u_int32_t base)
 
 	/*
 	 * Wait for the controller to become ready.
+	 * For some reason there can be -no- delays after calling reset
+	 * before we wait on ready status.
 	 */
 	if (dpt_pio_wait(base, HA_RSTATUS, HA_SBUSY, 0)) {
 		printf("dpt: timeout waiting for controller to become ready\n");
@@ -450,7 +455,7 @@ dpt_pio_get_conf (u_int32_t base)
 			return (NULL);
 		}
 
-		*p = inw(base + HA_RDATA);
+		(*p) = inw(base + HA_RDATA);
 		p++;
 	}
 
@@ -576,6 +581,10 @@ dpt_get_conf(dpt_softc_t *dpt, dpt_ccb_t *dccb, u_int32_t dccb_busaddr,
 	 && (dpt->sp->scsi_stat == 0)
 	 && (dpt->sp->residue_len == 0))
 		return (0);
+
+	if (dpt->sp->scsi_stat == SCSI_STATUS_CHECK_COND)
+		return (0);
+
 	return (1);
 }
 
@@ -1173,22 +1182,16 @@ dpt_send_eata_command(dpt_softc_t *dpt, eata_ccb_t *cmd_block,
 
 
 /* ==================== Exported Function definitions =======================*/
-struct dpt_softc *
-dpt_alloc(u_int unit, bus_space_tag_t tag, bus_space_handle_t bsh)
+dpt_softc_t *
+dpt_alloc(device_t dev, bus_space_tag_t tag, bus_space_handle_t bsh)
 {
-	struct dpt_softc *dpt;
+	dpt_softc_t	*dpt = device_get_softc(dev);
 	int    i;
 
-	dpt = (struct dpt_softc *)malloc(sizeof(*dpt), M_DEVBUF, M_NOWAIT);
-	if (dpt == NULL) {
-		printf("dpt%d: Unable to allocate softc\n", dpt->unit);
-		return (NULL);
-	}
-
 	bzero(dpt, sizeof(dpt_softc_t));
 	dpt->tag = tag;
 	dpt->bsh = bsh;
-	dpt->unit = unit;
+	dpt->unit = device_get_unit(dev);
 	SLIST_INIT(&dpt->free_dccb_list);
 	LIST_INIT(&dpt->pending_ccb_list);
 	TAILQ_INSERT_TAIL(&dpt_softcs, dpt, links);
@@ -1234,7 +1237,6 @@ dpt_free(struct dpt_softc *dpt)
 		break;
 	}
 	TAILQ_REMOVE(&dpt_softcs, dpt, links);
-	free(dpt, M_DEVBUF);
 }
 
 static u_int8_t string_sizes[] =
@@ -1396,6 +1398,7 @@ dpt_init(struct dpt_softc *dpt)
 			       /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
 			       /*flags*/BUS_DMA_ALLOCNOW,
 			       &dpt->buffer_dmat) != 0) {
+		printf("dpt: bus_dma_tag_create(...,dpt->buffer_dmat) failed\n");
 		goto error_exit;
 	}
 
@@ -1411,6 +1414,7 @@ dpt_init(struct dpt_softc *dpt)
 			       /*nsegments*/1,
 			       /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
 			       /*flags*/0, &dpt->dccb_dmat) != 0) {
+		printf("dpt: bus_dma_tag_create(...,dpt->dccb_dmat) failed\n");
 		goto error_exit;
         }
 
@@ -1419,6 +1423,7 @@ dpt_init(struct dpt_softc *dpt)
 	/* Allocation for our ccbs and interrupt status packet */
 	if (bus_dmamem_alloc(dpt->dccb_dmat, (void **)&dpt->dpt_dccbs,
 			     BUS_DMA_NOWAIT, &dpt->dccb_dmamap) != 0) {
+		printf("dpt: bus_dmamem_alloc(dpt->dccb_dmat,...) failed\n");
 		goto error_exit;
 	}
 
@@ -1443,8 +1448,10 @@ dpt_init(struct dpt_softc *dpt)
 	dpt->init_level++;
 
 	/* Allocate our first batch of ccbs */
-	if (dptallocccbs(dpt) == 0)
+	if (dptallocccbs(dpt) == 0) {
+		printf("dpt: dptallocccbs(dpt) == 0\n");
 		return (2);
+	}
 
 	/* Prepare for Target Mode */
 	dpt->target_mode_enabled = 1;