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| author | marius <marius@FreeBSD.org> | 2008-12-07 23:02:37 +0000 |
|---|---|---|
| committer | marius <marius@FreeBSD.org> | 2008-12-07 23:02:37 +0000 |
| commit | b5f6ffdd905393594ab1d9cc61a3ac47b95c2571 (patch) | |
| tree | 5e8839c045e4e51e8717550cec6cb78699ace04c /sys/dev/dc/if_dcreg.h | |
| parent | 7bc367aaa495fcbd51501cdb4011912439354c8b (diff) | |
| download | FreeBSD-src-b5f6ffdd905393594ab1d9cc61a3ac47b95c2571.zip FreeBSD-src-b5f6ffdd905393594ab1d9cc61a3ac47b95c2571.tar.gz | |
- According to the corresponding Linux, NetBSD and OpenSolaris
drivers, there should be a 1us delay after every write when
bit-banging the MII. Also insert barriers in order to ensure
the intended ordering. These changes hopefully will solve the
bus wedging occasionally experienced with DM9102A since r182461.
- Deobfuscate dc_mii_readreg() a bit.
Diffstat (limited to 'sys/dev/dc/if_dcreg.h')
| -rw-r--r-- | sys/dev/dc/if_dcreg.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/sys/dev/dc/if_dcreg.h b/sys/dev/dc/if_dcreg.h index eb798dc..cce2c10 100644 --- a/sys/dev/dc/if_dcreg.h +++ b/sys/dev/dc/if_dcreg.h @@ -791,6 +791,9 @@ struct dc_softc { #define CSR_READ_4(sc, reg) \ bus_space_read_4(sc->dc_btag, sc->dc_bhandle, reg) +#define CSR_BARRIER_4(sc, reg, flags) \ + bus_space_barrier(sc->dc_btag, sc->dc_bhandle, reg, 4, flags) + #define DC_TIMEOUT 1000 #define ETHER_ALIGN 2 |
