MFC 305695,305696,305699,305702,305703,305713,305715,305827,305852,305906,

305908,306062,306063,306137,306138,306206,306216,306273,306295,306301,
306465,309302:
Add support for adapters using the Terminator T6 ASIC.

305695:
cxgbe(4): Set up fl_starve_threshold2 accurately for T6.

305696:
cxgbe(4): Use correct macro for header length with T6 ASICs.  This
affects the transmit of the VF driver only.

305699:
cxgbe(4): Update the pad_boundary calculation for T6, which has a
different range of boundaries.

305702:
cxgbe(4): Use smaller min/max bursts for fl descriptors with a T6.

305703:
cxgbe(4): Deal with the slightly different SGE_STAT_CFG in T6.

305713:
cxgbe(4): Add support for additional port types and link speeds.

305715:
cxgbe(4): Catch up with the rename of tlscaps -> cryptocaps.  TLS is one
of the capabilities of the crypto engine in T6.

305827:
cxgbe(4): Use the interface's viid to calculate the PF/VF/VFValid fields
to use in tx work requests.

305852:
cxgbe(4): Attach to cards with the Terminator 6 ASIC.  T6 cards will
come up as 't6nex' nexus devices with 'cc' ports hanging off them.

The T6 firmware and configuration files will be added as soon as they
are released.  For now the driver will try to work with whatever
firmware and configuration is on the card's flash.

305906:
cxgbe/t4_tom: The SMAC entry for a VI is at a different location in the T6.

305908:
cxgbe/t4_tom: Update the active/passive open code to support T6.  Data
path works as-is.

306062:
cxgbe(4): Show wcwr_stats for T6 cards.

306063:
cxgbe(4): Setup congestion response for T6 rx queues.

306137:
cxgbetool: Add T6 support to the SGE context decoder.

306138:
Fix typo.

306206:
cxgbe(4): Catch up with the different layout of WHOAMI in T6.

Note that the code moved below t4_prep_adapter() as part of this change
because now it needs a working chip_id().

306216:
cxgbe(4): Fix the output of the "tids" sysctl on T6.

306273:
cxgbe(4): Fix netmap with T6, which doesn't encapsulate SGE_EGR_UPDATE
message inside a FW_MSG.  The base NIC already deals with updates in
either form.

306295:
cxgbe(4): Support SIOGIFXMEDIA so that ifconfig displays correct media
for 25Gbps and 100Gbps ports.   This should have been part of r305713,
which is when the driver first started reporting extended media types.

306301:
cxgbe(4): Use the port's top speed to figure out whether it is "high
speed" or not (for the purpose of calculating the number of queues etc.)
This does the right thing for 25Gbps and 100Gbps ports.

306465:
cxgbe(4): Claim the T6 -DBG card.

309302:
cxgbe(4): Include firmware for T6 cards in the driver.  Update all
firmwares to 1.16.12.0.

Sponsored by:	Chelsio Communications

1 files changed, 672 insertions, 126 deletions

diff --git a/sys/dev/cxgbe/firmware/t4fw_interface.h b/sys/dev/cxgbe/firmware/t4fw_interface.h
index fad7851..9f2bf0c 100644
--- a/sys/dev/cxgbe/firmware/t4fw_interface.h
+++ b/sys/dev/cxgbe/firmware/t4fw_interface.h
@@ -114,6 +114,7 @@ enum fw_wr_opcodes {
 	FW_RI_RECV_WR		= 0x17,
 	FW_RI_BIND_MW_WR	= 0x18,
 	FW_RI_FR_NSMR_WR	= 0x19,
+	FW_RI_FR_NSMR_TPTE_WR	= 0x20,
 	FW_RI_INV_LSTAG_WR	= 0x1a,
 	FW_RI_SEND_IMMEDIATE_WR	= 0x15,
 	FW_RI_ATOMIC_WR		= 0x16,
@@ -135,7 +136,9 @@ enum fw_wr_opcodes {
 	FW_POFCOE_ULPTX_WR	= 0x43,
 	FW_ISCSI_TX_DATA_WR	= 0x45,
 	FW_PTP_TX_PKT_WR        = 0x46,
-	FW_SEC_LOOKASIDE_LPBK_WR= 0x6d,
+	FW_TLSTX_DATA_WR	= 0x68,
+	FW_TLS_KEYCTX_TX_WR	= 0x69,
+	FW_CRYPTO_LOOKASIDE_WR	= 0x6d,
 	FW_COiSCSI_TGT_WR	= 0x70,
 	FW_COiSCSI_TGT_CONN_WR	= 0x71,
 	FW_COiSCSI_TGT_XMIT_WR	= 0x72,
@@ -913,7 +916,8 @@ enum fw_flowc_mnem {
 	FW_FLOWC_MNEM_DCBPRIO		= 12,
 	FW_FLOWC_MNEM_SND_SCALE		= 13,
 	FW_FLOWC_MNEM_RCV_SCALE		= 14,
-	FW_FLOWC_MNEM_MAX		= 15,
+	FW_FLOWC_MNEM_ULP_MODE		= 15,
+	FW_FLOWC_MNEM_MAX		= 16,
 };
 
 struct fw_flowc_mnemval {
@@ -1336,7 +1340,7 @@ struct fw_ri_cqe {
 		struct fw_ri_scqe {
 		__be32	qpid_n_stat_rxtx_type;
 		__be32	plen;
-		__be32	reserved;
+		__be32	stag;
 		__be32	wrid;
 		} scqe;
 		struct fw_ri_rcqe {
@@ -1804,6 +1808,18 @@ struct fw_ri_fr_nsmr_wr {
 #define G_FW_RI_FR_NSMR_WR_DCACPU(x)	\
     (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU)
 
+struct fw_ri_fr_nsmr_tpte_wr {
+	__u8   opcode;
+	__u8   flags;
+	__u16  wrid;
+	__u8   r1[3];
+	__u8   len16;
+	__be32 r2;
+	__be32 stag;
+	struct fw_ri_tpte tpte;
+	__be64 pbl[2];
+};
+
 struct fw_ri_inv_lstag_wr {
 	__u8   opcode;
 	__u8   flags;
@@ -3384,8 +3400,456 @@ struct fw_pi_error {
 #define G_FW_PI_ERROR_ERR_TYPE(x)	\
     (((x) >> S_FW_PI_ERROR_ERR_TYPE) & M_FW_PI_ERROR_ERR_TYPE)
 
-
-struct fw_sec_lookaside_lpbk_wr {
+struct fw_tlstx_data_wr {
+        __be32 op_to_immdlen;
+        __be32 flowid_len16;
+        __be32 plen;
+        __be32 lsodisable_to_flags;
+        __be32 ddraddr;
+        __be32 ctxloc_to_exp;
+        __be16 mfs;
+        __be16 adjustedplen_pkd;
+        __be16 expinplenmax_pkd;
+        __u8   pdusinplenmax_pkd;
+        __u8   r9;
+};
+
+#define S_FW_TLSTX_DATA_WR_COMPL        21
+#define M_FW_TLSTX_DATA_WR_COMPL        0x1
+#define V_FW_TLSTX_DATA_WR_COMPL(x)     ((x) << S_FW_TLSTX_DATA_WR_COMPL)
+#define G_FW_TLSTX_DATA_WR_COMPL(x)     \
+    (((x) >> S_FW_TLSTX_DATA_WR_COMPL) & M_FW_TLSTX_DATA_WR_COMPL)
+#define F_FW_TLSTX_DATA_WR_COMPL        V_FW_TLSTX_DATA_WR_COMPL(1U)
+
+#define S_FW_TLSTX_DATA_WR_IMMDLEN      0
+#define M_FW_TLSTX_DATA_WR_IMMDLEN      0xff
+#define V_FW_TLSTX_DATA_WR_IMMDLEN(x)   ((x) << S_FW_TLSTX_DATA_WR_IMMDLEN)
+#define G_FW_TLSTX_DATA_WR_IMMDLEN(x)   \
+    (((x) >> S_FW_TLSTX_DATA_WR_IMMDLEN) & M_FW_TLSTX_DATA_WR_IMMDLEN)
+
+#define S_FW_TLSTX_DATA_WR_FLOWID       8
+#define M_FW_TLSTX_DATA_WR_FLOWID       0xfffff
+#define V_FW_TLSTX_DATA_WR_FLOWID(x)    ((x) << S_FW_TLSTX_DATA_WR_FLOWID)
+#define G_FW_TLSTX_DATA_WR_FLOWID(x)    \
+    (((x) >> S_FW_TLSTX_DATA_WR_FLOWID) & M_FW_TLSTX_DATA_WR_FLOWID)
+
+#define S_FW_TLSTX_DATA_WR_LEN16        0
+#define M_FW_TLSTX_DATA_WR_LEN16        0xff
+#define V_FW_TLSTX_DATA_WR_LEN16(x)     ((x) << S_FW_TLSTX_DATA_WR_LEN16)
+#define G_FW_TLSTX_DATA_WR_LEN16(x)     \
+    (((x) >> S_FW_TLSTX_DATA_WR_LEN16) & M_FW_TLSTX_DATA_WR_LEN16)
+
+#define S_FW_TLSTX_DATA_WR_LSODISABLE   31
+#define M_FW_TLSTX_DATA_WR_LSODISABLE   0x1
+#define V_FW_TLSTX_DATA_WR_LSODISABLE(x) \
+    ((x) << S_FW_TLSTX_DATA_WR_LSODISABLE)
+#define G_FW_TLSTX_DATA_WR_LSODISABLE(x) \
+    (((x) >> S_FW_TLSTX_DATA_WR_LSODISABLE) & M_FW_TLSTX_DATA_WR_LSODISABLE)
+#define F_FW_TLSTX_DATA_WR_LSODISABLE   V_FW_TLSTX_DATA_WR_LSODISABLE(1U)
+
+#define S_FW_TLSTX_DATA_WR_ALIGNPLD     30
+#define M_FW_TLSTX_DATA_WR_ALIGNPLD     0x1
+#define V_FW_TLSTX_DATA_WR_ALIGNPLD(x)  ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLD)
+#define G_FW_TLSTX_DATA_WR_ALIGNPLD(x)  \
+    (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLD) & M_FW_TLSTX_DATA_WR_ALIGNPLD)
+#define F_FW_TLSTX_DATA_WR_ALIGNPLD     V_FW_TLSTX_DATA_WR_ALIGNPLD(1U)
+
+#define S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 29
+#define M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 0x1
+#define V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \
+    ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE)
+#define G_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \
+    (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) & \
+     M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE)
+#define F_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(1U)
+
+#define S_FW_TLSTX_DATA_WR_FLAGS        0
+#define M_FW_TLSTX_DATA_WR_FLAGS        0xfffffff
+#define V_FW_TLSTX_DATA_WR_FLAGS(x)     ((x) << S_FW_TLSTX_DATA_WR_FLAGS)
+#define G_FW_TLSTX_DATA_WR_FLAGS(x)     \
+    (((x) >> S_FW_TLSTX_DATA_WR_FLAGS) & M_FW_TLSTX_DATA_WR_FLAGS)
+
+#define S_FW_TLSTX_DATA_WR_CTXLOC       30
+#define M_FW_TLSTX_DATA_WR_CTXLOC       0x3
+#define V_FW_TLSTX_DATA_WR_CTXLOC(x)    ((x) << S_FW_TLSTX_DATA_WR_CTXLOC)
+#define G_FW_TLSTX_DATA_WR_CTXLOC(x)    \
+    (((x) >> S_FW_TLSTX_DATA_WR_CTXLOC) & M_FW_TLSTX_DATA_WR_CTXLOC)
+
+#define S_FW_TLSTX_DATA_WR_IVDSGL       29
+#define M_FW_TLSTX_DATA_WR_IVDSGL       0x1
+#define V_FW_TLSTX_DATA_WR_IVDSGL(x)    ((x) << S_FW_TLSTX_DATA_WR_IVDSGL)
+#define G_FW_TLSTX_DATA_WR_IVDSGL(x)    \
+    (((x) >> S_FW_TLSTX_DATA_WR_IVDSGL) & M_FW_TLSTX_DATA_WR_IVDSGL)
+#define F_FW_TLSTX_DATA_WR_IVDSGL       V_FW_TLSTX_DATA_WR_IVDSGL(1U)
+
+#define S_FW_TLSTX_DATA_WR_KEYSIZE      24
+#define M_FW_TLSTX_DATA_WR_KEYSIZE      0x1f
+#define V_FW_TLSTX_DATA_WR_KEYSIZE(x)   ((x) << S_FW_TLSTX_DATA_WR_KEYSIZE)
+#define G_FW_TLSTX_DATA_WR_KEYSIZE(x)   \
+    (((x) >> S_FW_TLSTX_DATA_WR_KEYSIZE) & M_FW_TLSTX_DATA_WR_KEYSIZE)
+
+#define S_FW_TLSTX_DATA_WR_NUMIVS       14
+#define M_FW_TLSTX_DATA_WR_NUMIVS       0xff
+#define V_FW_TLSTX_DATA_WR_NUMIVS(x)    ((x) << S_FW_TLSTX_DATA_WR_NUMIVS)
+#define G_FW_TLSTX_DATA_WR_NUMIVS(x)    \
+    (((x) >> S_FW_TLSTX_DATA_WR_NUMIVS) & M_FW_TLSTX_DATA_WR_NUMIVS)
+
+#define S_FW_TLSTX_DATA_WR_EXP          0
+#define M_FW_TLSTX_DATA_WR_EXP          0x3fff
+#define V_FW_TLSTX_DATA_WR_EXP(x)       ((x) << S_FW_TLSTX_DATA_WR_EXP)
+#define G_FW_TLSTX_DATA_WR_EXP(x)       \
+    (((x) >> S_FW_TLSTX_DATA_WR_EXP) & M_FW_TLSTX_DATA_WR_EXP)
+
+#define S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 1
+#define M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 0x7fff
+#define V_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \
+            ((x) << S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN)
+#define G_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \
+            (((x) >> S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) & \
+                  M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN)
+
+#define S_FW_TLSTX_DATA_WR_EXPINPLENMAX 4
+#define M_FW_TLSTX_DATA_WR_EXPINPLENMAX 0xfff
+#define V_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \
+            ((x) << S_FW_TLSTX_DATA_WR_EXPINPLENMAX)
+#define G_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \
+            (((x) >> S_FW_TLSTX_DATA_WR_EXPINPLENMAX) & \
+                  M_FW_TLSTX_DATA_WR_EXPINPLENMAX)
+
+#define S_FW_TLSTX_DATA_WR_PDUSINPLENMAX 2
+#define M_FW_TLSTX_DATA_WR_PDUSINPLENMAX 0x3f
+#define V_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \
+            ((x) << S_FW_TLSTX_DATA_WR_PDUSINPLENMAX)
+#define G_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \
+            (((x) >> S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) & \
+                  M_FW_TLSTX_DATA_WR_PDUSINPLENMAX)
+
+struct fw_tls_keyctx_tx_wr {
+        __be32 op_to_compl;
+        __be32 flowid_len16;
+        union fw_key_ctx {
+                struct fw_tx_keyctx_hdr {
+                        __u8   ctxlen;
+                        __u8   r2;
+                        __be16 dualck_to_txvalid;
+                        __u8   txsalt[4];
+                        __be64 r5;
+                } txhdr;
+                struct fw_rx_keyctx_hdr {
+                        __u8   flitcnt_hmacctrl;
+                        __u8   protover_ciphmode;
+                        __u8   authmode_to_rxvalid;
+                        __u8   ivpresent_to_rxmk_size;
+                        __u8   rxsalt[4];
+                        __be64 ivinsert_to_authinsrt;
+                } rxhdr;
+                struct fw_keyctx_clear {
+                        __be32 tx_key;
+                        __be32 rx_key;
+                } kctx_clr;
+        } u;
+        struct keys {
+                __u8   edkey[32];
+                __u8   ipad[64];
+                __u8   opad[64];
+        } keys;
+        __u8   reneg_to_write_rx;
+        __u8   protocol;
+        __u8   r7[2];
+        __be32 ftid;
+};
+
+#define S_FW_TLS_KEYCTX_TX_WR_OPCODE    24
+#define M_FW_TLS_KEYCTX_TX_WR_OPCODE    0xff
+#define V_FW_TLS_KEYCTX_TX_WR_OPCODE(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_OPCODE)
+#define G_FW_TLS_KEYCTX_TX_WR_OPCODE(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_OPCODE) & M_FW_TLS_KEYCTX_TX_WR_OPCODE)
+
+#define S_FW_TLS_KEYCTX_TX_WR_ATOMIC    23
+#define M_FW_TLS_KEYCTX_TX_WR_ATOMIC    0x1
+#define V_FW_TLS_KEYCTX_TX_WR_ATOMIC(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_ATOMIC)
+#define G_FW_TLS_KEYCTX_TX_WR_ATOMIC(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_ATOMIC) & M_FW_TLS_KEYCTX_TX_WR_ATOMIC)
+#define F_FW_TLS_KEYCTX_TX_WR_ATOMIC    V_FW_TLS_KEYCTX_TX_WR_ATOMIC(1U)
+
+#define S_FW_TLS_KEYCTX_TX_WR_FLUSH     22
+#define M_FW_TLS_KEYCTX_TX_WR_FLUSH     0x1
+#define V_FW_TLS_KEYCTX_TX_WR_FLUSH(x)  ((x) << S_FW_TLS_KEYCTX_TX_WR_FLUSH)
+#define G_FW_TLS_KEYCTX_TX_WR_FLUSH(x)  \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_FLUSH) & M_FW_TLS_KEYCTX_TX_WR_FLUSH)
+#define F_FW_TLS_KEYCTX_TX_WR_FLUSH     V_FW_TLS_KEYCTX_TX_WR_FLUSH(1U)
+
+#define S_FW_TLS_KEYCTX_TX_WR_COMPL     21
+#define M_FW_TLS_KEYCTX_TX_WR_COMPL     0x1
+#define V_FW_TLS_KEYCTX_TX_WR_COMPL(x)  ((x) << S_FW_TLS_KEYCTX_TX_WR_COMPL)
+#define G_FW_TLS_KEYCTX_TX_WR_COMPL(x)  \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_COMPL) & M_FW_TLS_KEYCTX_TX_WR_COMPL)
+#define F_FW_TLS_KEYCTX_TX_WR_COMPL     V_FW_TLS_KEYCTX_TX_WR_COMPL(1U)
+
+#define S_FW_TLS_KEYCTX_TX_WR_FLOWID    8
+#define M_FW_TLS_KEYCTX_TX_WR_FLOWID    0xfffff
+#define V_FW_TLS_KEYCTX_TX_WR_FLOWID(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_FLOWID)
+#define G_FW_TLS_KEYCTX_TX_WR_FLOWID(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_FLOWID) & M_FW_TLS_KEYCTX_TX_WR_FLOWID)
+
+#define S_FW_TLS_KEYCTX_TX_WR_LEN16     0
+#define M_FW_TLS_KEYCTX_TX_WR_LEN16     0xff
+#define V_FW_TLS_KEYCTX_TX_WR_LEN16(x)  ((x) << S_FW_TLS_KEYCTX_TX_WR_LEN16)
+#define G_FW_TLS_KEYCTX_TX_WR_LEN16(x)  \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_LEN16) & M_FW_TLS_KEYCTX_TX_WR_LEN16)
+
+#define S_FW_TLS_KEYCTX_TX_WR_DUALCK    12
+#define M_FW_TLS_KEYCTX_TX_WR_DUALCK    0x1
+#define V_FW_TLS_KEYCTX_TX_WR_DUALCK(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_DUALCK)
+#define G_FW_TLS_KEYCTX_TX_WR_DUALCK(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_DUALCK) & M_FW_TLS_KEYCTX_TX_WR_DUALCK)
+#define F_FW_TLS_KEYCTX_TX_WR_DUALCK    V_FW_TLS_KEYCTX_TX_WR_DUALCK(1U)
+
+#define S_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT 11
+#define M_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT 0x1
+#define V_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT(x) \
+    ((x) << S_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT)
+#define G_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT) & \
+     M_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT)
+#define F_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT \
+    V_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT(1U)
+
+#define S_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT 10
+#define M_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT 0x1
+#define V_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT(x) \
+    ((x) << S_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT)
+#define G_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT) & \
+     M_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT)
+#define F_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT \
+    V_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT(1U)
+
+#define S_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE 6
+#define M_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE 0xf
+#define V_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE(x) \
+    ((x) << S_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE)
+#define G_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE) & \
+     M_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE)
+
+#define S_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE 2
+#define M_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE 0xf
+#define V_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE(x) \
+    ((x) << S_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE)
+#define G_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE) & \
+     M_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE)
+
+#define S_FW_TLS_KEYCTX_TX_WR_TXVALID   0
+#define M_FW_TLS_KEYCTX_TX_WR_TXVALID   0x1
+#define V_FW_TLS_KEYCTX_TX_WR_TXVALID(x) \
+    ((x) << S_FW_TLS_KEYCTX_TX_WR_TXVALID)
+#define G_FW_TLS_KEYCTX_TX_WR_TXVALID(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXVALID) & M_FW_TLS_KEYCTX_TX_WR_TXVALID)
+#define F_FW_TLS_KEYCTX_TX_WR_TXVALID   V_FW_TLS_KEYCTX_TX_WR_TXVALID(1U)
+
+#define S_FW_TLS_KEYCTX_TX_WR_FLITCNT   3
+#define M_FW_TLS_KEYCTX_TX_WR_FLITCNT   0x1f
+#define V_FW_TLS_KEYCTX_TX_WR_FLITCNT(x) \
+    ((x) << S_FW_TLS_KEYCTX_TX_WR_FLITCNT)
+#define G_FW_TLS_KEYCTX_TX_WR_FLITCNT(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_FLITCNT) & M_FW_TLS_KEYCTX_TX_WR_FLITCNT)
+
+#define S_FW_TLS_KEYCTX_TX_WR_HMACCTRL  0
+#define M_FW_TLS_KEYCTX_TX_WR_HMACCTRL  0x7
+#define V_FW_TLS_KEYCTX_TX_WR_HMACCTRL(x) \
+    ((x) << S_FW_TLS_KEYCTX_TX_WR_HMACCTRL)
+#define G_FW_TLS_KEYCTX_TX_WR_HMACCTRL(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_HMACCTRL) & M_FW_TLS_KEYCTX_TX_WR_HMACCTRL)
+
+#define S_FW_TLS_KEYCTX_TX_WR_PROTOVER  4
+#define M_FW_TLS_KEYCTX_TX_WR_PROTOVER  0xf
+#define V_FW_TLS_KEYCTX_TX_WR_PROTOVER(x) \
+    ((x) << S_FW_TLS_KEYCTX_TX_WR_PROTOVER)
+#define G_FW_TLS_KEYCTX_TX_WR_PROTOVER(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_PROTOVER) & M_FW_TLS_KEYCTX_TX_WR_PROTOVER)
+
+#define S_FW_TLS_KEYCTX_TX_WR_CIPHMODE  0
+#define M_FW_TLS_KEYCTX_TX_WR_CIPHMODE  0xf
+#define V_FW_TLS_KEYCTX_TX_WR_CIPHMODE(x) \
+    ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHMODE)
+#define G_FW_TLS_KEYCTX_TX_WR_CIPHMODE(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHMODE) & M_FW_TLS_KEYCTX_TX_WR_CIPHMODE)
+
+#define S_FW_TLS_KEYCTX_TX_WR_AUTHMODE  4
+#define M_FW_TLS_KEYCTX_TX_WR_AUTHMODE  0xf
+#define V_FW_TLS_KEYCTX_TX_WR_AUTHMODE(x) \
+    ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHMODE)
+#define G_FW_TLS_KEYCTX_TX_WR_AUTHMODE(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHMODE) & M_FW_TLS_KEYCTX_TX_WR_AUTHMODE)
+
+#define S_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL 3
+#define M_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL 0x1
+#define V_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL(x) \
+    ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL)
+#define G_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL) & \
+     M_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL)
+#define F_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL \
+    V_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL(1U)
+
+#define S_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL 1
+#define M_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL 0x3
+#define V_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL(x) \
+    ((x) << S_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL)
+#define G_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL) & \
+     M_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL)
+
+#define S_FW_TLS_KEYCTX_TX_WR_RXVALID   0
+#define M_FW_TLS_KEYCTX_TX_WR_RXVALID   0x1
+#define V_FW_TLS_KEYCTX_TX_WR_RXVALID(x) \
+    ((x) << S_FW_TLS_KEYCTX_TX_WR_RXVALID)
+#define G_FW_TLS_KEYCTX_TX_WR_RXVALID(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXVALID) & M_FW_TLS_KEYCTX_TX_WR_RXVALID)
+#define F_FW_TLS_KEYCTX_TX_WR_RXVALID   V_FW_TLS_KEYCTX_TX_WR_RXVALID(1U)
+
+#define S_FW_TLS_KEYCTX_TX_WR_IVPRESENT 7
+#define M_FW_TLS_KEYCTX_TX_WR_IVPRESENT 0x1
+#define V_FW_TLS_KEYCTX_TX_WR_IVPRESENT(x) \
+    ((x) << S_FW_TLS_KEYCTX_TX_WR_IVPRESENT)
+#define G_FW_TLS_KEYCTX_TX_WR_IVPRESENT(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_IVPRESENT) & \
+     M_FW_TLS_KEYCTX_TX_WR_IVPRESENT)
+#define F_FW_TLS_KEYCTX_TX_WR_IVPRESENT V_FW_TLS_KEYCTX_TX_WR_IVPRESENT(1U)
+
+#define S_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT 6
+#define M_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT 0x1
+#define V_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT(x) \
+    ((x) << S_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT)
+#define G_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT) & \
+     M_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT)
+#define F_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT \
+    V_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT(1U)
+
+#define S_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE 3
+#define M_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE 0x7
+#define V_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE(x) \
+    ((x) << S_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE)
+#define G_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE) & \
+     M_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE)
+
+#define S_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE 0
+#define M_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE 0x7
+#define V_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE(x) \
+    ((x) << S_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE)
+#define G_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE) & \
+     M_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE)
+
+#define S_FW_TLS_KEYCTX_TX_WR_IVINSERT  55
+#define M_FW_TLS_KEYCTX_TX_WR_IVINSERT  0x1ffULL
+#define V_FW_TLS_KEYCTX_TX_WR_IVINSERT(x) \
+    ((x) << S_FW_TLS_KEYCTX_TX_WR_IVINSERT)
+#define G_FW_TLS_KEYCTX_TX_WR_IVINSERT(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_IVINSERT) & M_FW_TLS_KEYCTX_TX_WR_IVINSERT)
+
+#define S_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST 47
+#define M_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST 0xffULL
+#define V_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST(x) \
+    ((x) << S_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST)
+#define G_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST) & \
+     M_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST)
+
+#define S_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST 39
+#define M_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST 0xffULL
+#define V_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST(x) \
+    ((x) << S_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST)
+#define G_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST) & \
+     M_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST)
+
+#define S_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST 30
+#define M_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST 0x1ffULL
+#define V_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST(x) \
+    ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST)
+#define G_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST) & \
+     M_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST)
+
+#define S_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST 23
+#define M_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST 0x7f
+#define V_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST(x) \
+    ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST)
+#define G_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST) & \
+     M_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST)
+
+#define S_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST 14
+#define M_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST 0x1ff
+#define V_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST(x) \
+    ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST)
+#define G_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST) & \
+     M_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST)
+
+#define S_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST 7
+#define M_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST 0x7f
+#define V_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST(x) \
+    ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST)
+#define G_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST) & \
+     M_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST)
+
+#define S_FW_TLS_KEYCTX_TX_WR_AUTHINSRT 0
+#define M_FW_TLS_KEYCTX_TX_WR_AUTHINSRT 0x7f
+#define V_FW_TLS_KEYCTX_TX_WR_AUTHINSRT(x) \
+    ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHINSRT)
+#define G_FW_TLS_KEYCTX_TX_WR_AUTHINSRT(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHINSRT) & \
+     M_FW_TLS_KEYCTX_TX_WR_AUTHINSRT)
+
+#define S_FW_TLS_KEYCTX_TX_WR_RENEG     4
+#define M_FW_TLS_KEYCTX_TX_WR_RENEG     0x1
+#define V_FW_TLS_KEYCTX_TX_WR_RENEG(x)  ((x) << S_FW_TLS_KEYCTX_TX_WR_RENEG)
+#define G_FW_TLS_KEYCTX_TX_WR_RENEG(x)  \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_RENEG) & M_FW_TLS_KEYCTX_TX_WR_RENEG)
+#define F_FW_TLS_KEYCTX_TX_WR_RENEG     V_FW_TLS_KEYCTX_TX_WR_RENEG(1U)
+
+#define S_FW_TLS_KEYCTX_TX_WR_DELETE_TX 3
+#define M_FW_TLS_KEYCTX_TX_WR_DELETE_TX 0x1
+#define V_FW_TLS_KEYCTX_TX_WR_DELETE_TX(x) \
+    ((x) << S_FW_TLS_KEYCTX_TX_WR_DELETE_TX)
+#define G_FW_TLS_KEYCTX_TX_WR_DELETE_TX(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_DELETE_TX) & \
+     M_FW_TLS_KEYCTX_TX_WR_DELETE_TX)
+#define F_FW_TLS_KEYCTX_TX_WR_DELETE_TX V_FW_TLS_KEYCTX_TX_WR_DELETE_TX(1U)
+
+#define S_FW_TLS_KEYCTX_TX_WR_DELETE_RX 2
+#define M_FW_TLS_KEYCTX_TX_WR_DELETE_RX 0x1
+#define V_FW_TLS_KEYCTX_TX_WR_DELETE_RX(x) \
+    ((x) << S_FW_TLS_KEYCTX_TX_WR_DELETE_RX)
+#define G_FW_TLS_KEYCTX_TX_WR_DELETE_RX(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_DELETE_RX) & \
+     M_FW_TLS_KEYCTX_TX_WR_DELETE_RX)
+#define F_FW_TLS_KEYCTX_TX_WR_DELETE_RX V_FW_TLS_KEYCTX_TX_WR_DELETE_RX(1U)
+
+#define S_FW_TLS_KEYCTX_TX_WR_WRITE_TX  1
+#define M_FW_TLS_KEYCTX_TX_WR_WRITE_TX  0x1
+#define V_FW_TLS_KEYCTX_TX_WR_WRITE_TX(x) \
+    ((x) << S_FW_TLS_KEYCTX_TX_WR_WRITE_TX)
+#define G_FW_TLS_KEYCTX_TX_WR_WRITE_TX(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_WRITE_TX) & M_FW_TLS_KEYCTX_TX_WR_WRITE_TX)
+#define F_FW_TLS_KEYCTX_TX_WR_WRITE_TX  V_FW_TLS_KEYCTX_TX_WR_WRITE_TX(1U)
+
+#define S_FW_TLS_KEYCTX_TX_WR_WRITE_RX  0
+#define M_FW_TLS_KEYCTX_TX_WR_WRITE_RX  0x1
+#define V_FW_TLS_KEYCTX_TX_WR_WRITE_RX(x) \
+    ((x) << S_FW_TLS_KEYCTX_TX_WR_WRITE_RX)
+#define G_FW_TLS_KEYCTX_TX_WR_WRITE_RX(x) \
+    (((x) >> S_FW_TLS_KEYCTX_TX_WR_WRITE_RX) & M_FW_TLS_KEYCTX_TX_WR_WRITE_RX)
+#define F_FW_TLS_KEYCTX_TX_WR_WRITE_RX  V_FW_TLS_KEYCTX_TX_WR_WRITE_RX(1U)
+
+struct fw_crypto_lookaside_wr {
         __be32 op_to_cctx_size;
         __be32 len16_pkd;
         __be32 session_id;
@@ -3395,116 +3859,124 @@ struct fw_sec_lookaside_lpbk_wr {
         __be64 cookie;
 };
 
-#define S_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE 24
-#define M_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE 0xff
-#define V_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE(x) \
-    ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE)
-#define G_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE(x) \
-    (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE) & \
-     M_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE)
-
-#define S_FW_SEC_LOOKASIDE_LPBK_WR_COMPL 23
-#define M_FW_SEC_LOOKASIDE_LPBK_WR_COMPL 0x1
-#define V_FW_SEC_LOOKASIDE_LPBK_WR_COMPL(x) \
-    ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_COMPL)
-#define G_FW_SEC_LOOKASIDE_LPBK_WR_COMPL(x) \
-    (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_COMPL) & \
-     M_FW_SEC_LOOKASIDE_LPBK_WR_COMPL)
-#define F_FW_SEC_LOOKASIDE_LPBK_WR_COMPL V_FW_SEC_LOOKASIDE_LPBK_WR_COMPL(1U)
-
-#define S_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN 15
-#define M_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN 0xff
-#define V_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN(x) \
-    ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN)
-#define G_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN(x) \
-    (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN) & \
-     M_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN)
-
-#define S_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC 5
-#define M_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC 0x3
-#define V_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC(x) \
-    ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC)
-#define G_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC(x) \
-    (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC) & \
-     M_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC)
-
-#define S_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE 0
-#define M_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE 0x1f
-#define V_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE(x) \
-    ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE)
-#define G_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE(x) \
-    (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE) & \
-     M_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE)
-
-#define S_FW_SEC_LOOKASIDE_LPBK_WR_LEN16 0
-#define M_FW_SEC_LOOKASIDE_LPBK_WR_LEN16 0xff
-#define V_FW_SEC_LOOKASIDE_LPBK_WR_LEN16(x) \
-    ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_LEN16)
-#define G_FW_SEC_LOOKASIDE_LPBK_WR_LEN16(x) \
-    (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_LEN16) & \
-     M_FW_SEC_LOOKASIDE_LPBK_WR_LEN16)
-
-#define S_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID 29
-#define M_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID 0x3
-#define V_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID(x) \
-    ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID)
-#define G_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID(x) \
-    (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID) & \
-     M_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID)
-
-#define S_FW_SEC_LOOKASIDE_LPBK_WR_LCB  27
-#define M_FW_SEC_LOOKASIDE_LPBK_WR_LCB  0x3
-#define V_FW_SEC_LOOKASIDE_LPBK_WR_LCB(x) \
-    ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_LCB)
-#define G_FW_SEC_LOOKASIDE_LPBK_WR_LCB(x) \
-    (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_LCB) & M_FW_SEC_LOOKASIDE_LPBK_WR_LCB)
-
-#define S_FW_SEC_LOOKASIDE_LPBK_WR_PHASH 25
-#define M_FW_SEC_LOOKASIDE_LPBK_WR_PHASH 0x3
-#define V_FW_SEC_LOOKASIDE_LPBK_WR_PHASH(x) \
-    ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_PHASH)
-#define G_FW_SEC_LOOKASIDE_LPBK_WR_PHASH(x) \
-    (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_PHASH) & \
-     M_FW_SEC_LOOKASIDE_LPBK_WR_PHASH)
-
-#define S_FW_SEC_LOOKASIDE_LPBK_WR_IV   23
-#define M_FW_SEC_LOOKASIDE_LPBK_WR_IV   0x3
-#define V_FW_SEC_LOOKASIDE_LPBK_WR_IV(x) \
-    ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_IV)
-#define G_FW_SEC_LOOKASIDE_LPBK_WR_IV(x) \
-    (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_IV) & M_FW_SEC_LOOKASIDE_LPBK_WR_IV)
-
-#define S_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH 10
-#define M_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH 0x3
-#define V_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH(x) \
-    ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH)
-#define G_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH(x) \
-    (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH) & \
-     M_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH)
-
-#define S_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID 0
-#define M_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID 0x3ff
-#define V_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID(x) \
-    ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID)
-#define G_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID(x) \
-    (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID) & \
-     M_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID)
-
-#define S_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE 24
-#define M_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE 0xff
-#define V_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE(x) \
-    ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE)
-#define G_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE(x) \
-    (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE) & \
-     M_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE)
-
-#define S_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE 17
-#define M_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE 0x7f
-#define V_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE(x) \
-    ((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE)
-#define G_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE(x) \
-    (((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE) & \
-     M_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE)
+#define S_FW_CRYPTO_LOOKASIDE_WR_OPCODE 24
+#define M_FW_CRYPTO_LOOKASIDE_WR_OPCODE 0xff
+#define V_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \
+    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_OPCODE)
+#define G_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \
+    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) & \
+     M_FW_CRYPTO_LOOKASIDE_WR_OPCODE)
+
+#define S_FW_CRYPTO_LOOKASIDE_WR_COMPL 23
+#define M_FW_CRYPTO_LOOKASIDE_WR_COMPL 0x1
+#define V_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \
+    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_COMPL)
+#define G_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \
+    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_COMPL) & \
+     M_FW_CRYPTO_LOOKASIDE_WR_COMPL)
+#define F_FW_CRYPTO_LOOKASIDE_WR_COMPL V_FW_CRYPTO_LOOKASIDE_WR_COMPL(1U)
+
+#define S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 15
+#define M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 0xff
+#define V_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \
+    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN)
+#define G_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \
+    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) & \
+     M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN)
+
+#define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 5
+#define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 0x3
+#define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \
+    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC)
+#define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \
+    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) & \
+     M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC)
+
+#define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0
+#define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0x1f
+#define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \
+    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE)
+#define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \
+    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) & \
+     M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE)
+
+#define S_FW_CRYPTO_LOOKASIDE_WR_LEN16 0
+#define M_FW_CRYPTO_LOOKASIDE_WR_LEN16 0xff
+#define V_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \
+    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LEN16)
+#define G_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \
+    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LEN16) & \
+     M_FW_CRYPTO_LOOKASIDE_WR_LEN16)
+
+#define S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 29
+#define M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 0x3
+#define V_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \
+    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID)
+#define G_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \
+    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) & \
+     M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID)
+
+#define S_FW_CRYPTO_LOOKASIDE_WR_LCB  27
+#define M_FW_CRYPTO_LOOKASIDE_WR_LCB  0x3
+#define V_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \
+    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LCB)
+#define G_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \
+    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LCB) & M_FW_CRYPTO_LOOKASIDE_WR_LCB)
+
+#define S_FW_CRYPTO_LOOKASIDE_WR_PHASH 25
+#define M_FW_CRYPTO_LOOKASIDE_WR_PHASH 0x3
+#define V_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \
+    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PHASH)
+#define G_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \
+    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PHASH) & \
+     M_FW_CRYPTO_LOOKASIDE_WR_PHASH)
+
+#define S_FW_CRYPTO_LOOKASIDE_WR_IV   23
+#define M_FW_CRYPTO_LOOKASIDE_WR_IV   0x3
+#define V_FW_CRYPTO_LOOKASIDE_WR_IV(x) \
+    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IV)
+#define G_FW_CRYPTO_LOOKASIDE_WR_IV(x) \
+    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IV) & M_FW_CRYPTO_LOOKASIDE_WR_IV)
+
+#define S_FW_CRYPTO_LOOKASIDE_WR_FQIDX  15
+#define M_FW_CRYPTO_LOOKASIDE_WR_FQIDX  0xff
+#define V_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \
+	((x) << S_FW_CRYPTO_LOOKASIDE_WR_FQIDX)
+#define G_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \
+	(((x) >> S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) &\
+	  M_FW_CRYPTO_LOOKASIDE_WR_FQIDX)
+
+#define S_FW_CRYPTO_LOOKASIDE_WR_TX_CH 10
+#define M_FW_CRYPTO_LOOKASIDE_WR_TX_CH 0x3
+#define V_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \
+    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_TX_CH)
+#define G_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \
+    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) & \
+     M_FW_CRYPTO_LOOKASIDE_WR_TX_CH)
+
+#define S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0
+#define M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0x3ff
+#define V_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \
+    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID)
+#define G_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \
+    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) & \
+     M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID)
+
+#define S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 24
+#define M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 0xff
+#define V_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \
+    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE)
+#define G_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \
+    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) & \
+     M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE)
+
+#define S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 17
+#define M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 0x7f
+#define V_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \
+    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE)
+#define G_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \
+    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) & \
+     M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE)
 
 /******************************************************************************
  *  C O M M A N D s
@@ -3571,6 +4043,7 @@ enum fw_cmd_opcodes {
 	FW_FCOE_STATS_CMD              = 0x37,
 	FW_FCOE_FCF_CMD                = 0x38,
 	FW_DCB_IEEE_CMD		       = 0x3a,
+	FW_DIAG_CMD		       = 0x3d,
 	FW_PTP_CMD                     = 0x3e,
 	FW_LASTC2E_CMD                 = 0x40,
 	FW_ERROR_CMD                   = 0x80,
@@ -4095,8 +4568,9 @@ enum fw_caps_config_iscsi {
 	FW_CAPS_CONFIG_ISCSI_TARGET_CMDOFLD = 0x00000100,
 };
 
-enum fw_caps_config_tls {
-	FW_CAPS_CONFIG_TLSKEYS = 0x00000001,
+enum fw_caps_config_crypto {
+	FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001,
+	FW_CAPS_CONFIG_TLSKEYS = 0x00000002,
 };
 
 enum fw_caps_config_fcoe {
@@ -4128,7 +4602,7 @@ struct fw_caps_config_cmd {
 	__be16 niccaps;
 	__be16 toecaps;
 	__be16 rdmacaps;
-	__be16 tlscaps;
+	__be16 cryptocaps;
 	__be16 iscsicaps;
 	__be16 fcoecaps;
 	__be32 cfcsum;
@@ -4208,6 +4682,7 @@ enum fw_params_param_dev {
 	FW_PARAMS_PARAM_DEV_RSSINFO	= 0x19,
 	FW_PARAMS_PARAM_DEV_SCFGREV	= 0x1A,
 	FW_PARAMS_PARAM_DEV_VPDREV	= 0x1B,
+	FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR	= 0x1C,
 };
 
 /*
@@ -4294,6 +4769,7 @@ enum fw_params_param_pfvf {
         FW_PARAMS_PARAM_PFVF_TLS_END = 0x35,
 	FW_PARAMS_PARAM_PFVF_RAWF_START	= 0x36,
 	FW_PARAMS_PARAM_PFVF_RAWF_END	= 0x37,
+	FW_PARAMS_PARAM_PFVF_RSSKEYINFO	= 0x38,
 };
 
 /*
@@ -6305,7 +6781,7 @@ struct fw_acl_vlan_cmd {
 enum fw_port_cap {
 	FW_PORT_CAP_SPEED_100M		= 0x0001,
 	FW_PORT_CAP_SPEED_1G		= 0x0002,
-	FW_PORT_CAP_SPEED_2_5G		= 0x0004,
+	FW_PORT_CAP_SPEED_25G		= 0x0004,
 	FW_PORT_CAP_SPEED_10G		= 0x0008,
 	FW_PORT_CAP_SPEED_40G		= 0x0010,
 	FW_PORT_CAP_SPEED_100G		= 0x0020,
@@ -6776,7 +7252,13 @@ enum fw_port_type {
 	FW_PORT_TYPE_QSA	= 13,	/* No, 1, Yes, No, No, No, 10G */
 	FW_PORT_TYPE_QSFP	= 14,	/* No, 4, Yes, No, No, No, 40G */
 	FW_PORT_TYPE_BP40_BA	= 15,	/* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
-
+	FW_PORT_TYPE_KR4_100G	= 16,	/* No, 4, 100G, Backplane */
+	FW_PORT_TYPE_CR4_QSFP	= 17,	/* No, 4, 100G */
+	FW_PORT_TYPE_CR_QSFP	= 18,	/* No, 1, 25G Spider cable */
+	FW_PORT_TYPE_CR_SFP28	= 19,	/* No, 1, 25G - Old vpd */
+	FW_PORT_TYPE_SFP28	= 20,	/* No, 1, 25G - New vpd */
+	FW_PORT_TYPE_KR_SFP28	= 21,	/* No, 1, 25G using Backplane */
+	FW_PORT_TYPE_CR2_QSFP	= 22,	/* No, 2, 50G */
 	FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
 };
 
@@ -7477,7 +7959,7 @@ struct fw_rss_glb_config_cmd {
 			__be64 r5;
 		} manual;
 		struct fw_rss_glb_config_basicvirtual {
-			__be32 mode_pkd;
+			__be32 mode_keymode;
 			__be32 synmapen_to_hashtoeplitz;
 			__be64 r8;
 			__be64 r9;
@@ -7495,6 +7977,19 @@ struct fw_rss_glb_config_cmd {
 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL	1
 #define FW_RSS_GLB_CONFIG_CMD_MODE_MAX		1
 
+#define S_FW_RSS_GLB_CONFIG_CMD_KEYMODE	26
+#define M_FW_RSS_GLB_CONFIG_CMD_KEYMODE	0x3
+#define V_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \
+    ((x) << S_FW_RSS_GLB_CONFIG_CMD_KEYMODE)
+#define G_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \
+    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) & \
+     M_FW_RSS_GLB_CONFIG_CMD_KEYMODE)
+
+#define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBKEY	0
+#define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBVF_KEY	1
+#define FW_RSS_GLB_CONFIG_CMD_KEYMODE_PFVF_KEY	2
+#define FW_RSS_GLB_CONFIG_CMD_KEYMODE_IDXVF_KEY	3
+
 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8
 #define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1
 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
@@ -7594,7 +8089,8 @@ struct fw_rss_vi_config_cmd {
 		struct fw_rss_vi_config_basicvirtual {
 			__be32 r6;
 			__be32 defaultq_to_udpen;
-			__be64 r9;
+			__be32 secretkeyidx_pkd;
+			__be32 secretkeyxor;
 			__be64 r10;
 		} basicvirtual;
 	} u;
@@ -7661,6 +8157,14 @@ struct fw_rss_vi_config_cmd {
     (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN	V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
 
+#define S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0
+#define M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0xf
+#define V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \
+    ((x) << S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX)
+#define G_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \
+    (((x) >> S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) & \
+     M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX)
+
 enum fw_sched_sc {
 	FW_SCHED_SC_CONFIG		= 0,
 	FW_SCHED_SC_PARAMS		= 1,
@@ -8565,6 +9069,43 @@ struct fw_debug_cmd {
 #define G_FW_DEBUG_CMD_TYPE(x)		\
     (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
 
+enum fw_diag_cmd_type {
+	FW_DIAG_CMD_TYPE_OFLDIAG = 0,
+};
+
+enum fw_diag_cmd_ofldiag_op {
+	FW_DIAG_CMD_OFLDIAG_TEST_NONE = 0,
+	FW_DIAG_CMD_OFLDIAG_TEST_START,
+	FW_DIAG_CMD_OFLDIAG_TEST_STOP,
+	FW_DIAG_CMD_OFLDIAG_TEST_STATUS,
+};
+
+enum fw_diag_cmd_ofldiag_status {
+	FW_DIAG_CMD_OFLDIAG_STATUS_IDLE = 0,
+	FW_DIAG_CMD_OFLDIAG_STATUS_RUNNING,
+	FW_DIAG_CMD_OFLDIAG_STATUS_FAILED,
+	FW_DIAG_CMD_OFLDIAG_STATUS_PASSED,
+};
+
+struct fw_diag_cmd {
+	__be32 op_type;
+	__be32 len16_pkd;
+	union fw_diag_test {
+		struct fw_diag_test_ofldiag {
+			__u8   test_op;
+			__u8   r3;
+			__be16 test_status;
+			__be32 duration;
+		} ofldiag;
+	} u;
+};
+
+#define S_FW_DIAG_CMD_TYPE		0
+#define M_FW_DIAG_CMD_TYPE		0xff
+#define V_FW_DIAG_CMD_TYPE(x)		((x) << S_FW_DIAG_CMD_TYPE)
+#define G_FW_DIAG_CMD_TYPE(x)		\
+    (((x) >> S_FW_DIAG_CMD_TYPE) & M_FW_DIAG_CMD_TYPE)
+
 /******************************************************************************
  *   P C I E   F W   R E G I S T E R
  **************************************/
@@ -8778,14 +9319,19 @@ enum fw_hdr_chip {
 
 enum {
 	T4FW_VERSION_MAJOR	= 0x01,
-	T4FW_VERSION_MINOR	= 0x05,
-	T4FW_VERSION_MICRO	= 0x25,
+	T4FW_VERSION_MINOR	= 0x10,
+	T4FW_VERSION_MICRO	= 0x0c,
 	T4FW_VERSION_BUILD	= 0x00,
 
 	T5FW_VERSION_MAJOR	= 0x01,
-	T5FW_VERSION_MINOR	= 0x05,
-	T5FW_VERSION_MICRO	= 0x25,
+	T5FW_VERSION_MINOR	= 0x10,
+	T5FW_VERSION_MICRO	= 0x0c,
 	T5FW_VERSION_BUILD	= 0x00,
+
+	T6FW_VERSION_MAJOR	= 0x01,
+	T6FW_VERSION_MINOR	= 0x10,
+	T6FW_VERSION_MICRO	= 0x0c,
+	T6FW_VERSION_BUILD	= 0x00,
 };
 
 enum {