cxgbe(4): Update firmware to 1.8.4.0.

MFC after:	5 days

1 files changed, 137 insertions, 47 deletions

diff --git a/sys/dev/cxgbe/firmware/t4fw_interface.h b/sys/dev/cxgbe/firmware/t4fw_interface.h
index 804d09f..cd03816 100644
--- a/sys/dev/cxgbe/firmware/t4fw_interface.h
+++ b/sys/dev/cxgbe/firmware/t4fw_interface.h
@@ -45,9 +45,11 @@ enum fw_retval {
 	FW_EFAULT		= 14,	/* bad address; fw bad */
 	FW_EBUSY		= 16,	/* resource busy */
 	FW_EEXIST		= 17,	/* file exists */
+	FW_ENODEV		= 19,	/* no such device */
 	FW_EINVAL		= 22,	/* invalid argument */
 	FW_ENOSPC		= 28,	/* no space left on device */
 	FW_ENOSYS		= 38,	/* functionality not implemented */
+	FW_ENODATA		= 61,	/* no data available */
 	FW_EPROTO		= 71,	/* protocol error */
 	FW_EADDRINUSE		= 98,	/* address already in use */
 	FW_EADDRNOTAVAIL	= 99,	/* cannot assigned requested address */
@@ -114,6 +116,8 @@ enum fw_wr_opcodes {
 	FW_SCSI_TGT_ACC_WR	= 0x35,
 	FW_SCSI_TGT_XMIT_WR	= 0x36,
 	FW_SCSI_TGT_RSP_WR	= 0x37,
+	FW_POFCOE_TCB_WR	= 0x42,
+	FW_POFCOE_ULPTX_WR	= 0x43,
 	FW_LASTC2E_WR		= 0x70
 };
 
@@ -556,12 +560,15 @@ struct fw_eth_tx_uo_wr {
 	__be32 op_immdlen;
 	__be32 equiq_to_len16;
 	__be64 r3;
-	__be16 ethlen;
+	__u8   r4;
+	__u8   ethlen;
 	__be16 iplen;
-	__be16 udplen;
+	__u8   udplen;
+	__u8   rtplen;
+	__be16 r5;
 	__be16 mss;
+	__be16 schedpktsize;
 	__be32 length;
-	__be32 r4;
 };
 
 struct fw_eq_flush_wr {
@@ -708,19 +715,19 @@ enum fw_flowc_mnem_uostate {
 };
 
 enum fw_flowc_mnem {
-	FW_FLOWC_MNEM_PFNVFN,		/* PFN [15:8] VFN [7:0] */
-	FW_FLOWC_MNEM_CH,
-	FW_FLOWC_MNEM_PORT,
-	FW_FLOWC_MNEM_IQID,
-	FW_FLOWC_MNEM_SNDNXT,
-	FW_FLOWC_MNEM_RCVNXT,
-	FW_FLOWC_MNEM_SNDBUF,
-	FW_FLOWC_MNEM_MSS,
-	FW_FLOWC_MNEM_TXDATAPLEN_MAX,
-	FW_FLOWC_MNEM_TCPSTATE,
-	FW_FLOWC_MNEM_UOSTATE,
-	FW_FLOWC_MNEM_SCHEDCLASS,
-	FW_FLOWC_MNEM_DCBPRIO,
+	FW_FLOWC_MNEM_PFNVFN		= 0, /* PFN [15:8] VFN [7:0] */
+	FW_FLOWC_MNEM_CH		= 1,
+	FW_FLOWC_MNEM_PORT		= 2,
+	FW_FLOWC_MNEM_IQID		= 3,
+	FW_FLOWC_MNEM_SNDNXT		= 4,
+	FW_FLOWC_MNEM_RCVNXT		= 5,
+	FW_FLOWC_MNEM_SNDBUF		= 6,
+	FW_FLOWC_MNEM_MSS		= 7,
+	FW_FLOWC_MNEM_TXDATAPLEN_MAX	= 8,
+	FW_FLOWC_MNEM_TCPSTATE		= 9,
+	FW_FLOWC_MNEM_UOSTATE		= 10,
+	FW_FLOWC_MNEM_SCHEDCLASS	= 11,
+	FW_FLOWC_MNEM_DCBPRIO		= 12,
 };
 
 struct fw_flowc_mnemval {
@@ -2789,6 +2796,55 @@ struct fw_scsi_tgt_rsp_wr {
 #define G_FW_SCSI_TGT_RSP_WR_CLASS(x)	\
     (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS)
 
+struct fw_pofcoe_tcb_wr {
+	__be32 op_compl;
+	__be32 equiq_to_len16;
+	__be64 cookie;
+	__be32 tid_to_port;
+	__be16 x_id;
+	__be16 vlan_id;
+	__be32 s_id;
+	__be32 d_id;
+	__be32 tag;
+	__be32 xfer_len;
+	__be32 r4;
+	__be16 r5;
+	__be16 iqid;
+};
+
+#define S_FW_POFCOE_TCB_WR_TID		12
+#define M_FW_POFCOE_TCB_WR_TID		0xfffff
+#define V_FW_POFCOE_TCB_WR_TID(x)	((x) << S_FW_POFCOE_TCB_WR_TID)
+#define G_FW_POFCOE_TCB_WR_TID(x)	\
+    (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID)
+
+#define S_FW_POFCOE_TCB_WR_ALLOC	4
+#define M_FW_POFCOE_TCB_WR_ALLOC	0x1
+#define V_FW_POFCOE_TCB_WR_ALLOC(x)	((x) << S_FW_POFCOE_TCB_WR_ALLOC)
+#define G_FW_POFCOE_TCB_WR_ALLOC(x)	\
+    (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC)
+#define F_FW_POFCOE_TCB_WR_ALLOC	V_FW_POFCOE_TCB_WR_ALLOC(1U)
+
+#define S_FW_POFCOE_TCB_WR_FREE		3
+#define M_FW_POFCOE_TCB_WR_FREE		0x1
+#define V_FW_POFCOE_TCB_WR_FREE(x)	((x) << S_FW_POFCOE_TCB_WR_FREE)
+#define G_FW_POFCOE_TCB_WR_FREE(x)	\
+    (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE)
+#define F_FW_POFCOE_TCB_WR_FREE	V_FW_POFCOE_TCB_WR_FREE(1U)
+
+#define S_FW_POFCOE_TCB_WR_PORT		0
+#define M_FW_POFCOE_TCB_WR_PORT		0x7
+#define V_FW_POFCOE_TCB_WR_PORT(x)	((x) << S_FW_POFCOE_TCB_WR_PORT)
+#define G_FW_POFCOE_TCB_WR_PORT(x)	\
+    (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT)
+
+struct fw_pofcoe_ulptx_wr {
+	__be32 op_pkd;
+	__be32 equiq_to_len16;
+	__u64  cookie;
+};
+
+
 /******************************************************************************
  *  C O M M A N D s
  *********************/
@@ -2937,8 +2993,9 @@ enum fw_ldst_addrspc {
 	FW_LDST_ADDRSPC_MPS       = 0x0020,
 	FW_LDST_ADDRSPC_FUNC      = 0x0028,
 	FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
-	FW_LDST_ADDRSPC_FUNC_I2C  = 0x002A,
+	FW_LDST_ADDRSPC_FUNC_I2C  = 0x002A, /* legacy */
 	FW_LDST_ADDRSPC_LE	  = 0x0030,
+	FW_LDST_ADDRSPC_I2C       = 0x0038,
 };
 
 /*
@@ -3018,17 +3075,26 @@ struct fw_ldst_cmd {
 			__be16 nset_pkd;
 			__be32 data[12];
 		} pcie;
-		struct fw_ldst_i2c {
+		struct fw_ldst_i2c_deprecated {
 			__u8   pid_pkd;
 			__u8   base;
 			__u8   boffset;
 			__u8   data;
 			__be32 r9;
+		} i2c_deprecated;
+		struct fw_ldst_i2c {
+			__u8   pid;
+			__u8   did;
+			__u8   boffset;
+			__u8   blen;
+			__be32 r9;
+			__u8   data[48];
 		} i2c;
 		struct fw_ldst_le {
-			__be16	region;
-			__be16	nval;
-			__u32	val[12];
+			__be32 index;
+			__be32 r9;
+			__u8   val[33];
+			__u8   r11[7];
 		} le;
 	} u;
 };
@@ -3332,6 +3398,8 @@ enum fw_caps_config_fcoe {
 	FW_CAPS_CONFIG_FCOE_INITIATOR	= 0x00000001,
 	FW_CAPS_CONFIG_FCOE_TARGET	= 0x00000002,
 	FW_CAPS_CONFIG_FCOE_CTRL_OFLD   = 0x00000004,
+	FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008,
+	FW_CAPS_CONFIG_POFCOE_TARGET    = 0x00000010,
 };
 
 enum fw_memtype_cf {
@@ -3465,7 +3533,8 @@ enum fw_params_param_pfvf {
 	FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
 	FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
 	FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F,
-	FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30
+	FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
+	FW_PARAMS_PARAM_PFVF_CPLFW4MSG_CPLSGEEGRUPDATE = 0x31
 };
 
 /*
@@ -3474,6 +3543,7 @@ enum fw_params_param_pfvf {
 enum fw_params_param_dmaq {
 	FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
 	FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
+	FW_PARAMS_PARAM_DMAQ_IQ_INTIDX	= 0x02,
 	FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
 	FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
 	FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
@@ -4943,7 +5013,7 @@ struct fw_vi_cmd {
 	__u8   portid_pkd;
 	__u8   nmac;
 	__u8   nmac0[6];
-	__be16 rsssize_pkd;
+	__be16 norss_rsssize;
 	__u8   nmac1[6];
 	__be16 idsiiq_pkd;
 	__u8   nmac2[6];
@@ -4998,6 +5068,13 @@ struct fw_vi_cmd {
 #define G_FW_VI_CMD_PORTID(x)	\
     (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID)
 
+#define S_FW_VI_CMD_NORSS	11
+#define M_FW_VI_CMD_NORSS	0x1
+#define V_FW_VI_CMD_NORSS(x)	((x) << S_FW_VI_CMD_NORSS)
+#define G_FW_VI_CMD_NORSS(x)	\
+    (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS)
+#define F_FW_VI_CMD_NORSS	V_FW_VI_CMD_NORSS(1U)
+
 #define S_FW_VI_CMD_RSSSIZE	0
 #define M_FW_VI_CMD_RSSSIZE	0x7ff
 #define V_FW_VI_CMD_RSSSIZE(x)	((x) << S_FW_VI_CMD_RSSSIZE)
@@ -5524,6 +5601,8 @@ enum fw_port_dcb_type {
 
 enum fw_port_diag_ops {
 	FW_PORT_DIAGS_TEMP		= 0x00,
+	FW_PORT_DIAGS_TX_POWER		= 0x01,
+	FW_PORT_DIAGS_RX_POWER		= 0x02,
 };
 
 struct fw_port_cmd {
@@ -5560,8 +5639,9 @@ struct fw_port_cmd {
 			__be64 r9;
 		} info;
 		struct fw_port_diags {
-			__be32 diagop_diagval;
-			__be32 r;
+			__u8   diagop;
+			__u8   r[3];
+			__be32 diagval;
 		} diags;
 		union fw_port_dcb {
 			struct fw_port_dcb_pgid {
@@ -5602,7 +5682,7 @@ struct fw_port_cmd {
 			struct fw_port_dcb_control {
 				__u8   type;
 				__u8   all_syncd_pkd;
-				__be16   r10_lo[3];
+				__be16 r10_lo[3];
 				__be64 r11;
 			} control;
 		} dcb;
@@ -5748,18 +5828,6 @@ struct fw_port_cmd {
 #define G_FW_PORT_CMD_MODTYPE(x)	\
     (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
 
-#define S_FW_PORT_CMD_DIAGOP	24
-#define M_FW_PORT_CMD_DIAGOP	0xff
-#define V_FW_PORT_CMD_DIAGOP(x)	((x) << S_FW_PORT_CMD_DIAGOP)
-#define G_FW_PORT_CMD_DIAGOP(x)	\
-    (((x) >> S_FW_PORT_CMD_DIAGOP) & M_FW_PORT_CMD_DIAGOP)
-
-#define S_FW_PORT_CMD_DIAGVAL		0
-#define M_FW_PORT_CMD_DIAGVAL		0xffffff
-#define V_FW_PORT_CMD_DIAGVAL(x)	((x) << S_FW_PORT_CMD_DIAGVAL)
-#define G_FW_PORT_CMD_DIAGVAL(x)	\
-    (((x) >> S_FW_PORT_CMD_DIAGVAL) & M_FW_PORT_CMD_DIAGVAL)
-
 #define S_FW_PORT_CMD_APPLY	7
 #define M_FW_PORT_CMD_APPLY	0x1
 #define V_FW_PORT_CMD_APPLY(x)	((x) << S_FW_PORT_CMD_APPLY)
@@ -5816,6 +5884,10 @@ enum fw_port_module_type {
 enum fw_port_mod_sub_type {
 	FW_PORT_MOD_SUB_TYPE_NA,
 	FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1,
+	FW_PORT_MOD_SUB_TYPE_TN8022=0x2,
+	FW_PORT_MOD_SUB_TYPE_AQ1202=0x3,
+	FW_PORT_MOD_SUB_TYPE_88x3120=0x4,
+	FW_PORT_MOD_SUB_TYPE_BCM84834=0x5,
 	FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8,
 
 	/*
@@ -5832,11 +5904,13 @@ enum fw_port_mod_sub_type {
 /* link down reason codes (3b) */
 enum fw_port_link_dn_rc {
 	FW_PORT_LINK_DN_RC_NONE,
-	FW_PORT_LINK_DN_RC_REMFLT,
-	FW_PORT_LINK_DN_ANEG_F,
-	FW_PORT_LINK_DN_MS_RES_F,
-	FW_PORT_LINK_DN_OVERHEAT,
-	FW_PORT_LINK_DN_UNKNOWN
+	FW_PORT_LINK_DN_RC_REMFLT,	/* Remote fault detected */
+	FW_PORT_LINK_DN_ANEG_F,		/* Auto-negotiation fault */
+	FW_PORT_LINK_DN_RESERVED3,
+	FW_PORT_LINK_DN_OVERHEAT,	/* Port overheated */
+	FW_PORT_LINK_DN_UNKNOWN,	/* Unable to determine reason */
+	FW_PORT_LINK_DN_RX_LOS,		/* No RX signal detected */
+	FW_PORT_LINK_DN_RESERVED7
 };
 
 /* port stats */
@@ -6635,7 +6709,6 @@ enum fw_sched_params_level {
 	FW_SCHED_PARAMS_LEVEL_CL_RL	= 0,
 	FW_SCHED_PARAMS_LEVEL_CL_WRR	= 1,
 	FW_SCHED_PARAMS_LEVEL_CH_RL	= 2,
-	FW_SCHED_PARAMS_LEVEL_CH_WRR	= 3,
 };
 
 enum fw_sched_params_mode {
@@ -6676,7 +6749,8 @@ struct fw_sched_cmd {
 			__be32 max;
 			__be16 weight;
 			__be16 pktsize;
-			__be32 r4;
+			__be16 burstsize;
+			__be16 r4;
 		} params;
 	} u;
 };
@@ -7353,6 +7427,16 @@ struct fw_debug_cmd {
  *   P C I E   F W   R E G I S T E R
  **************************************/
 
+enum pcie_fw_eval {
+	PCIE_FW_EVAL_CRASH		= 0,
+	PCIE_FW_EVAL_PREP		= 1,
+	PCIE_FW_EVAL_CONF		= 2,
+	PCIE_FW_EVAL_INIT		= 3,
+	PCIE_FW_EVAL_UNEXPECTEDEVENT	= 4,
+	PCIE_FW_EVAL_OVERHEAT		= 5,
+	PCIE_FW_EVAL_DEVICESHUTDOWN	= 6,
+};
+
 /**
  *	Register definitions for the PCIE_FW register which the firmware uses
  *	to retain status across RESETs.  This register should be considered
@@ -7377,6 +7461,11 @@ struct fw_debug_cmd {
 #define G_PCIE_FW_HALT(x)       (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT)
 #define F_PCIE_FW_HALT          V_PCIE_FW_HALT(1U)
 
+#define S_PCIE_FW_EVAL		24
+#define M_PCIE_FW_EVAL		0x7
+#define V_PCIE_FW_EVAL(x)	((x) << S_PCIE_FW_EVAL)
+#define G_PCIE_FW_EVAL(x)	(((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL)
+
 #define S_PCIE_FW_STAGE		21
 #define M_PCIE_FW_STAGE		0x7
 #define V_PCIE_FW_STAGE(x)	((x) << S_PCIE_FW_STAGE)
@@ -7455,11 +7544,11 @@ struct fw_hdr {
 	__u8	intfver_ri;
 	__u8	intfver_iscsipdu;
 	__u8	intfver_iscsi;
+	__u8	intfver_fcoepdu;
 	__u8	intfver_fcoe;
-	__u8	reserved2;
+	__u32	reserved2;
 	__u32	reserved3;
 	__u32	reserved4;
-	__u32	reserved5;
 	__be32	flags;
 	__be32	reserved6[23];
 };
@@ -7504,6 +7593,7 @@ enum {
 	FW_HDR_INTFVER_RI	= 0x00,
 	FW_HDR_INTFVER_ISCSIPDU	= 0x00,
 	FW_HDR_INTFVER_ISCSI	= 0x00,
+	FW_HDR_INTFVER_FCOEPDU  = 0x00,
 	FW_HDR_INTFVER_FCOE	= 0x00,
 };