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authornp <np@FreeBSD.org>2009-10-05 20:21:41 +0000
committernp <np@FreeBSD.org>2009-10-05 20:21:41 +0000
commit7e261d5659ff5086d3f0055f0d6ba9ede8e15f30 (patch)
tree802f7eebcdd7790a4ecc31d402dcf0fa269b0ff2 /sys/dev/cxgb/common/cxgb_regs.h
parent3c6c0fbaddc33d4c8303445bbe08717280dce4cc (diff)
downloadFreeBSD-src-7e261d5659ff5086d3f0055f0d6ba9ede8e15f30.zip
FreeBSD-src-7e261d5659ff5086d3f0055f0d6ba9ede8e15f30.tar.gz
cxgb(4) updates, including:
- support for the new Gen-2, BT, and LP-CR cards. - T3 firmware 7.7.0 - shared "common code" updates. Approved by: gnn (mentor) Obtained from: Chelsio MFC after: 1 month
Diffstat (limited to 'sys/dev/cxgb/common/cxgb_regs.h')
-rw-r--r--sys/dev/cxgb/common/cxgb_regs.h28
1 files changed, 28 insertions, 0 deletions
diff --git a/sys/dev/cxgb/common/cxgb_regs.h b/sys/dev/cxgb/common/cxgb_regs.h
index dd8db9a..644fa26 100644
--- a/sys/dev/cxgb/common/cxgb_regs.h
+++ b/sys/dev/cxgb/common/cxgb_regs.h
@@ -280,6 +280,11 @@ $FreeBSD$
#define V_RSPQ7STARVED(x) ((x) << S_RSPQ7STARVED)
#define F_RSPQ7STARVED V_RSPQ7STARVED(1U)
+#define S_RSPQXSTARVED 0
+#define M_RSPQXSTARVED 0xff
+#define V_RSPQXSTARVED(x) ((x) << S_RSPQXSTARVED)
+#define G_RSPQXSTARVED(x) (((x) >> S_RSPQXSTARVED) & M_RSPQXSTARVED)
+
#define S_RSPQ0DISABLED 8
#define V_RSPQ0DISABLED(x) ((x) << S_RSPQ0DISABLED)
#define F_RSPQ0DISABLED V_RSPQ0DISABLED(1U)
@@ -376,6 +381,11 @@ $FreeBSD$
#define V_FL15EMPTY(x) ((x) << S_FL15EMPTY)
#define F_FL15EMPTY V_FL15EMPTY(1U)
+#define S_FLXEMPTY 16
+#define M_FLXEMPTY 0xffff
+#define V_FLXEMPTY(x) ((x) << S_FLXEMPTY)
+#define G_FLXEMPTY(x) (((x) >> S_FLXEMPTY) & M_FLXEMPTY)
+
#define A_SG_EGR_PRI_CNT 0x50
#define S_EGRERROPCODE 24
@@ -6235,10 +6245,28 @@ $FreeBSD$
#define V_ACK(x) ((x) << S_ACK)
#define F_ACK V_ACK(1U)
+#define S_I2C_DATA 0
+#define M_I2C_DATA 0xff
+#define V_I2C_DATA(x) ((x) << S_I2C_DATA)
+#define G_I2C_DATA(x) (((x) >> S_I2C_DATA) & M_I2C_DATA)
+
+#define S_I2C_BUSY 31
+#define V_I2C_BUSY(x) ((x) << S_I2C_BUSY)
+#define F_I2C_BUSY V_I2C_BUSY(1U)
+
+#define S_I2C_ACK 30
+#define V_I2C_ACK(x) ((x) << S_I2C_ACK)
+#define F_I2C_ACK V_I2C_ACK(1U)
+
#define S_I2C_CONT 1
#define V_I2C_CONT(x) ((x) << S_I2C_CONT)
#define F_I2C_CONT V_I2C_CONT(1U)
+#define S_I2C_RDWR 0
+#define V_I2C_RDWR(x) ((x) << S_I2C_RDWR)
+#define F_I2C_READ V_I2C_RDWR(0U)
+#define F_I2C_WRITE V_I2C_RDWR(1U)
+
/* registers for module MI1 */
#define MI1_BASE_ADDR 0x6b0
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