Updated cx driver commit part 1: bring in the new kernel driver.

This is the vastly updated cx drvier from Roman Kurakin <rik@cronyx.ru>
who has been patiently waiting for this update for sometime.

The driver is mostly a rewrite from the version we have in the tree.
While some similarities remain, losing the little history that the old
driver has is not a big loss, and the re@ felt it was easier this way (less
error prone).

The userland parts of this update will be committed shortly.

The driver is not connected to the build yet.  I want to make sure I
don't break any platform at any time, so I want to test that with
these files in the tree before I continue (on the off chance I'm
forgetting a file).

I changed the DEBUG macro to CX_DEBUG from the code that was submitted
(to not break when we go to building with opt_global.h after the
release), as well adding $FreeBSD$.

Submitted by: Roman Kurakin
Approved by: re@ <scottl>

9 files changed, 7566 insertions, 0 deletions

diff --git a/sys/dev/cx/cronyxfw.h b/sys/dev/cx/cronyxfw.h
new file mode 100644
index 0000000..7026413
--- /dev/null
+++ b/sys/dev/cx/cronyxfw.h
@@ -0,0 +1,32 @@
+/*
+ * Cronyx firmware definitions.
+ *
+ * Copyright (C) 1996 Cronyx Engineering.
+ * Author: Serge Vakulenko, <vak@cronyx.ru>
+ *
+ * This software is distributed with NO WARRANTIES, not even the implied
+ * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Authors grant any other persons or organisations permission to use
+ * or modify this software as long as this message is kept with the software,
+ * all derivative works or modified versions.
+ *
+ * Cronyx Id: cronyxfw.h,v 1.1.2.1 2003/11/12 17:09:49 rik Exp $
+ * $FreeBSD$
+ */
+#define CRONYX_DAT_MAGIC 2001107011L	/* firmware file magic */
+
+typedef struct _cr_dat_tst {
+	long start;			/* verify start */
+	long end;			/* verify end */
+} cr_dat_tst_t;
+
+typedef struct {                        /* firmware file header */
+	unsigned long magic;            /* firmware magic */
+	long hdrsz;			/* header size in bytes */
+	long len;			/* firmware data size in bits */
+	long ntest;			/* number of tests */
+	unsigned long sum;              /* header+tests+data checksum */
+	char version[8];                /* firmware version number */
+	char date[8];                   /* date when compiled */
+} cr_dat_t;
diff --git a/sys/dev/cx/csigma.c b/sys/dev/cx/csigma.c
new file mode 100644
index 0000000..db2c138
--- /dev/null
+++ b/sys/dev/cx/csigma.c
@@ -0,0 +1,1438 @@
+/*
+ * Low-level subroutines for Cronyx-Sigma adapter.
+ *
+ * Copyright (C) 1994-2000 Cronyx Engineering.
+ * Author: Serge Vakulenko, <vak@cronyx.ru>
+ *
+ * This software is distributed with NO WARRANTIES, not even the implied
+ * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Authors grant any other persons or organisations permission to use
+ * or modify this software as long as this message is kept with the software,
+ * all derivative works or modified versions.
+ *
+ * Cronyx Id: csigma.c,v 1.1.2.1 2003/11/12 17:13:41 rik Exp $
+ * $FreeBSD$
+ */
+#include <dev/cx/machdep.h>
+#include <dev/cx/cxddk.h>
+#include <dev/cx/cxreg.h>
+#include <dev/cx/cronyxfw.h>
+
+#define DMA_MASK	0xd4	/* DMA mask register */
+#define DMA_MASK_CLEAR	0x04	/* DMA clear mask */
+#define DMA_MODE	0xd6	/* DMA mode register */
+#define DMA_MODE_MASTER	0xc0	/* DMA master mode */
+
+#define BYTE *(unsigned char*)&
+
+static unsigned char irqmask [] = {
+	BCR0_IRQ_DIS,	BCR0_IRQ_DIS,	BCR0_IRQ_DIS,	BCR0_IRQ_3,
+	BCR0_IRQ_DIS,	BCR0_IRQ_5,	BCR0_IRQ_DIS,	BCR0_IRQ_7,
+	BCR0_IRQ_DIS,	BCR0_IRQ_DIS,	BCR0_IRQ_10,	BCR0_IRQ_11,
+	BCR0_IRQ_12,	BCR0_IRQ_DIS,	BCR0_IRQ_DIS,	BCR0_IRQ_15,
+};
+
+static unsigned char dmamask [] = {
+	BCR0_DMA_DIS,	BCR0_DMA_DIS,	BCR0_DMA_DIS,	BCR0_DMA_DIS,
+	BCR0_DMA_DIS,	BCR0_DMA_5,	BCR0_DMA_6,	BCR0_DMA_7,
+};
+
+/* standard base port set */
+static short porttab [] = {
+	0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0,
+	0x300, 0x320, 0x340, 0x360, 0x380, 0x3a0, 0x3c0, 0x3e0, 0
+};
+
+/* valid IRQs and DRQs */
+static short irqtab [] = { 3, 5, 7, 10, 11, 12, 15, 0 };
+static short dmatab [] = { 5, 6, 7, 0 };
+
+static int valid (short value, short *list)
+{
+	while (*list)
+		if (value == *list++)
+			return 1;
+	return 0;
+}
+
+long cx_rxbaud = 9600;		/* receiver baud rate */
+long cx_txbaud = 9600;		/* transmitter baud rate */
+
+int cx_univ_mode = M_HDLC;	/* univ. chan. mode: async or sync */
+int cx_sync_mode = M_HDLC;	/* sync. chan. mode: HDLC, Bisync or X.21 */
+int cx_iftype = 0;		/* univ. chan. interface: upper/lower */
+
+static int cx_probe_chip (port_t base);
+static void cx_setup_chip (cx_chan_t *c);
+
+/*
+ * Wait for CCR to clear.
+ */
+void cx_cmd (port_t base, int cmd)
+{
+	port_t port = CCR(base);
+	int count;
+
+	/* Wait 10 msec for the previous command to complete. */
+	for (count=0; inb(port) && count<20000; ++count)
+		continue;
+
+	/* Issue the command. */
+	outb (port, cmd);
+
+	/* Wait 10 msec for the command to complete. */
+	for (count=0; inb(port) && count<20000; ++count)
+		continue;
+}
+
+/*
+ * Reset the chip.
+ */
+static int cx_reset (port_t port)
+{
+	int count;
+
+	/* Wait up to 10 msec for revision code to appear after reset. */
+	for (count=0; count<20000; ++count)
+		if (inb(GFRCR(port)) != 0)
+			break;
+
+	cx_cmd (port, CCR_RSTALL);
+
+	/* Firmware revision code should clear imediately. */
+	/* Wait up to 10 msec for revision code to appear again. */
+	for (count=0; count<20000; ++count)
+		if (inb(GFRCR(port)) != 0)
+			return (1);
+
+	/* Reset failed. */
+	return (0);
+}
+
+int cx_download (port_t port, const unsigned char *firmware, long bits,
+	const cr_dat_tst_t *tst)
+{
+	unsigned char cr2, sr;
+	long i, n, maxn = (bits + 7) / 8;
+	int v, b;
+
+	inb (BDET(port));
+	for (i=n=0; n<maxn; ++n) {
+		v = ((firmware[n] ^ ' ') << 1) | (firmware[n] >> 7 & 1);
+		for (b=0; b<7; b+=2, i+=2) {
+			if (i >= bits)
+				break;
+			cr2 = 0;
+			if (v >> b & 1) cr2 |= BCR2_TMS;
+			if (v >> b & 2) cr2 |= BCR2_TDI;
+			outb (BCR2(port), cr2);
+			sr = inb (BSR(port));
+			outb (BCR0(port), BCR0800_TCK);
+			outb (BCR0(port), 0);
+			if (i >= tst->end)
+				++tst;
+			if (i >= tst->start && (sr & BSR800_LERR))
+				return (0);
+		}
+	}
+	return (1);
+}
+
+/*
+ * Check if the Sigma-XXX board is present at the given base port.
+ */
+static int cx_probe_chained_board (port_t port, int *c0, int *c1)
+{
+	int rev, i;
+
+	/* Read and check the board revision code. */
+	rev = inb (BSR(port));
+	*c0 = *c1 = 0;
+	switch (rev & BSR_VAR_MASK) {
+	case CRONYX_100:	*c0 = 1;	break;
+	case CRONYX_400:	*c1 = 1;	break;
+	case CRONYX_500:	*c0 = *c1 = 1;	break;
+	case CRONYX_410:	*c0 = 1;	break;
+	case CRONYX_810:	*c0 = *c1 = 1;	break;
+	case CRONYX_410s:	*c0 = 1;	break;
+	case CRONYX_810s:	*c0 = *c1 = 1;	break;
+	case CRONYX_440:	*c0 = 1;	break;
+	case CRONYX_840:	*c0 = *c1 = 1;	break;
+	case CRONYX_401:	*c0 = 1;	break;
+	case CRONYX_801:	*c0 = *c1 = 1;	break;
+	case CRONYX_401s:	*c0 = 1;	break;
+	case CRONYX_801s:	*c0 = *c1 = 1;	break;
+	case CRONYX_404:	*c0 = 1;	break;
+	case CRONYX_703:	*c0 = *c1 = 1;	break;
+	default:		return (0);	/* invalid variant code */
+	}
+
+	switch (rev & BSR_OSC_MASK) {
+	case BSR_OSC_20:	/* 20 MHz */
+	case BSR_OSC_18432:	/* 18.432 MHz */
+		break;
+	default:
+		return (0);	/* oscillator frequency does not match */
+	}
+
+	for (i=2; i<0x10; i+=2)
+		if ((inb (BSR(port)+i) & BSR_REV_MASK) != (rev & BSR_REV_MASK))
+			return (0);	/* status changed? */
+	return (1);
+}
+
+/*
+ * Check if the Sigma-800 board is present at the given base port.
+ * Read board status register 1 and check identification bits
+ * which should invert every next read.
+ */
+static int cx_probe_800_chained_board (port_t port)
+{
+	unsigned char det, odet;
+	int i;
+
+	odet = inb (BDET(port));
+	if ((odet & (BDET_IB | BDET_IB_NEG)) != BDET_IB &&
+	    (odet & (BDET_IB | BDET_IB_NEG)) != BDET_IB_NEG)
+		return (0);
+	for (i=0; i<100; ++i) {
+		det = inb (BDET(port));
+		if (((det ^ odet) & (BDET_IB | BDET_IB_NEG)) !=
+		    (BDET_IB | BDET_IB_NEG))
+			return (0);
+		odet = det;
+	}
+	/* Reset the controller. */
+	outb (BCR0(port), 0);
+	outb (BCR1(port), 0);
+	outb (BCR2(port), 0);
+	return (1);
+}
+
+/*
+ * Check if the Sigma-2x board is present at the given base port.
+ */
+static int cx_probe_2x_board (port_t port)
+{
+	int rev, i;
+
+	/* Read and check the board revision code. */
+	rev = inb (BSR(port));
+	if ((rev & BSR2X_VAR_MASK) != CRONYX_22 &&
+	    (rev & BSR2X_VAR_MASK) != CRONYX_24)
+		return (0);		/* invalid variant code */
+
+	for (i=2; i<0x10; i+=2)
+		if ((inb (BSR(port)+i) & BSR2X_REV_MASK) !=
+		    (rev & BSR2X_REV_MASK))
+			return (0);	/* status changed? */
+	return (1);
+}
+
+/*
+ * Check if the Cronyx-Sigma board is present at the given base port.
+ */
+int cx_probe_board (port_t port, int irq, int dma)
+{
+	int c0, c1, c2=0, c3=0, result;
+
+	if (! valid (port, porttab))
+		return 0;
+
+	if (irq > 0 && ! valid (irq, irqtab))
+		return 0;
+
+	if (dma > 0 && ! valid (dma, dmatab))
+		return 0;
+
+	if (cx_probe_800_chained_board (port)) {
+		/* Sigma-800 detected. */
+		if (! (inb (BSR(port)) & BSR_NOCHAIN)) {
+			/* chained board attached */
+			if (! cx_probe_800_chained_board (port+0x10))
+				/* invalid chained board? */
+				return (0);
+			if (! (inb (BSR(port+0x10)) & BSR_NOCHAIN))
+				/* invalid chained board flag? */
+				return (0);
+		}
+		return 1;
+	}
+	if (cx_probe_chained_board (port, &c0, &c1)) {
+		/* Sigma-XXX detected. */
+		if (! (inb (BSR(port)) & BSR_NOCHAIN)) {
+			/* chained board attached */
+			if (! cx_probe_chained_board (port+0x10, &c2, &c3))
+				/* invalid chained board? */
+				return (0);
+			if (! (inb (BSR(port+0x10)) & BSR_NOCHAIN))
+				/* invalid chained board flag? */
+				return (0);
+		}
+	} else if (cx_probe_2x_board (port)) {
+		c0 = 1;		/* Sigma-2x detected. */
+		c1 = 0;
+	} else
+		return (0);     /* no board detected */
+
+	/* Turn off the reset bit. */
+	outb (BCR0(port), BCR0_NORESET);
+	if (c2 || c3)
+		outb (BCR0(port + 0x10), BCR0_NORESET);
+
+	result = 1;
+	if (c0 && ! cx_probe_chip (CS0(port)))
+		result = 0;	/* no CD2400 chip here */
+	else if (c1 && ! cx_probe_chip (CS1A(port)) &&
+	    ! cx_probe_chip (CS1(port)))
+		result = 0;	/* no second CD2400 chip */
+	else if (c2 && ! cx_probe_chip (CS0(port + 0x10)))
+		result = 0;	/* no CD2400 chip on the slave board */
+	else if (c3 && ! cx_probe_chip (CS1(port + 0x10)))
+		result = 0;	/* no second CD2400 chip on the slave board */
+
+	/* Reset the controller. */
+	outb (BCR0(port), 0);
+	if (c2 || c3)
+		outb (BCR0(port + 0x10), 0);
+
+	/* Yes, we really have valid Sigma board. */
+	return (result);
+}
+
+/*
+ * Check if the CD2400 chip is present at the given base port.
+ */
+static int cx_probe_chip (port_t base)
+{
+	int rev, newrev, count;
+
+	/* Wait up to 10 msec for revision code to appear after reset. */
+	rev = 0;
+	for (count=0; rev==0; ++count) {
+		if (count >= 20000)
+			return (0); /* reset failed */
+		rev = inb (GFRCR(base));
+	}
+
+	/* Read and check the global firmware revision code. */
+	if (! (rev>=REVCL_MIN && rev<=REVCL_MAX) &&
+	    ! (rev>=REVCL31_MIN && rev<=REVCL31_MAX))
+		return (0);	/* CD2400/2431 revision does not match */
+
+	/* Reset the chip. */
+	if (! cx_reset (base))
+		return (0);
+
+	/* Read and check the new global firmware revision code. */
+	newrev = inb (GFRCR(base));
+	if (newrev != rev)
+		return (0);	/* revision changed */
+
+	/* Yes, we really have CD2400/2431 chip here. */
+	return (1);
+}
+
+/*
+ * Check that the irq is functional.
+ * irq>0  - activate the interrupt from the adapter (irq=on)
+ * irq<0  - deactivate the interrupt (irq=off)
+ * irq==0 - free the interrupt line (irq=tri-state)
+ * Return the interrupt mask _before_ activating irq.
+ */
+int cx_probe_irq (cx_board_t *b, int irq)
+{
+	int mask, rev;
+        port_t port;
+
+	rev = inb (BSR(b->port));
+        port = ((rev & BSR_VAR_MASK) != CRONYX_400) ? CS0(b->port) : CS1(b->port);
+
+	outb (0x20, 0x0a);
+	mask = inb (0x20);
+	outb (0xa0, 0x0a);
+	mask |= inb (0xa0) << 8;
+
+	if (irq > 0) {
+		outb (BCR0(b->port), BCR0_NORESET | irqmask[irq]);
+		outb (CAR(port), 0);
+		cx_cmd (port, CCR_CLRCH);
+		outb (CMR(port), CMR_HDLC);
+		outb (TCOR(port), 0);
+		outb (TBPR(port), 1);
+		cx_cmd (port, CCR_INITCH | CCR_ENTX);
+		outb (IER(port), IER_TXMPTY);
+	} else if (irq < 0) {
+		cx_reset (port);
+		if (-irq > 7) {
+			outb (0xa0, 0x60 | ((-irq) & 7));
+			outb (0x20, 0x62);
+		} else
+			outb (0x20, 0x60 | (-irq));
+	} else
+		outb (BCR0(b->port), 0);
+	return mask;
+}
+
+static int cx_chip_revision (port_t port, int rev)
+{
+	int count;
+
+	/* Model 400 has no first chip. */
+	port = ((rev & BSR_VAR_MASK) != CRONYX_400) ? CS0(port) : CS1(port);
+
+	/* Wait up to 10 msec for revision code to appear after reset. */
+	for (count=0; inb(GFRCR(port))==0; ++count)
+		if (count >= 20000)
+			return (0); /* reset failed */
+
+	return inb (GFRCR (port));
+}
+
+/*
+ * Probe and initialize the board structure.
+ */
+void cx_init (cx_board_t *b, int num, port_t port, int irq, int dma)
+{
+	int gfrcr, rev, chain, mod = 0, rev2 = 0, mod2 = 0;
+
+	rev = inb (BSR(port));
+	chain = ! (rev & BSR_NOCHAIN);
+	if (cx_probe_800_chained_board (port)) {
+		cx_init_800 (b, num, port, irq, dma, chain);
+		return;
+	}
+	if ((rev & BSR2X_VAR_MASK) == CRONYX_22 ||
+	    (rev & BSR2X_VAR_MASK) == CRONYX_24) {
+		cx_init_2x (b, num, port, irq, dma,
+			(rev & BSR2X_VAR_MASK), (rev & BSR2X_OSC_33));
+		return;
+        }
+
+	outb (BCR0(port), BCR0_NORESET);
+	if (chain)
+		outb (BCR0(port+0x10), BCR0_NORESET);
+	gfrcr = cx_chip_revision (port, rev);
+	if (gfrcr >= REVCL31_MIN && gfrcr <= REVCL31_MAX)
+		mod = 1;
+	if (chain) {
+		rev2 = inb (BSR(port+0x10));
+		gfrcr = cx_chip_revision (port+0x10, rev2);
+		if (gfrcr >= REVCL31_MIN && gfrcr <= REVCL31_MAX)
+			mod2 = 1;
+		outb (BCR0(port+0x10), 0);
+	}
+	outb (BCR0(port), 0);
+
+	cx_init_board (b, num, port, irq, dma, chain,
+		(rev & BSR_VAR_MASK), (rev & BSR_OSC_MASK), mod,
+		(rev2 & BSR_VAR_MASK), (rev2 & BSR_OSC_MASK), mod2);
+}
+
+/*
+ * Initialize the board structure, given the type of the board.
+ */
+void cx_init_board (cx_board_t *b, int num, port_t port, int irq, int dma,
+	int chain, int rev, int osc, int mod, int rev2, int osc2, int mod2)
+{
+	cx_chan_t *c;
+	char *type;
+	int i;
+
+	/* Initialize board structure. */
+	b->port = port;
+	b->num = num;
+	b->irq = irq;
+	b->dma = dma;
+	b->opt = board_opt_dflt;
+
+	b->type = B_SIGMA_XXX;
+	b->if0type = b->if8type = cx_iftype;
+
+	/* Set channels 0 and 8 mode, set DMA and IRQ. */
+	b->bcr0 = b->bcr0b = BCR0_NORESET | dmamask[b->dma] | irqmask[b->irq];
+
+	/* Clear DTR[0..3] and DTR[8..12]. */
+	b->bcr1 = b->bcr1b = 0;
+
+	/*------------------ Master board -------------------*/
+
+	/* Read and check the board revision code. */
+	strcpy (b->name, mod ? "m" : "");
+	switch (rev) {
+	default:	  type = "";	 break;
+	case CRONYX_100:  type = "100";  break;
+	case CRONYX_400:  type = "400";  break;
+	case CRONYX_500:  type = "500";  break;
+	case CRONYX_410:  type = "410";  break;
+	case CRONYX_810:  type = "810";  break;
+	case CRONYX_410s: type = "410s"; break;
+	case CRONYX_810s: type = "810s"; break;
+	case CRONYX_440:  type = "440";  break;
+	case CRONYX_840:  type = "840";  break;
+	case CRONYX_401:  type = "401";  break;
+	case CRONYX_801:  type = "801";  break;
+	case CRONYX_401s: type = "401s"; break;
+	case CRONYX_801s: type = "801s"; break;
+	case CRONYX_404:  type = "404";  break;
+	case CRONYX_703:  type = "703";  break;
+	}
+	strcat (b->name, type);
+
+	switch (osc) {
+	default:
+	case BSR_OSC_20: /* 20 MHz */
+		b->chan[0].oscfreq = b->chan[1].oscfreq =
+		b->chan[2].oscfreq = b->chan[3].oscfreq =
+		b->chan[4].oscfreq = b->chan[5].oscfreq =
+		b->chan[6].oscfreq = b->chan[7].oscfreq =
+			mod ? 33000000L : 20000000L;
+		strcat (b->name, "a");
+		break;
+	case BSR_OSC_18432: /* 18.432 MHz */
+		b->chan[0].oscfreq = b->chan[1].oscfreq =
+		b->chan[2].oscfreq = b->chan[3].oscfreq =
+		b->chan[4].oscfreq = b->chan[5].oscfreq =
+		b->chan[6].oscfreq = b->chan[7].oscfreq =
+			mod ? 20000000L : 18432000L;
+		strcat (b->name, "b");
+		break;
+	}
+
+	/*------------------ Slave board -------------------*/
+
+	if (chain) {
+		/* Read and check the board revision code. */
+		strcat (b->name, mod2 ? "/m" : "/");
+		switch (rev2) {
+		default:	  type = "";	 break;
+		case CRONYX_100:  type = "100";  break;
+		case CRONYX_400:  type = "400";  break;
+		case CRONYX_500:  type = "500";  break;
+		case CRONYX_410:  type = "410";  break;
+		case CRONYX_810:  type = "810";  break;
+		case CRONYX_410s: type = "410s"; break;
+		case CRONYX_810s: type = "810s"; break;
+		case CRONYX_440:  type = "440";  break;
+		case CRONYX_840:  type = "840";  break;
+		case CRONYX_401:  type = "401";  break;
+		case CRONYX_801:  type = "801";  break;
+		case CRONYX_401s: type = "401s"; break;
+		case CRONYX_801s: type = "801s"; break;
+		case CRONYX_404:  type = "404";  break;
+		case CRONYX_703:  type = "703";  break;
+		}
+		strcat (b->name, type);
+
+		switch (osc2) {
+		default:
+		case BSR_OSC_20: /* 20 MHz */
+			b->chan[8].oscfreq = b->chan[9].oscfreq =
+			b->chan[10].oscfreq = b->chan[11].oscfreq =
+			b->chan[12].oscfreq = b->chan[13].oscfreq =
+			b->chan[14].oscfreq = b->chan[15].oscfreq =
+				mod2 ? 33000000L : 20000000L;
+			strcat (b->name, "a");
+			break;
+		case BSR_OSC_18432: /* 18.432 MHz */
+			b->chan[8].oscfreq = b->chan[9].oscfreq =
+			b->chan[10].oscfreq = b->chan[11].oscfreq =
+			b->chan[12].oscfreq = b->chan[13].oscfreq =
+			b->chan[14].oscfreq = b->chan[15].oscfreq =
+				mod2 ? 20000000L : 18432000L;
+			strcat (b->name, "b");
+			break;
+		}
+	}
+
+	/* Initialize channel structures. */
+	for (i=0; i<4; ++i) {
+		b->chan[i+0].port  = CS0(port);
+		b->chan[i+4].port  = cx_probe_chip (CS1A(port)) ?
+			CS1A(port) : CS1(port);
+		b->chan[i+8].port  = CS0(port+0x10);
+		b->chan[i+12].port = CS1(port+0x10);
+	}
+	for (c=b->chan; c<b->chan+NCHAN; ++c) {
+		c->board = b;
+		c->num = c - b->chan;
+		c->type = T_NONE;
+	}
+
+	/*------------------ Master board -------------------*/
+
+	switch (rev) {
+	case CRONYX_400:
+		for (i=4; i<8; ++i)
+			b->chan[i].type = T_UNIV_RS232;
+		break;
+	case CRONYX_100:
+		b->chan[0].type = T_UNIV_RS232;
+		break;
+	case CRONYX_500:
+		b->chan[0].type = T_UNIV_RS232;
+		for (i=4; i<8; ++i)
+			b->chan[i].type = T_UNIV_RS232;
+		break;
+	case CRONYX_410:
+		b->chan[0].type = T_UNIV_V35;
+		for (i=1; i<4; ++i)
+			b->chan[i].type = T_UNIV_RS232;
+		break;
+	case CRONYX_810:
+		b->chan[0].type = T_UNIV_V35;
+		for (i=1; i<8; ++i)
+			b->chan[i].type = T_UNIV_RS232;
+		break;
+	case CRONYX_410s:
+		b->chan[0].type = T_UNIV_V35;
+		for (i=1; i<4; ++i)
+			b->chan[i].type = T_SYNC_RS232;
+		break;
+	case CRONYX_810s:
+		b->chan[0].type = T_UNIV_V35;
+		for (i=1; i<4; ++i)
+			b->chan[i].type = T_SYNC_RS232;
+		for (i=4; i<8; ++i)
+			b->chan[i].type = T_UNIV_RS232;
+		break;
+	case CRONYX_440:
+		b->chan[0].type = T_UNIV_V35;
+		for (i=1; i<4; ++i)
+			b->chan[i].type = T_SYNC_V35;
+		break;
+	case CRONYX_840:
+		b->chan[0].type = T_UNIV_V35;
+		for (i=1; i<4; ++i)
+			b->chan[i].type = T_SYNC_V35;
+		for (i=4; i<8; ++i)
+			b->chan[i].type = T_UNIV_RS232;
+		break;
+	case CRONYX_401:
+		b->chan[0].type = T_UNIV_RS449;
+		for (i=1; i<4; ++i)
+			b->chan[i].type = T_UNIV_RS232;
+		break;
+	case CRONYX_801:
+		b->chan[0].type = T_UNIV_RS449;
+		for (i=1; i<8; ++i)
+			b->chan[i].type = T_UNIV_RS232;
+		break;
+	case CRONYX_401s:
+		b->chan[0].type = T_UNIV_RS449;
+		for (i=1; i<4; ++i)
+			b->chan[i].type = T_SYNC_RS232;
+		break;
+	case CRONYX_801s:
+		b->chan[0].type = T_UNIV_RS449;
+		for (i=1; i<4; ++i)
+			b->chan[i].type = T_SYNC_RS232;
+		for (i=4; i<8; ++i)
+			b->chan[i].type = T_UNIV_RS232;
+		break;
+	case CRONYX_404:
+		b->chan[0].type = T_UNIV_RS449;
+		for (i=1; i<4; ++i)
+			b->chan[i].type = T_SYNC_RS449;
+		break;
+	case CRONYX_703:
+		b->chan[0].type = T_UNIV_RS449;
+		for (i=1; i<3; ++i)
+			b->chan[i].type = T_SYNC_RS449;
+		for (i=4; i<8; ++i)
+			b->chan[i].type = T_UNIV_RS232;
+		break;
+	}
+
+	/*------------------ Slave board -------------------*/
+
+	if (chain) {
+		switch (rev2) {
+		case CRONYX_400:
+			break;
+		case CRONYX_100:
+			b->chan[8].type = T_UNIV_RS232;
+			break;
+		case CRONYX_500:
+			b->chan[8].type = T_UNIV_RS232;
+			for (i=12; i<16; ++i)
+				b->chan[i].type = T_UNIV_RS232;
+			break;
+		case CRONYX_410:
+			b->chan[8].type = T_UNIV_V35;
+			for (i=9; i<12; ++i)
+				b->chan[i].type = T_UNIV_RS232;
+			break;
+		case CRONYX_810:
+			b->chan[8].type = T_UNIV_V35;
+			for (i=9; i<16; ++i)
+				b->chan[i].type = T_UNIV_RS232;
+			break;
+		case CRONYX_410s:
+			b->chan[8].type = T_UNIV_V35;
+			for (i=9; i<12; ++i)
+				b->chan[i].type = T_SYNC_RS232;
+			break;
+		case CRONYX_810s:
+			b->chan[8].type = T_UNIV_V35;
+			for (i=9; i<12; ++i)
+				b->chan[i].type = T_SYNC_RS232;
+			for (i=12; i<16; ++i)
+				b->chan[i].type = T_UNIV_RS232;
+			break;
+		case CRONYX_440:
+			b->chan[8].type = T_UNIV_V35;
+			for (i=9; i<12; ++i)
+				b->chan[i].type = T_SYNC_V35;
+			break;
+		case CRONYX_840:
+			b->chan[8].type = T_UNIV_V35;
+			for (i=9; i<12; ++i)
+				b->chan[i].type = T_SYNC_V35;
+			for (i=12; i<16; ++i)
+				b->chan[i].type = T_UNIV_RS232;
+			break;
+		case CRONYX_401:
+			b->chan[8].type = T_UNIV_RS449;
+			for (i=9; i<12; ++i)
+				b->chan[i].type = T_UNIV_RS232;
+			break;
+		case CRONYX_801:
+			b->chan[8].type = T_UNIV_RS449;
+			for (i=9; i<16; ++i)
+				b->chan[i].type = T_UNIV_RS232;
+			break;
+		case CRONYX_401s:
+			b->chan[8].type = T_UNIV_RS449;
+			for (i=9; i<12; ++i)
+				b->chan[i].type = T_UNIV_RS232;
+			break;
+		case CRONYX_801s:
+			b->chan[8].type = T_UNIV_RS449;
+			for (i=9; i<12; ++i)
+				b->chan[i].type = T_SYNC_RS232;
+			for (i=12; i<16; ++i)
+				b->chan[i].type = T_UNIV_RS232;
+			break;
+		case CRONYX_404:
+			b->chan[8].type = T_UNIV_RS449;
+			for (i=9; i<12; ++i)
+				b->chan[i].type = T_SYNC_RS449;
+			break;
+		case CRONYX_703:
+			b->chan[8].type = T_UNIV_RS449;
+			for (i=9; i<11; ++i)
+				b->chan[i].type = T_SYNC_RS449;
+			for (i=12; i<16; ++i)
+				b->chan[i].type = T_UNIV_RS232;
+			break;
+		}
+	}
+
+	b->nuniv = b->nsync = b->nasync = 0;
+	for (c=b->chan; c<b->chan+NCHAN; ++c)
+		switch (c->type) {
+		case T_ASYNC:      ++b->nasync; break;
+		case T_UNIV:
+		case T_UNIV_RS232:
+		case T_UNIV_RS449:
+		case T_UNIV_V35:   ++b->nuniv;  break;
+		case T_SYNC_RS232:
+		case T_SYNC_V35:
+		case T_SYNC_RS449: ++b->nsync;  break;
+		}
+
+	cx_reinit_board (b);
+}
+
+/*
+ * Initialize the Sigma-800 board structure.
+ */
+void cx_init_800 (cx_board_t *b, int num, port_t port, int irq, int dma,
+	int chain)
+{
+	cx_chan_t *c;
+	int i;
+
+	/* Initialize board structure. */
+	b->port = port;
+	b->num = num;
+	b->irq = irq;
+	b->dma = dma;
+	b->opt = board_opt_dflt;
+	b->type = B_SIGMA_800;
+
+	/* Set channels 0 and 8 mode, set DMA and IRQ. */
+	b->bcr0 = b->bcr0b = dmamask[b->dma] | irqmask[b->irq];
+
+	/* Clear DTR[0..7] and DTR[8..15]. */
+	b->bcr1 = b->bcr1b = 0;
+
+	strcpy (b->name, "800");
+	if (chain)
+		strcat (b->name, "/800");
+
+	/* Initialize channel structures. */
+	for (i=0; i<4; ++i) {
+		b->chan[i+0].port  = CS0(port);
+		b->chan[i+4].port  = cx_probe_chip (CS1A(port)) ?
+			CS1A(port) : CS1(port);
+		b->chan[i+8].port  = CS0(port+0x10);
+		b->chan[i+12].port = CS1(port+0x10);
+	}
+	for (c=b->chan; c<b->chan+NCHAN; ++c) {
+		c->board = b;
+		c->num = c - b->chan;
+		c->oscfreq = 33000000L;
+		c->type = (c->num < 8 || chain) ? T_UNIV_RS232 : T_NONE;
+	}
+
+	b->nuniv = b->nsync = b->nasync = 0;
+	for (c=b->chan; c<b->chan+NCHAN; ++c)
+		switch (c->type) {
+		case T_ASYNC:      ++b->nasync; break;
+		case T_UNIV:
+		case T_UNIV_RS232:
+		case T_UNIV_RS449:
+		case T_UNIV_V35:   ++b->nuniv;  break;
+		case T_SYNC_RS232:
+		case T_SYNC_V35:
+		case T_SYNC_RS449: ++b->nsync;  break;
+		}
+
+	cx_reinit_board (b);
+}
+
+/*
+ * Initialize the Sigma-2x board structure.
+ */
+void cx_init_2x (cx_board_t *b, int num, port_t port, int irq, int dma,
+	int rev, int osc)
+{
+	cx_chan_t *c;
+	int i;
+
+	/* Initialize board structure. */
+	b->port = port;
+	b->num = num;
+	b->irq = irq;
+	b->dma = dma;
+	b->opt = board_opt_dflt;
+
+	b->type = B_SIGMA_2X;
+
+	/* Set channels 0 and 8 mode, set DMA and IRQ. */
+	b->bcr0 = BCR0_NORESET | dmamask[b->dma] | irqmask[b->irq];
+	if (b->type == B_SIGMA_2X && b->opt.fast)
+		b->bcr0 |= BCR02X_FAST;
+
+	/* Clear DTR[0..3] and DTR[8..12]. */
+	b->bcr1 = 0;
+
+	/* Initialize channel structures. */
+	for (i=0; i<4; ++i) {
+		b->chan[i+0].port  = CS0(port);
+		b->chan[i+4].port  = CS1(port);
+		b->chan[i+8].port  = CS0(port+0x10);
+		b->chan[i+12].port = CS1(port+0x10);
+	}
+	for (c=b->chan; c<b->chan+NCHAN; ++c) {
+		c->board = b;
+		c->num = c - b->chan;
+		c->type = T_NONE;
+		c->oscfreq = (osc & BSR2X_OSC_33) ? 33000000L : 20000000L;
+	}
+
+	/* Check the board revision code. */
+	strcpy (b->name, "22");
+	b->chan[0].type = T_UNIV;
+	b->chan[1].type = T_UNIV;
+	b->nsync = b->nasync = 0;
+	b->nuniv = 2;
+	if (rev == CRONYX_24) {
+		strcpy (b->name, "24");
+		b->chan[2].type = T_UNIV;
+		b->chan[3].type = T_UNIV;
+		b->nuniv += 2;
+	}
+	strcat (b->name, (osc & BSR2X_OSC_33) ? "c" : "a");
+	cx_reinit_board (b);
+}
+
+/*
+ * Reinitialize all channels, using new options and baud rate.
+ */
+void cx_reinit_board (cx_board_t *b)
+{
+	cx_chan_t *c;
+
+	b->opt = board_opt_dflt;
+	if (b->type == B_SIGMA_2X) {
+		b->bcr0 &= ~BCR02X_FAST;
+		if (b->opt.fast)
+			b->bcr0 |= BCR02X_FAST;
+	} else
+		b->if0type = b->if8type = cx_iftype;
+	for (c=b->chan; c<b->chan+NCHAN; ++c) {
+		switch (c->type) {
+		default:
+		case T_NONE:
+			continue;
+		case T_UNIV:
+		case T_UNIV_RS232:
+		case T_UNIV_RS449:
+		case T_UNIV_V35:
+			c->mode = (cx_univ_mode == M_ASYNC) ?
+				M_ASYNC : cx_sync_mode;
+			break;
+		case T_SYNC_RS232:
+		case T_SYNC_V35:
+		case T_SYNC_RS449:
+			c->mode = cx_sync_mode;
+			break;
+		case T_ASYNC:
+			c->mode = M_ASYNC;
+			break;
+		}
+		c->rxbaud = cx_rxbaud;
+		c->txbaud = cx_txbaud;
+		c->opt = chan_opt_dflt;
+		c->aopt = opt_async_dflt;
+		c->hopt = opt_hdlc_dflt;
+	}
+}
+
+/*
+ * Set up the board.
+ */
+int cx_setup_board (cx_board_t *b, const unsigned char *firmware,
+	long bits, const cr_dat_tst_t *tst)
+{
+	int i;
+#ifndef NDIS_MINIPORT_DRIVER
+	/* Disable DMA channel. */
+	outb (DMA_MASK, (b->dma & 3) | DMA_MASK_CLEAR);
+#endif
+	/* Reset the controller. */
+	outb (BCR0(b->port), 0);
+	if (b->chan[8].type || b->chan[12].type)
+		outb (BCR0(b->port+0x10), 0);
+
+	/* Load the firmware. */
+	if (b->type == B_SIGMA_800) {
+		/* Reset the controllers. */
+		outb (BCR2(b->port), BCR2_TMS);
+		if (b->chan[8].type || b->chan[12].type)
+			outb (BCR2(b->port+0x10), BCR2_TMS);
+		outb (BCR2(b->port), 0);
+		if (b->chan[8].type || b->chan[12].type)
+			outb (BCR2(b->port+0x10), 0);
+
+		if (firmware &&
+		    (! cx_download (b->port, firmware, bits, tst) ||
+		    ((b->chan[8].type || b->chan[12].type) &&
+		    ! cx_download (b->port+0x10, firmware, bits, tst))))
+			return (0);
+	}
+
+	/*
+	 * Set channels 0 and 8 to RS232 async. mode.
+	 * Enable DMA and IRQ.
+	 */
+	outb (BCR0(b->port), b->bcr0);
+	if (b->chan[8].type || b->chan[12].type)
+		outb (BCR0(b->port+0x10), b->bcr0b);
+
+	/* Clear DTR[0..3] and DTR[8..12]. */
+	outw (BCR1(b->port), b->bcr1);
+	if (b->chan[8].type || b->chan[12].type)
+		outw (BCR1(b->port+0x10), b->bcr1b);
+
+	if (b->type == B_SIGMA_800)
+		outb (BCR2(b->port), b->opt.fast &
+			(BCR2_BUS0 | BCR2_BUS1));
+
+	/* Initialize all controllers. */
+	for (i=0; i<NCHAN; i+=4)
+		if (b->chan[i].type != T_NONE)
+			cx_setup_chip (b->chan + i);
+#ifndef NDIS_MINIPORT_DRIVER
+	/* Set up DMA channel to master mode. */
+	outb (DMA_MODE, (b->dma & 3) | DMA_MODE_MASTER);
+
+	/* Enable DMA channel. */
+	outb (DMA_MASK, b->dma & 3);
+#endif
+	/* Initialize all channels. */
+	for (i=0; i<NCHAN; ++i)
+		if (b->chan[i].type != T_NONE)
+			cx_setup_chan (b->chan + i);
+	return (1);
+}
+
+/*
+ * Initialize the board.
+ */
+static void cx_setup_chip (cx_chan_t *c)
+{
+	/* Reset the chip. */
+	cx_reset (c->port);
+
+	/*
+	 * Set all interrupt level registers to the same value.
+	 * This enables the internal CD2400 priority scheme.
+	 */
+	outb (RPILR(c->port), BRD_INTR_LEVEL);
+	outb (TPILR(c->port), BRD_INTR_LEVEL);
+	outb (MPILR(c->port), BRD_INTR_LEVEL);
+
+	/* Set bus error count to zero. */
+	outb (BERCNT(c->port), 0);
+
+	/* Set 16-bit DMA mode. */
+	outb (DMR(c->port), 0);
+
+	/* Set timer period register to 1 msec (approximately). */
+	outb (TPR(c->port), 10);
+}
+
+/*
+ * Initialize the CD2400 channel.
+ */
+void cx_update_chan (cx_chan_t *c)
+{
+	int clock, period;
+
+	if (c->board->type == B_SIGMA_XXX)
+		switch (c->num) {
+		case 0:
+			c->board->bcr0 &= ~BCR0_UMASK;
+			if (c->mode != M_ASYNC)
+				c->board->bcr0 |= BCR0_UM_SYNC;
+			if (c->board->if0type &&
+			    (c->type==T_UNIV_RS449 || c->type==T_UNIV_V35))
+				c->board->bcr0 |= BCR0_UI_RS449;
+			outb (BCR0(c->board->port), c->board->bcr0);
+			break;
+		case 8:
+			c->board->bcr0b &= ~BCR0_UMASK;
+			if (c->mode != M_ASYNC)
+				c->board->bcr0b |= BCR0_UM_SYNC;
+			if (c->board->if8type &&
+			    (c->type==T_UNIV_RS449 || c->type==T_UNIV_V35))
+				c->board->bcr0b |= BCR0_UI_RS449;
+			outb (BCR0(c->board->port+0x10), c->board->bcr0b);
+			break;
+		}
+
+	/* set current channel number */
+	outb (CAR(c->port), c->num & 3);
+
+	switch (c->mode) {	/* initialize the channel mode */
+	case M_ASYNC:
+		/* set receiver timeout register */
+		outw (RTPR(c->port), 10);          /* 10 msec, see TPR */
+		c->opt.rcor.encod = ENCOD_NRZ;
+
+		outb (CMR(c->port), CMR_RXDMA | CMR_TXDMA | CMR_ASYNC);
+		outb (COR1(c->port), BYTE c->aopt.cor1);
+		outb (COR2(c->port), BYTE c->aopt.cor2);
+		outb (COR3(c->port), BYTE c->aopt.cor3);
+		outb (COR6(c->port), BYTE c->aopt.cor6);
+		outb (COR7(c->port), BYTE c->aopt.cor7);
+		outb (SCHR1(c->port), c->aopt.schr1);
+		outb (SCHR2(c->port), c->aopt.schr2);
+		outb (SCHR3(c->port), c->aopt.schr3);
+		outb (SCHR4(c->port), c->aopt.schr4);
+		outb (SCRL(c->port), c->aopt.scrl);
+		outb (SCRH(c->port), c->aopt.scrh);
+		outb (LNXT(c->port), c->aopt.lnxt);
+		break;
+	case M_HDLC:
+		outb (CMR(c->port), CMR_RXDMA | CMR_TXDMA | CMR_HDLC);
+		outb (COR1(c->port), BYTE c->hopt.cor1);
+		outb (COR2(c->port), BYTE c->hopt.cor2);
+		outb (COR3(c->port), BYTE c->hopt.cor3);
+		outb (RFAR1(c->port), c->hopt.rfar1);
+		outb (RFAR2(c->port), c->hopt.rfar2);
+		outb (RFAR3(c->port), c->hopt.rfar3);
+		outb (RFAR4(c->port), c->hopt.rfar4);
+		outb (CPSR(c->port), c->hopt.cpsr);
+		break;
+	}
+
+	/* set mode-independent options */
+	outb (COR4(c->port), BYTE c->opt.cor4);
+	outb (COR5(c->port), BYTE c->opt.cor5);
+
+	/* set up receiver clock values */
+	if (c->mode == M_ASYNC || c->opt.rcor.dpll || c->opt.tcor.llm) {
+		cx_clock (c->oscfreq, c->rxbaud, &clock, &period);
+		c->opt.rcor.clk = clock;
+	} else {
+		c->opt.rcor.clk = CLK_EXT;
+		period = 1;
+	}
+	outb (RCOR(c->port), BYTE c->opt.rcor);
+	outb (RBPR(c->port), period);
+
+	/* set up transmitter clock values */
+	if (c->mode == M_ASYNC || !c->opt.tcor.ext1x) {
+		unsigned ext1x = c->opt.tcor.ext1x;
+		c->opt.tcor.ext1x = 0;
+		cx_clock (c->oscfreq, c->txbaud, &clock, &period);
+		c->opt.tcor.clk = clock;
+		c->opt.tcor.ext1x = ext1x;
+	} else {
+		c->opt.tcor.clk = CLK_EXT;
+		period = 1;
+	}
+	outb (TCOR(c->port), BYTE c->opt.tcor);
+	outb (TBPR(c->port), period);
+}
+
+/*
+ * Initialize the CD2400 channel.
+ */
+void cx_setup_chan (cx_chan_t *c)
+{
+	/* set current channel number */
+	outb (CAR(c->port), c->num & 3);
+
+	/* reset the channel */
+	cx_cmd (c->port, CCR_CLRCH);
+
+	/* set LIVR to contain the board and channel numbers */
+	outb (LIVR(c->port), c->board->num << 6 | c->num << 2);
+
+	/* clear DTR, RTS, set TXCout/DTR pin */
+	outb (MSVR_RTS(c->port), 0);
+	outb (MSVR_DTR(c->port), c->mode==M_ASYNC ? 0 : MSV_TXCOUT);
+
+	/* set receiver A buffer physical address */
+	outw (ARBADRU(c->port), (unsigned short) (c->arphys>>16));
+	outw (ARBADRL(c->port), (unsigned short) c->arphys);
+
+	/* set receiver B buffer physical address */
+	outw (BRBADRU(c->port), (unsigned short) (c->brphys>>16));
+	outw (BRBADRL(c->port), (unsigned short) c->brphys);
+
+	/* set transmitter A buffer physical address */
+	outw (ATBADRU(c->port), (unsigned short) (c->atphys>>16));
+	outw (ATBADRL(c->port), (unsigned short) c->atphys);
+
+	/* set transmitter B buffer physical address */
+	outw (BTBADRU(c->port), (unsigned short) (c->btphys>>16));
+	outw (BTBADRL(c->port), (unsigned short) c->btphys);
+
+	c->dtr = 0;
+	c->rts = 0;
+
+	cx_update_chan (c);
+}
+
+/*
+ * Control DTR signal for the channel.
+ * Turn it on/off.
+ */
+void cx_set_dtr (cx_chan_t *c, int on)
+{
+	cx_board_t *b = c->board;
+
+	c->dtr = on ? 1 : 0;
+
+	if (b->type == B_SIGMA_2X) {
+		if (on) b->bcr1 |= BCR1_DTR(c->num);
+		else    b->bcr1 &= ~BCR1_DTR(c->num);
+		outw (BCR1(b->port), b->bcr1);
+		return;
+	}
+	if (b->type == B_SIGMA_800) {
+		if (c->num >= 8) {
+			if (on) b->bcr1b |= BCR1800_DTR(c->num);
+			else    b->bcr1b &= ~BCR1800_DTR(c->num);
+			outb (BCR1(b->port+0x10), b->bcr1b);
+		} else {
+			if (on) b->bcr1 |= BCR1800_DTR(c->num);
+			else    b->bcr1 &= ~BCR1800_DTR(c->num);
+			outb (BCR1(b->port), b->bcr1);
+		}
+		return;
+	}
+	if (c->mode == M_ASYNC) {
+		outb (CAR(c->port), c->num & 3);
+		outb (MSVR_DTR(c->port), on ? MSV_DTR : 0);
+		return;
+	}
+
+	switch (c->num) {
+	default:
+		/* Channels 4..7 and 12..15 in syncronous mode
+		 * have no DTR signal. */
+		break;
+
+	case 1: case 2:  case 3:
+		if (c->type == T_UNIV_RS232)
+			break;
+	case 0:
+		if (on) b->bcr1 |= BCR1_DTR(c->num);
+		else    b->bcr1 &= ~BCR1_DTR(c->num);
+		outw (BCR1(b->port), b->bcr1);
+		break;
+
+	case 9: case 10: case 11:
+		if (c->type == T_UNIV_RS232)
+			break;
+	case 8:
+		if (on) b->bcr1b |= BCR1_DTR(c->num & 3);
+		else    b->bcr1b &= ~BCR1_DTR(c->num & 3);
+		outw (BCR1(b->port+0x10), b->bcr1b);
+		break;
+	}
+}
+
+/*
+ * Control RTS signal for the channel.
+ * Turn it on/off.
+ */
+void cx_set_rts (cx_chan_t *c, int on)
+{
+	c->rts = on ? 1 : 0;
+	outb (CAR(c->port), c->num & 3);
+	outb (MSVR_RTS(c->port), on ? MSV_RTS : 0);
+}
+
+/*
+ * Get the state of DSR signal of the channel.
+ */
+int cx_get_dsr (cx_chan_t *c)
+{
+	unsigned char sigval;
+
+	if (c->board->type == B_SIGMA_2X ||
+	    c->board->type == B_SIGMA_800 ||
+	    c->mode == M_ASYNC) {
+		outb (CAR(c->port), c->num & 3);
+		return (inb (MSVR(c->port)) & MSV_DSR ? 1 : 0);
+	}
+
+	/*
+	 * Channels 4..7 and 12..15 don't have DSR signal available.
+	 */
+	switch (c->num) {
+	default:
+		return (1);
+
+	case 1: case 2:  case 3:
+		if (c->type == T_UNIV_RS232)
+			return (1);
+	case 0:
+		sigval = inw (BSR(c->board->port)) >> 8;
+		break;
+
+	case 9: case 10: case 11:
+		if (c->type == T_UNIV_RS232)
+			return (1);
+	case 8:
+		sigval = inw (BSR(c->board->port+0x10)) >> 8;
+		break;
+	}
+	return (~sigval >> (c->num & 3) & 1);
+}
+
+/*
+ * Get the state of CARRIER signal of the channel.
+ */
+int cx_get_cd (cx_chan_t *c)
+{
+	unsigned char sigval;
+
+	if (c->board->type == B_SIGMA_2X ||
+	    c->board->type == B_SIGMA_800 ||
+	    c->mode == M_ASYNC) {
+		outb (CAR(c->port), c->num & 3);
+		return (inb (MSVR(c->port)) & MSV_CD ? 1 : 0);
+	}
+
+	/*
+	 * Channels 4..7 and 12..15 don't have CD signal available.
+	 */
+	switch (c->num) {
+	default:
+		return (1);
+
+	case 1: case 2:  case 3:
+		if (c->type == T_UNIV_RS232)
+			return (1);
+	case 0:
+		sigval = inw (BSR(c->board->port)) >> 8;
+		break;
+
+	case 9: case 10: case 11:
+		if (c->type == T_UNIV_RS232)
+			return (1);
+	case 8:
+		sigval = inw (BSR(c->board->port+0x10)) >> 8;
+		break;
+	}
+	return (~sigval >> 4 >> (c->num & 3) & 1);
+}
+
+/*
+ * Get the state of CTS signal of the channel.
+ */
+int cx_get_cts (cx_chan_t *c)
+{
+	outb (CAR(c->port), c->num & 3);
+	return (inb (MSVR(c->port)) & MSV_CTS ? 1 : 0);
+}
+
+/*
+ * Compute CD2400 clock values.
+ */
+void cx_clock (long hz, long ba, int *clk, int *div)
+{
+	static short clocktab[] = { 8, 32, 128, 512, 2048, 0 };
+
+	for (*clk=0; clocktab[*clk]; ++*clk) {
+		long c = ba * clocktab[*clk];
+		if (hz <= c*256) {
+			*div = (2 * hz + c) / (2 * c) - 1;
+			return;
+		}
+	}
+	/* Incorrect baud rate.  Return some meaningful values. */
+	*clk = 0;
+	*div = 255;
+}
+
+/*
+ * Turn LED on/off.
+ */
+void cx_led (cx_board_t *b, int on)
+{
+	switch (b->type) {
+	case B_SIGMA_2X:
+		if (on) b->bcr0 |= BCR02X_LED;
+		else    b->bcr0 &= ~BCR02X_LED;
+		outb (BCR0(b->port), b->bcr0);
+		break;
+	}
+}
+
+void cx_disable_dma (cx_board_t *b)
+{
+#ifndef NDIS_MINIPORT_DRIVER
+	/* Disable DMA channel. */
+	outb (DMA_MASK, (b->dma & 3) | DMA_MASK_CLEAR);
+#endif
+}
+
+cx_board_opt_t board_opt_dflt = { /* board options */
+	BUS_NORMAL,		/* normal bus master timing */
+};
+
+cx_chan_opt_t chan_opt_dflt = { /* mode-independent options */
+	{			/* cor4 */
+		7,		/* FIFO threshold, odd is better */
+		0,
+		0,              /* don't detect 1 to 0 on CTS */
+		1,		/* detect 1 to 0 on CD */
+		0,              /* detect 1 to 0 on DSR */
+	},
+	{			/* cor5 */
+		0,		/* receive flow control FIFO threshold */
+		0,
+		0,              /* don't detect 0 to 1 on CTS */
+		1,		/* detect 0 to 1 on CD */
+		0,              /* detect 0 to 1 on DSR */
+	},
+	{			/* rcor */
+		0,		/* dummy clock source */
+		ENCOD_NRZ,      /* NRZ mode */
+		0,              /* disable DPLL */
+		0,
+		0,		/* transmit line value */
+	},
+	{			/* tcor */
+		0,
+		0,		/* local loopback mode */
+		0,
+		1,		/* external 1x clock mode */
+		0,
+		0,		/* dummy transmit clock source */
+	},
+};
+
+cx_opt_async_t opt_async_dflt = { /* default async options */
+	{			/* cor1 */
+		8-1,		/* 8-bit char length */
+		0,		/* don't ignore parity */
+		PARM_NOPAR,	/* no parity */
+		PAR_EVEN,	/* even parity */
+	},
+	{			/* cor2 */
+		0,              /* disable automatic DSR */
+		1,              /* enable automatic CTS */
+		0,              /* disable automatic RTS */
+		0,		/* no remote loopback */
+		0,
+		0,              /* disable embedded cmds */
+		0,		/* disable XON/XOFF */
+		0,		/* disable XANY */
+	},
+	{			/* cor3 */
+		STOPB_1,	/* 1 stop bit */
+		0,
+		0,		/* disable special char detection */
+		FLOWCC_PASS,	/* pass flow ctl chars to the host */
+		0,		/* range detect disable */
+		0,		/* disable extended spec. char detect */
+	},
+	{			/* cor6 */
+		PERR_INTR,	/* generate exception on parity errors */
+		BRK_INTR,	/* generate exception on break condition */
+		0,		/* don't translate NL to CR on input */
+		0,		/* don't translate CR to NL on input */
+		0,		/* don't discard CR on input */
+	},
+	{			/* cor7 */
+		0,		/* don't translate CR to NL on output */
+		0,		/* don't translate NL to CR on output */
+		0,
+		0,		/* don't process flow ctl err chars */
+		0,		/* disable LNext option */
+		0,		/* don't strip 8 bit on input */
+	},
+	0, 0, 0, 0, 0, 0, 0,	/* clear schr1-4, scrl, scrh, lnxt */
+};
+
+cx_opt_hdlc_t opt_hdlc_dflt = { /* default hdlc options */
+	{			/* cor1 */
+		2,              /* 2 inter-frame flags */
+		0,		/* no-address mode */
+		CLRDET_DISABLE,	/* disable clear detect */
+		AFLO_1OCT,	/* 1-byte address field length */
+	},
+	{			/* cor2 */
+		0,		/* disable automatic DSR */
+		0,              /* disable automatic CTS */
+		0,              /* disable automatic RTS */
+		0,
+		CRC_INVERT,	/* use CRC V.41 */
+		0,
+		FCS_NOTPASS,	/* don't pass received CRC to the host */
+		0,
+	},
+	{			/* cor3 */
+		0,              /* 0 pad characters sent */
+		IDLE_FLAG,	/* idle in flag */
+		0,		/* enable FCS */
+		FCSP_ONES,	/* FCS preset to all ones (V.41) */
+		SYNC_AA,	/* use AAh as sync char */
+		0,              /* disable pad characters */
+	},
+	0, 0, 0, 0,		/* clear rfar1-4 */
+	POLY_V41,		/* use V.41 CRC polynomial */
+};
diff --git a/sys/dev/cx/csigmafw.h b/sys/dev/cx/csigmafw.h
new file mode 100644
index 0000000..a5e4e05
--- /dev/null
+++ b/sys/dev/cx/csigmafw.h
@@ -0,0 +1,852 @@
+/*
+ * DO NOT EDIT MANUALLY!
+ * This code was generated by mkfw utility
+ * from the file `csigma.dat'
+ *
+ * Cronyx Id: csigmafw.h,v 1.1 2002/06/03 10:19:39 rik Exp $
+ * $FreeBSD$
+ */
+long csigma_fw_len = 131234;
+
+const char *csigma_fw_version = "1.2";
+const char *csigma_fw_date = "06.06.00";
+const char *csigma_fw_copyright = "Copyright (C) 2000 Cronyx Engineering.";
+
+const cr_dat_tst_t csigma_fw_tvec[] = {
+	{ 65066, 66278}, { 66314, 67526}, { 67562, 68774}, { 68810, 70022}, 
+	{ 70058, 71270}, { 71306, 72518}, { 72554, 73766}, { 73802, 75014}, 
+	{ 75050, 76262}, { 76298, 77510}, { 77546, 78758}, { 78794, 80006}, 
+	{ 80042, 81254}, { 81290, 82502}, { 82538, 83750}, { 83786, 84998}, 
+	{ 85034, 86246}, { 86282, 87494}, { 87530, 88742}, { 88778, 89990}, 
+	{ 90026, 91238}, { 91274, 92486}, { 92522, 93734}, { 93770, 94982}, 
+	{ 95018, 96230}, { 96266, 97478}, { 97514, 98726}, { 98762, 99974}, 
+	{100010,101222}, {101258,102470}, {102506,103718}, {103754,104966}, 
+	{105002,106214}, {106250,107462}, {107498,108710}, {108746,109958}, 
+	{109994,111206}, {111242,112454}, {112490,113702}, {113738,114950}, 
+	{114986,116198}, {116234,117446}, {117482,118694}, {118730,119942}, 
+	{119978,121190}, {121226,122438}, {122474,123686}, {123722,124934}, 
+	{124970,126182}, {126218,127430}, {127466,128678}, {128714,129926}, 
+	{129962,131174}, {131234,131234}, 
+};
+
+const unsigned char csigma_fw_data[] = {
+	155,153,97,92,102,96,32,100,100,36,112,112,112,112,48,49,48,52,52,
+	52,100,100,100,116,117,36,100,100,52,52,52,52,116,100,49,49,36,37,
+	37,49,49,49,117,53,33,49,49,37,37,37,37,37,36,52,97,97,97,97,100,100,
+	100,97,101,96,100,36,53,96,97,97,36,97,97,112,112,96,101,100,100,100,
+	36,49,48,49,49,97,101,116,37,96,101,49,52,112,33,100,100,100,112,101,
+	116,49,97,36,37,52,100,101,116,36,49,100,52,33,49,49,49,100,53,100,
+	100,100,32,37,37,37,37,116,112,96,97,97,97,100,100,100,97,101,96,100,
+	100,97,97,113,36,33,97,97,112,112,112,48,49,49,113,53,59,57,49,100,
+	96,100,100,97,97,97,97,33,48,101,112,112,112,48,49,49,113,32,101,101,
+	100,36,112,112,112,112,97,96,100,48,52,52,100,100,100,52,96,113,49,
+	49,33,52,52,52,52,112,113,36,37,37,37,49,49,49,37,116,117,100,100,
+	117,32,37,37,49,116,37,97,97,33,53,49,49,49,113,37,97,100,100,33,53,
+	113,53,32,53,101,112,48,97,101,100,100,116,37,49,48,113,49,52,112,
+	48,53,49,48,100,48,113,36,100,100,100,112,97,36,100,100,52,52,52,52,
+	52,52,116,33,37,37,37,49,49,49,37,52,48,49,49,37,37,101,49,36,36,117,
+	97,97,97,97,100,100,100,49,76,68,100,48,33,49,49,49,37,37,37,37,96,
+	52,97,97,97,97,100,100,100,97,101,96,100,100,97,97,97,97,37,33,49,
+	97,112,112,48,49,49,113,112,49,48,49,113,112,112,112,112,96,96,49,
+	52,52,52,100,100,100,52,37,32,49,49,117,33,52,52,100,96,52,36,37,37,
+	116,100,100,100,100,48,33,49,49,49,116,100,117,32,116,52,97,97,36,
+	53,49,49,113,37,33,48,49,100,112,96,97,116,100,101,48,97,100,49,48,
+	49,49,97,116,113,101,100,100,36,112,112,112,96,37,37,52,52,52,100,
+	100,100,52,116,36,100,100,100,100,52,101,48,48,52,36,37,37,37,49,49,
+	49,53,16,177,177,112,116,100,100,52,52,52,100,52,32,113,36,37,37,37,
+	49,49,49,101,100,48,49,49,37,37,37,37,53,113,100,36,97,97,97,100,100,
+	100,49,49,100,100,100,97,97,97,97,33,53,101,112,112,112,48,49,49,113,
+	112,49,48,49,97,37,112,112,48,97,112,48,52,52,112,49,49,49,49,36,97,
+	100,100,52,112,49,117,33,112,113,36,37,116,32,49,49,49,116,48,33,49,
+	53,97,33,37,113,49,33,97,36,49,101,96,100,100,36,53,100,96,100,100,
+	97,97,97,97,33,53,52,112,112,112,48,49,49,113,116,112,101,100,36,112,
+	112,52,97,96,112,48,52,52,52,100,100,100,52,32,179,51,37,48,100,100,
+	100,36,112,112,112,32,100,49,52,52,52,100,100,100,52,96,37,100,100,
+	52,52,52,52,52,113,49,36,37,37,37,49,49,49,101,100,36,49,49,37,37,
+	37,37,37,116,52,97,97,97,97,100,100,100,97,101,96,100,36,53,96,97,
+	97,36,97,97,112,112,96,101,100,100,100,112,32,48,49,49,97,101,116,
+	37,96,101,49,52,100,52,100,100,100,48,36,49,49,97,36,37,52,100,48,
+	113,113,101,37,52,33,49,49,49,52,32,32,49,49,37,37,37,37,37,116,52,
+	97,97,97,97,100,100,100,97,101,96,100,100,100,100,113,36,33,97,97,
+	112,112,112,48,49,49,113,37,110,108,100,101,96,100,100,97,97,97,97,
+	33,48,101,112,112,112,48,49,49,113,112,49,48,49,113,112,112,112,112,
+	49,101,100,48,52,52,100,100,100,52,116,36,100,100,52,52,52,52,52,48,
+	112,36,37,37,37,49,49,49,37,96,100,100,100,117,32,37,37,49,36,112,
+	96,97,33,53,49,49,49,49,100,96,100,100,33,53,113,53,32,53,101,112,
+	96,117,101,100,100,116,37,49,48,49,100,49,112,48,53,49,48,100,48,113,
+	36,100,100,100,112,97,36,100,100,52,52,52,52,52,112,97,33,37,37,37,
+	49,49,49,101,101,101,100,100,32,37,101,49,36,36,37,97,97,97,97,100,
+	100,100,113,77,68,116,96,32,49,49,37,37,37,37,37,96,100,97,97,97,97,
+	100,100,100,113,49,48,49,49,49,96,97,97,101,52,49,97,112,112,48,49,
+	49,113,112,49,48,49,113,112,112,112,112,96,96,49,52,52,52,100,100,
+	100,52,116,36,100,100,112,33,52,52,100,48,52,36,37,37,116,100,100,
+	100,100,48,33,49,49,37,37,49,116,32,116,52,97,33,117,53,49,49,113,
+	101,97,48,49,53,101,96,97,116,100,96,112,116,96,49,48,49,49,97,113,
+	101,48,49,113,112,112,112,112,96,37,37,52,52,52,100,100,100,52,49,
+	49,100,100,52,52,100,96,37,112,97,33,37,37,37,49,49,49,53,21,177,177,
+	97,36,100,100,52,52,52,52,52,32,113,36,37,37,37,49,49,49,37,53,33,
+	49,49,37,37,37,37,53,113,100,36,100,97,97,100,100,100,113,48,97,100,
+	100,97,97,97,97,33,36,101,112,112,112,48,49,49,113,96,97,48,49,49,
+	113,112,112,48,97,112,48,52,52,112,49,49,49,49,32,37,100,100,52,112,
+	49,117,33,112,113,36,37,116,117,100,100,100,117,48,33,49,101,33,116,
+	32,113,101,116,52,37,49,101,96,100,100,36,53,100,96,100,100,97,97,
+	97,97,33,53,113,112,112,112,48,49,49,113,112,49,48,49,113,112,112,
+	52,97,96,112,48,52,52,52,100,100,100,52,52,230,102,53,96,101,100,36,
+	112,112,112,112,32,100,52,52,52,52,100,100,100,52,33,33,49,49,33,100,
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+	127,108,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,
+	100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,32,49,
+	49,97,117,101,100,100,100,100,100,100,52,52,52,52,52,100,100,100,32,
+	37,37,49,49,49,49,49,49,49,49,49,49,113,116,117,49,49,97,101,100,100,
+	117,100,100,100,100,100,100,100,52,36,53,49,116,100,100,100,32,49,
+	49,49,49,49,49,49,49,49,113,117,53,97,37,53,49,97,33,49,49,49,49,49,
+	49,49,49,49,49,49,97,101,100,100,100,100,100,100,100,100,100,100,100,
+	100,100,100,100,100,100,100,100,100,112,49,49,116,117,117,117,100,
+	100,100,112,93,51,33,127,108,100,100,100,100,100,100,100,100,100,100,
+	100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,
+	100,100,100,100,97,100,48,96,101,100,100,100,100,100,100,116,112,112,
+	112,112,96,100,100,48,52,52,48,49,49,49,49,49,49,49,113,112,48,49,
+	52,48,49,33,52,52,52,49,100,100,100,100,100,100,100,100,52,97,52,100,
+	100,100,100,32,37,37,37,49,49,49,49,49,49,49,49,49,113,48,37,49,49,
+	49,96,97,97,97,100,100,100,100,100,100,100,52,100,100,100,100,100,
+	100,100,100,100,100,100,100,100,100,100,100,100,36,48,113,112,116,
+	49,113,33,116,117,117,100,100,100,36,92,51,48,127,108,100,100,100,
+	100,36,117,117,117,117,53,49,97,117,117,117,117,101,100,100,100,100,
+	100,100,116,117,117,117,117,101,100,112,117,117,97,53,100,100,100,
+	100,100,100,100,96,100,100,100,100,48,49,116,49,49,49,117,100,100,
+	100,100,100,100,100,117,117,117,97,32,49,113,117,117,117,53,96,100,
+	100,100,100,100,100,36,117,53,113,117,36,49,97,117,117,117,117,101,
+	100,100,100,100,100,100,36,112,96,101,36,48,49,33,112,117,117,117,
+	49,49,49,49,49,49,49,117,49,117,117,117,49,49,116,117,117,117,117,
+	100,100,100,100,100,100,100,117,117,117,117,32,49,49,116,97,97,33,
+	53,49,49,101,92,59,101,43,179,100,194,206,100,};
diff --git a/sys/dev/cx/cxddk.c b/sys/dev/cx/cxddk.c
new file mode 100644
index 0000000..e4328b5
--- /dev/null
+++ b/sys/dev/cx/cxddk.c
@@ -0,0 +1,905 @@
+/*
+ * Cronyx-Sigma Driver Development Kit.
+ *
+ * Copyright (C) 1998 Cronyx Engineering.
+ * Author: Pavel Novikov, <pavel@inr.net.kiae.su>
+ *
+ * Copyright (C) 1998-2003 Cronyx Engineering.
+ * Author: Roman Kurakin, <rik@cronyx.ru>
+ *
+ * This software is distributed with NO WARRANTIES, not even the implied
+ * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Authors grant any other persons or organisations permission to use
+ * or modify this software as long as this message is kept with the software,
+ * all derivative works or modified versions.
+ *
+ * Cronyx Id: cxddk.c,v 1.1.2.2 2003/11/27 14:24:50 rik Exp $
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <dev/cx/machdep.h>
+#include <dev/cx/cxddk.h>
+#include <dev/cx/cxreg.h>
+#include <dev/cx/cronyxfw.h>
+#include <dev/cx/csigmafw.h>
+
+#define BYTE *(unsigned char*)&
+
+/* standard base port set */
+static short porttab [] = {
+	0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0,
+	0x300, 0x320, 0x340, 0x360, 0x380, 0x3a0, 0x3c0, 0x3e0, 0
+};
+
+/*
+ * Compute the optimal size of the receive buffer.
+ */
+static int cx_compute_buf_len (cx_chan_t *c)
+{
+	int rbsz;
+	if (c->mode == M_ASYNC) {
+		rbsz = (c->rxbaud + 800 - 1) / 800 * 2;
+		if (rbsz < 4)
+			rbsz = 4;
+		else if (rbsz  > DMABUFSZ)
+			rbsz = DMABUFSZ;
+	}
+	else
+		rbsz = DMABUFSZ;
+
+	return rbsz;
+}
+
+/*
+ * Auto-detect the installed adapters.
+ */
+int cx_find (port_t *board_ports)
+{
+	int i, n;
+
+	for (i=0, n=0; porttab[i] && n<NBRD; i++)
+		if (cx_probe_board (porttab[i], -1, -1))
+			board_ports[n++] = porttab[i];
+	return n;
+}
+
+/*
+ * Initialize the adapter.
+ */
+int cx_open_board (cx_board_t *b, int num, port_t port, int irq, int dma)
+{
+	cx_chan_t *c;
+
+	if (num >= NBRD || ! cx_probe_board (port, irq, dma))
+		return 0;
+
+	/* init callback pointers */
+	for (c=b->chan; c<b->chan+NCHAN; ++c) {
+		c->call_on_tx = 0;
+		c->call_on_rx = 0;
+		c->call_on_msig = 0;
+		c->call_on_err = 0;
+	}
+
+	cx_init (b, num, port, irq, dma);
+
+	/* Loading firmware */
+	if (! cx_setup_board (b, csigma_fw_data, csigma_fw_len, csigma_fw_tvec))
+		return 0;
+	return 1;
+}
+
+/*
+ * Shutdown the adapter.
+ */
+void cx_close_board (cx_board_t *b)
+{
+	cx_setup_board (b, 0, 0, 0);
+
+	/* Reset the controller. */
+	outb (BCR0(b->port), 0);
+	if (b->chan[8].type || b->chan[12].type)
+		outb (BCR0(b->port+0x10), 0);
+}
+
+/*
+ * Start the channel.
+ */
+void cx_start_chan (cx_chan_t *c, cx_buf_t *cb, unsigned long phys)
+{
+	int command = 0;
+	int mode = 0;
+	int ier = 0;
+	int rbsz;
+
+	c->overflow = 0;
+
+	/* Setting up buffers */
+	if (cb) {
+		c->arbuf = cb->rbuffer[0];
+		c->brbuf = cb->rbuffer[1];
+		c->atbuf = cb->tbuffer[0];
+		c->btbuf = cb->tbuffer[1];
+		c->arphys = phys + ((char*)c->arbuf - (char*)cb);
+		c->brphys = phys + ((char*)c->brbuf - (char*)cb);
+		c->atphys = phys + ((char*)c->atbuf - (char*)cb);
+		c->btphys = phys + ((char*)c->btbuf - (char*)cb);
+	}
+
+	/* Set current channel number */
+	outb (CAR(c->port), c->num & 3);
+
+	/* set receiver A buffer physical address */
+	outw (ARBADRU(c->port), (unsigned short) (c->arphys>>16));
+	outw (ARBADRL(c->port), (unsigned short) c->arphys);
+
+	/* set receiver B buffer physical address */
+	outw (BRBADRU(c->port), (unsigned short) (c->brphys>>16));
+	outw (BRBADRL(c->port), (unsigned short) c->brphys);
+
+	/* set transmitter A buffer physical address */
+	outw (ATBADRU(c->port), (unsigned short) (c->atphys>>16));
+	outw (ATBADRL(c->port), (unsigned short) c->atphys);
+
+	/* set transmitter B buffer physical address */
+	outw (BTBADRU(c->port), (unsigned short) (c->btphys>>16));
+	outw (BTBADRL(c->port), (unsigned short) c->btphys);
+
+	/* rx */
+	command |= CCR_ENRX;
+	ier |= IER_RXD;
+	if (c->board->dma) {
+		mode |= CMR_RXDMA;
+		if (c->mode == M_ASYNC)
+			ier |= IER_RET;
+	}
+
+	/* tx */
+	command |= CCR_ENTX;
+	ier |= (c->mode == M_ASYNC) ? IER_TXD : (IER_TXD | IER_TXMPTY);
+	if (c->board->dma)
+		mode |= CMR_TXDMA;
+
+	/* Set mode */
+	outb (CMR(c->port), mode | (c->mode == M_ASYNC ? CMR_ASYNC : CMR_HDLC));
+
+	/* Clear and initialize channel */
+	cx_cmd (c->port, CCR_CLRCH);
+	cx_cmd (c->port, CCR_INITCH | command);
+	if (c->mode == M_ASYNC)
+		cx_cmd (c->port, CCR_ENTX);
+
+	/* Start receiver */
+	rbsz = cx_compute_buf_len(c);
+	outw (ARBCNT(c->port), rbsz);
+	outw (BRBCNT(c->port), rbsz);
+	outw (ARBSTS(c->port), BSTS_OWN24);
+	outw (BRBSTS(c->port), BSTS_OWN24);
+
+	if (c->mode == M_ASYNC)
+		ier |= IER_MDM;
+
+	/* Enable interrupts */
+	outb (IER(c->port), ier);
+
+	/* Clear DTR and RTS */
+	cx_set_dtr (c, 0);
+	cx_set_rts (c, 0);
+}
+
+/*
+ * Turn the receiver on/off.
+ */
+void cx_enable_receive (cx_chan_t *c, int on)
+{
+	unsigned char ier;
+
+	if (cx_receive_enabled(c) && ! on) {
+		outb (CAR(c->port), c->num & 3);
+		if (c->mode == M_ASYNC) {
+			ier = inb (IER(c->port));
+			outb (IER(c->port), ier & ~ (IER_RXD | IER_RET));
+		}
+		cx_cmd (c->port, CCR_DISRX);
+	} else if (! cx_receive_enabled(c) && on) {
+		outb (CAR(c->port), c->num & 3);
+		ier = inb (IER(c->port));
+		if (c->mode == M_ASYNC)
+			outb (IER(c->port), ier | (IER_RXD | IER_RET));
+		else
+			outb (IER(c->port), ier | IER_RXD);
+ 		cx_cmd (c->port, CCR_ENRX);
+	}
+}
+
+/*
+ * Turn the transmiter on/off.
+ */
+void cx_enable_transmit (cx_chan_t *c, int on)
+{
+	if (cx_transmit_enabled(c) && ! on) {
+		outb (CAR(c->port), c->num & 3);
+		if (c->mode != M_ASYNC)
+			outb (STCR(c->port), STC_ABORTTX | STC_SNDSPC);
+		cx_cmd (c->port, CCR_DISTX);
+	} else if (! cx_transmit_enabled(c) && on) {
+		outb (CAR(c->port), c->num & 3);
+		cx_cmd (c->port, CCR_ENTX);
+	}
+}
+
+/*
+ * Get channel status.
+ */
+int cx_receive_enabled (cx_chan_t *c)
+{
+	outb (CAR(c->port), c->num & 3);
+	return (inb (CSR(c->port)) & CSRA_RXEN) != 0;
+}
+
+int cx_transmit_enabled (cx_chan_t *c)
+{
+	outb (CAR(c->port), c->num & 3);
+	return (inb (CSR(c->port)) & CSRA_TXEN) != 0;
+}
+
+unsigned long cx_get_baud (cx_chan_t *c)
+{
+	return (c->opt.tcor.clk == CLK_EXT) ? 0 : c->txbaud;
+}
+
+int cx_get_loop (cx_chan_t *c)
+{
+	return c->opt.tcor.llm ? 1 : 0;
+}
+
+int cx_get_nrzi (cx_chan_t *c)
+{
+	return c->opt.rcor.encod == ENCOD_NRZI;
+}
+
+int cx_get_dpll (cx_chan_t *c)
+{
+	return c->opt.rcor.dpll ? 1 : 0;
+}
+
+void cx_set_baud (cx_chan_t *c, unsigned long bps)
+{
+	int clock, period;
+
+	c->txbaud = c->rxbaud = bps;
+
+	/* Set current channel number */
+	outb (CAR(c->port), c->num & 3);
+	if (bps) {
+		if (c->mode == M_ASYNC || c->opt.rcor.dpll || c->opt.tcor.llm) {
+			/* Receive baud - internal */
+			cx_clock (c->oscfreq, c->rxbaud, &clock, &period);
+			c->opt.rcor.clk = clock;
+			outb (RCOR(c->port), BYTE c->opt.rcor);
+			outb (RBPR(c->port), period);
+		} else {
+			/* Receive baud - external */
+			c->opt.rcor.clk = CLK_EXT;
+			outb (RCOR(c->port), BYTE c->opt.rcor);
+			outb (RBPR(c->port), 1);
+		}
+
+		/* Transmit baud - internal */
+		cx_clock (c->oscfreq, c->txbaud, &clock, &period);
+		c->opt.tcor.clk = clock;
+		c->opt.tcor.ext1x = 0;
+		outb (TBPR(c->port), period);
+	} else if (c->mode != M_ASYNC) {
+		/* External clock - disable local loopback and DPLL */
+		c->opt.tcor.llm = 0;
+		c->opt.rcor.dpll = 0;
+
+		/* Transmit baud - external */
+		c->opt.tcor.ext1x = 1;
+		c->opt.tcor.clk = CLK_EXT;
+		outb (TBPR(c->port), 1);
+
+		/* Receive baud - external */
+		c->opt.rcor.clk = CLK_EXT;
+		outb (RCOR(c->port), BYTE c->opt.rcor);
+		outb (RBPR(c->port), 1);
+	}
+	if (c->opt.tcor.llm)
+		outb (COR2(c->port), (BYTE c->hopt.cor2) & ~3);
+	else
+		outb (COR2(c->port), BYTE c->hopt.cor2);
+	outb (TCOR(c->port), BYTE c->opt.tcor);
+}
+
+void cx_set_loop (cx_chan_t *c, int on)
+{
+	if (! c->txbaud)
+		return;
+
+	c->opt.tcor.llm = on ? 1 : 0;
+	cx_set_baud (c, c->txbaud);
+}
+
+void cx_set_dpll (cx_chan_t *c, int on)
+{
+	if (! c->txbaud)
+		return;
+
+	c->opt.rcor.dpll = on ? 1 : 0;
+	cx_set_baud (c, c->txbaud);
+}
+
+void cx_set_nrzi (cx_chan_t *c, int nrzi)
+{
+	c->opt.rcor.encod = (nrzi ? ENCOD_NRZI : ENCOD_NRZ);
+	outb (CAR(c->port), c->num & 3);
+	outb (RCOR(c->port), BYTE c->opt.rcor);
+}
+
+static int cx_send (cx_chan_t *c, char *data, int len,
+	void *attachment)
+{
+	unsigned char *buf;
+	port_t cnt_port, sts_port;
+	void **attp;
+
+	/* Set the current channel number. */
+	outb (CAR(c->port), c->num & 3);
+
+	/* Determine the buffer order. */
+	if (inb (DMABSTS(c->port)) & DMABSTS_NTBUF) {
+		if (inb (BTBSTS(c->port)) & BSTS_OWN24) {
+			buf	 = c->atbuf;
+			cnt_port = ATBCNT(c->port);
+			sts_port = ATBSTS(c->port);
+			attp	 = &c->attach[0];
+		} else {
+			buf	 = c->btbuf;
+			cnt_port = BTBCNT(c->port);
+			sts_port = BTBSTS(c->port);
+			attp	 = &c->attach[1];
+		}
+	} else {
+		if (inb (ATBSTS(c->port)) & BSTS_OWN24) {
+			buf	 = c->btbuf;
+			cnt_port = BTBCNT(c->port);
+			sts_port = BTBSTS(c->port);
+			attp	 = &c->attach[1];
+		} else {
+			buf	 = c->atbuf;
+			cnt_port = ATBCNT(c->port);
+			sts_port = ATBSTS(c->port);
+			attp	 = &c->attach[0];
+		}
+	}
+	/* Is it busy? */
+	if (inb (sts_port) & BSTS_OWN24)
+		return -1;
+
+	memcpy (buf, data, len);
+	*attp = attachment;
+
+	/* Start transmitter. */
+	outw (cnt_port, len);
+	outb (sts_port, BSTS_EOFR | BSTS_INTR | BSTS_OWN24);
+
+	/* Enable TXMPTY interrupt,
+	 * to catch the case when the second buffer is empty. */
+	if (c->mode != M_ASYNC) {
+		if ((inb(ATBSTS(c->port)) & BSTS_OWN24) &&
+		    (inb(BTBSTS(c->port)) & BSTS_OWN24)) {
+			outb (IER(c->port), IER_RXD | IER_TXD | IER_TXMPTY);
+		} else
+			outb (IER(c->port), IER_RXD | IER_TXD);
+	}
+	return 0;
+}
+
+/*
+ * Number of free buffs
+ */
+int cx_buf_free (cx_chan_t *c)
+{
+	return ! (inb (ATBSTS(c->port)) & BSTS_OWN24) +
+		! (inb (BTBSTS(c->port)) & BSTS_OWN24);
+}
+
+/*
+ * Send the data packet.
+ */
+int cx_send_packet (cx_chan_t *c, char *data, int len, void *attachment)
+{
+	if (len >= DMABUFSZ)
+		return -2;
+	if (c->mode == M_ASYNC) {
+		static char buf [DMABUFSZ];
+		char *p, *t = buf;
+
+		/* Async -- double all nulls. */
+		for (p=data; p < data+len && t < buf+DMABUFSZ-1; ++p)
+			if ((*t++ = *p) == 0)
+				*t++ = 0;
+		return cx_send (c, buf, t-buf, attachment);
+	}
+	return cx_send (c, data, len, attachment);
+}
+
+static int cx_receive_interrupt (cx_chan_t *c)
+{
+	unsigned short risr;
+	int len = 0, rbsz;
+
+	++c->rintr;
+	risr = inw (RISR(c->port));
+
+	/* Compute optimal receiver buffer length */
+	rbsz = cx_compute_buf_len(c);
+	if (c->mode == M_ASYNC && (risr & RISA_TIMEOUT)) {
+		unsigned long rcbadr = (unsigned short) inw (RCBADRL(c->port)) |
+			(long) inw (RCBADRU(c->port)) << 16;
+		unsigned char *buf = 0;
+		port_t cnt_port = 0, sts_port = 0;
+
+		if (rcbadr >= c->brphys && rcbadr < c->brphys+DMABUFSZ) {
+			buf = c->brbuf;
+			len = rcbadr - c->brphys;
+			cnt_port = BRBCNT(c->port);
+			sts_port = BRBSTS(c->port);
+		} else if (rcbadr >= c->arphys && rcbadr < c->arphys+DMABUFSZ) {
+			buf = c->arbuf;
+			len = rcbadr - c->arphys;
+			cnt_port = ARBCNT(c->port);
+			sts_port = ARBSTS(c->port);
+		}
+
+		if (len) {
+			c->ibytes += len;
+			c->received_data = buf;
+			c->received_len = len;
+
+			/* Restart receiver. */
+			outw (cnt_port, rbsz);
+			outb (sts_port, BSTS_OWN24);
+		}
+		return (REOI_TERMBUFF);
+	}
+
+	/* Receive errors. */
+	if (risr & RIS_OVERRUN) {
+		++c->ierrs;
+		if (c->call_on_err)
+			c->call_on_err (c, CX_OVERRUN);
+	} else if (c->mode != M_ASYNC && (risr & RISH_CRCERR)) {
+		++c->ierrs;
+		if (c->call_on_err)
+			c->call_on_err (c, CX_CRC);
+	} else if (c->mode != M_ASYNC && (risr & (RISH_RXABORT | RISH_RESIND))) {
+		++c->ierrs;
+		if (c->call_on_err)
+			c->call_on_err (c, CX_FRAME);
+	} else if (c->mode == M_ASYNC && (risr & RISA_PARERR)) {
+		++c->ierrs;
+		if (c->call_on_err)
+			c->call_on_err (c, CX_CRC);
+	} else if (c->mode == M_ASYNC && (risr & RISA_FRERR)) {
+		++c->ierrs;
+		if (c->call_on_err)
+			c->call_on_err (c, CX_FRAME);
+	} else if (c->mode == M_ASYNC && (risr & RISA_BREAK)) {
+		if (c->call_on_err)
+			c->call_on_err (c, CX_BREAK);
+	} else if (! (risr & RIS_EOBUF)) {
+		++c->ierrs;
+	} else {
+		/* Handle received data. */
+		len = (risr & RIS_BB) ? inw(BRBCNT(c->port)) : inw(ARBCNT(c->port));
+
+		if (len > DMABUFSZ) {
+			/* Fatal error: actual DMA transfer size
+			 * exceeds our buffer size.  It could be caused
+			 * by incorrectly programmed DMA register or
+			 * hardware fault.  Possibly, should panic here. */
+			len = DMABUFSZ;
+		} else if (c->mode != M_ASYNC && ! (risr & RIS_EOFR)) {
+			/* The received frame does not fit in the DMA buffer.
+			 * It could be caused by serial lie noise,
+			 * or if the peer has too big MTU. */
+			if (! c->overflow) {
+				if (c->call_on_err)
+					c->call_on_err (c, CX_OVERFLOW);
+				c->overflow = 1;
+				++c->ierrs;
+			}
+		} else if (! c->overflow) {
+			if (risr & RIS_BB) {
+				c->received_data = c->brbuf;
+				c->received_len = len;
+			} else {
+				c->received_data = c->arbuf;
+				c->received_len = len;
+			}
+			if (c->mode != M_ASYNC)
+				++c->ipkts;
+			c->ibytes += len;
+		} else
+			c->overflow = 0;
+	}
+
+	/* Restart receiver. */
+	if (! (inb (ARBSTS(c->port)) & BSTS_OWN24)) {
+		outw (ARBCNT(c->port), rbsz);
+		outb (ARBSTS(c->port), BSTS_OWN24);
+	}
+	if (! (inb (BRBSTS(c->port)) & BSTS_OWN24)) {
+		outw (BRBCNT(c->port), rbsz);
+		outb (BRBSTS(c->port), BSTS_OWN24);
+	}
+
+	/* Discard exception characters. */
+	if ((risr & RISA_SCMASK) && c->aopt.cor2.ixon)
+		return (REOI_DISCEXC);
+	else
+		return (0);
+}
+
+static void cx_transmit_interrupt (cx_chan_t *c)
+{
+	unsigned char tisr;
+	int len = 0;
+
+	++c->tintr;
+	tisr = inb (TISR(c->port));
+	if (tisr & TIS_UNDERRUN) {	/* Transmit underrun error */
+		if (c->call_on_err)
+			c->call_on_err (c, CX_UNDERRUN);
+		++c->oerrs;
+	} else if (tisr & (TIS_EOBUF | TIS_TXEMPTY | TIS_TXDATA)) {
+		/* Call processing function */
+		if (tisr & TIS_BB) {
+			len = inw(BTBCNT(c->port));
+			if (c->call_on_tx)
+				c->call_on_tx (c, c->attach[1], len);
+		} else {
+			len = inw(ATBCNT(c->port));
+			if (c->call_on_tx)
+				c->call_on_tx (c, c->attach[0], len);
+		}
+		if (c->mode != M_ASYNC && len != 0)
+			++c->opkts;
+		c->obytes += len;
+	}
+
+	/* Enable TXMPTY interrupt,
+	 * to catch the case when the second buffer is empty. */
+	if (c->mode != M_ASYNC) {
+		if ((inb (ATBSTS(c->port)) & BSTS_OWN24) &&
+		   (inb (BTBSTS(c->port)) & BSTS_OWN24)) {
+			outb (IER(c->port), IER_RXD | IER_TXD | IER_TXMPTY);
+		} else
+			outb (IER(c->port), IER_RXD | IER_TXD);
+	}
+}
+
+void cx_int_handler (cx_board_t *b)
+{
+	unsigned char livr;
+	cx_chan_t *c;
+
+	while (! (inw (BSR(b->port)) & BSR_NOINTR)) {
+		/* Enter the interrupt context, using IACK bus cycle.
+		   Read the local interrupt vector register. */
+		livr = inb (IACK(b->port, BRD_INTR_LEVEL));
+		c = b->chan + (livr>>2 & 0xf);
+		if (c->type == T_NONE)
+			continue;
+		switch (livr & 3) {
+		case LIV_MODEM: 		/* modem interrupt */
+			++c->mintr;
+			if (c->call_on_msig)
+				c->call_on_msig (c);
+			outb (MEOIR(c->port), 0);
+			break;
+		case LIV_EXCEP: 		/* receive exception */
+		case LIV_RXDATA:		/* receive interrupt */
+			outb (REOIR(c->port), cx_receive_interrupt (c));
+			if (c->call_on_rx && c->received_data) {
+				c->call_on_rx (c, c->received_data,
+					c->received_len);
+				c->received_data = 0;
+			}
+			break;
+		case LIV_TXDATA:		/* transmit interrupt */
+			cx_transmit_interrupt (c);
+			outb (TEOIR(c->port), 0);
+			break;
+		}
+	}
+}
+
+/*
+ * Register event processing functions
+ */
+void cx_register_transmit (cx_chan_t *c,
+	void (*func) (cx_chan_t *c, void *attachment, int len))
+{
+	c->call_on_tx = func;
+}
+
+void cx_register_receive (cx_chan_t *c,
+	void (*func) (cx_chan_t *c, char *data, int len))
+{
+	c->call_on_rx = func;
+}
+
+void cx_register_modem (cx_chan_t *c, void (*func) (cx_chan_t *c))
+{
+	c->call_on_msig = func;
+}
+
+void cx_register_error (cx_chan_t *c, void (*func) (cx_chan_t *c, int data))
+{
+	c->call_on_err = func;
+}
+
+/*
+ * Async protocol functions.
+ */
+
+/*
+ * Enable/disable transmitter.
+ */
+void cx_transmitter_ctl (cx_chan_t *c,int start)
+{
+	outb (CAR(c->port), c->num & 3);
+	cx_cmd (c->port, start ? CCR_ENTX : CCR_DISTX);
+}
+
+/*
+ * Discard all data queued in transmitter.
+ */
+void cx_flush_transmit (cx_chan_t *c)
+{
+	outb (CAR(c->port), c->num & 3);
+	cx_cmd (c->port, CCR_CLRTX);
+}
+
+/*
+ * Send the XON/XOFF flow control symbol.
+ */
+void cx_xflow_ctl (cx_chan_t *c, int on)
+{
+	outb (CAR(c->port), c->num & 3);
+	outb (STCR(c->port), STC_SNDSPC | (on ? STC_SSPC_1 : STC_SSPC_2));
+}
+
+/*
+ * Send the break signal for a given number of milliseconds.
+ */
+void cx_send_break (cx_chan_t *c, int msec)
+{
+	static unsigned char buf [128];
+	unsigned char *p;
+
+	p = buf;
+	*p++ = 0;		/* extended transmit command */
+	*p++ = 0x81;		/* send break */
+
+	if (msec > 10000)	/* max 10 seconds */
+		msec = 10000;
+	if (msec < 10)		/* min 10 msec */
+		msec = 10;
+	while (msec > 0) {
+		int ms = 250;	/* 250 msec */
+		if (ms > msec)
+			ms = msec;
+		msec -= ms;
+		*p++ = 0;	/* extended transmit command */
+		*p++ = 0x82;	/* insert delay */
+		*p++ = ms;
+	}
+	*p++ = 0;		/* extended transmit command */
+	*p++ = 0x83;		/* stop break */
+
+	cx_send (c, buf, p-buf, 0);
+}
+
+/*
+ * Set async parameters.
+ */
+void cx_set_async_param (cx_chan_t *c, int baud, int bits, int parity,
+	int stop2, int ignpar, int rtscts,
+	int ixon, int ixany, int symstart, int symstop)
+{
+	int clock, period;
+	cx_cor1_async_t cor1;
+
+	/* Set character length and parity mode. */
+	BYTE cor1 = 0;
+	cor1.charlen = bits - 1;
+	cor1.parmode = parity ? PARM_NORMAL : PARM_NOPAR;
+	cor1.parity = parity==1 ? PAR_ODD : PAR_EVEN;
+	cor1.ignpar = ignpar ? 1 : 0;
+
+	/* Enable/disable hardware CTS. */
+	c->aopt.cor2.ctsae = rtscts ? 1 : 0;
+
+	/* Enable extended transmit command mode.
+	 * Unfortunately, there is no other method for sending break. */
+	c->aopt.cor2.etc = 1;
+
+	/* Enable/disable hardware XON/XOFF. */
+	c->aopt.cor2.ixon = ixon ? 1 : 0;
+	c->aopt.cor2.ixany = ixany ? 1 : 0;
+
+	/* Set the number of stop bits. */
+	if (stop2)
+		c->aopt.cor3.stopb = STOPB_2;
+	else
+		c->aopt.cor3.stopb = STOPB_1;
+
+	/* Disable/enable passing XON/XOFF chars to the host. */
+	c->aopt.cor3.scde = ixon ? 1 : 0;
+	c->aopt.cor3.flowct = ixon ? FLOWCC_NOTPASS : FLOWCC_PASS;
+
+	c->aopt.schr1 = symstart;	/* XON */
+	c->aopt.schr2 = symstop;	/* XOFF */
+
+	/* Set current channel number. */
+	outb (CAR(c->port), c->num & 3);
+
+	/* Set up clock values. */
+	if (baud) {
+		c->rxbaud = c->txbaud = baud;
+
+		/* Receiver. */
+		cx_clock (c->oscfreq, c->rxbaud, &clock, &period);
+		c->opt.rcor.clk = clock;
+		outb (RCOR(c->port), BYTE c->opt.rcor);
+		outb (RBPR(c->port), period);
+
+		/* Transmitter. */
+		cx_clock (c->oscfreq, c->txbaud, &clock, &period);
+		c->opt.tcor.clk = clock;
+		c->opt.tcor.ext1x = 0;
+		outb (TCOR(c->port), BYTE c->opt.tcor);
+		outb (TBPR(c->port), period);
+	}
+	outb (COR2(c->port), BYTE c->aopt.cor2);
+	outb (COR3(c->port), BYTE c->aopt.cor3);
+	outb (SCHR1(c->port), c->aopt.schr1);
+	outb (SCHR2(c->port), c->aopt.schr2);
+
+	if (BYTE c->aopt.cor1 != BYTE cor1) {
+		BYTE c->aopt.cor1 = BYTE cor1;
+		outb (COR1(c->port), BYTE c->aopt.cor1);
+		/* Any change to COR1 require reinitialization. */
+		/* Unfortunately, it may cause transmitter glitches... */
+		cx_cmd (c->port, CCR_INITCH);
+	}
+}
+
+/*
+ * Set mode: M_ASYNC or M_HDLC.
+ * Both receiver and transmitter are disabled.
+ */
+int cx_set_mode (cx_chan_t *c, int mode)
+{
+	if (mode == M_HDLC) {
+		if (c->type == T_ASYNC)
+			return -1;
+
+		if (c->mode == M_HDLC)
+			return 0;
+
+		c->mode = M_HDLC;
+	} else if (mode == M_ASYNC) {
+		if (c->type == T_SYNC_RS232 ||
+		    c->type == T_SYNC_V35   ||
+		    c->type == T_SYNC_RS449)
+			return -1;
+
+		if (c->mode == M_ASYNC)
+			return 0;
+
+		c->mode = M_ASYNC;
+		c->opt.tcor.ext1x = 0;
+		c->opt.tcor.llm = 0;
+		c->opt.rcor.dpll = 0;
+		c->opt.rcor.encod = ENCOD_NRZ;
+		if (! c->txbaud || ! c->rxbaud)
+			c->txbaud = c->rxbaud = 9600;
+	} else
+		return -1;
+
+	cx_setup_chan (c);
+	cx_start_chan (c, 0, 0);
+	cx_enable_receive (c, 0);
+	cx_enable_transmit (c, 0);
+	return 0;
+}
+
+/*
+ * Set port type for old models of Sigma
+ */
+void cx_set_port (cx_chan_t *c, int iftype)
+{
+	if (c->board->type == B_SIGMA_XXX) {
+		switch (c->num) {
+		case 0:
+			if ((c->board->if0type != 0) == (iftype != 0))
+				return;
+			c->board->if0type = iftype;
+			c->board->bcr0 &= ~BCR0_UMASK;
+			if (c->board->if0type &&
+			    (c->type==T_UNIV_RS449 || c->type==T_UNIV_V35))
+				c->board->bcr0 |= BCR0_UI_RS449;
+			outb (BCR0(c->board->port), c->board->bcr0);
+			break;
+		case 8:
+			if ((c->board->if8type != 0) == (iftype != 0))
+				return;
+			c->board->if8type = iftype;
+			c->board->bcr0b &= ~BCR0_UMASK;
+			if (c->board->if8type &&
+			    (c->type==T_UNIV_RS449 || c->type==T_UNIV_V35))
+				c->board->bcr0b |= BCR0_UI_RS449;
+			outb (BCR0(c->board->port+0x10), c->board->bcr0b);
+			break;
+		}
+	}
+}
+
+/*
+ * Get port type for old models of Sigma
+ * -1 Fixed port type or auto detect
+ *  0 RS232
+ *  1 V35
+ *  2 RS449
+ */
+int cx_get_port (cx_chan_t *c)
+{
+	int iftype;
+
+	if (c->board->type == B_SIGMA_XXX) {
+		switch (c->num) {
+		case 0:
+			iftype = c->board->if0type; break;
+		case 8:
+			iftype = c->board->if8type; break;
+		default:
+			return -1;
+		}
+
+		if (iftype)
+			switch (c->type) {
+			case T_UNIV_V35:   return 1; break;
+			case T_UNIV_RS449: return 2; break;
+			default:	   return -1; break;
+			}
+		else
+			return 0;
+	} else
+		return -1;
+}
+
+void cx_intr_off (cx_board_t *b)
+{
+	outb (BCR0(b->port), b->bcr0 & ~BCR0_IRQ_MASK);
+	if (b->chan[8].port || b->chan[12].port)
+		outb (BCR0(b->port+0x10), b->bcr0b & ~BCR0_IRQ_MASK);
+}
+
+void cx_intr_on (cx_board_t *b)
+{
+	outb (BCR0(b->port), b->bcr0);
+	if (b->chan[8].port || b->chan[12].port)
+		outb (BCR0(b->port+0x10), b->bcr0b);
+}
+
+int cx_checkintr (cx_board_t *b)
+{
+	return (!(inw (BSR(b->port)) & BSR_NOINTR));
+}
diff --git a/sys/dev/cx/cxddk.h b/sys/dev/cx/cxddk.h
new file mode 100644
index 0000000..75b40c0
--- /dev/null
+++ b/sys/dev/cx/cxddk.h
@@ -0,0 +1,487 @@
+/*
+ * Defines for Cronyx-Sigma adapter driver.
+ *
+ * Copyright (C) 1994-2001 Cronyx Engineering.
+ * Author: Serge Vakulenko, <vak@cronyx.ru>
+ *
+ * Copyright (C) 1998-2003 Cronyx Engineering.
+ * Author: Roman Kurakin, <rik@cronyx.ru>
+ *
+ * This software is distributed with NO WARRANTIES, not even the implied
+ * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Authors grant any other persons or organisations permission to use
+ * or modify this software as long as this message is kept with the software,
+ * all derivative works or modified versions.
+ *
+ * Cronyx Id: cxddk.h,v 1.1.2.1 2003/11/12 17:13:41 rik Exp $
+ * $FreeBSD$
+ */
+
+#ifndef port_t
+#   ifdef _M_ALPHA                      /* port address on Alpha under */
+#      define port_t unsigned long      /* Windows NT is 32 bit long */
+#   else
+#      define port_t unsigned short     /* all other architectures */
+#   endif                               /* have 16-bit port addresses */
+#endif
+
+#define NBRD		3		/* the max number of installed boards */
+#define NPORT		32		/* the number of i/o ports per board */
+#define DMABUFSZ	1600
+
+/*
+ * Asynchronous channel mode -------------------------------------------------
+ */
+
+/* Parity */
+#define	PAR_EVEN	0	/* even parity */
+#define	PAR_ODD		1	/* odd parity */
+
+/* Parity mode */
+#define	PARM_NOPAR	0	/* no parity */
+#define	PARM_FORCE	1	/* force parity (odd = force 1, even = 0) */
+#define	PARM_NORMAL	2	/* normal parity */
+
+/* Flow control transparency mode */
+#define	FLOWCC_PASS	0	/* pass flow ctl chars as exceptions */
+#define FLOWCC_NOTPASS  1       /* don't pass flow ctl chars to the host */
+
+/* Stop bit length */
+#define	STOPB_1		2	/* 1 stop bit */
+#define	STOPB_15	3	/* 1.5 stop bits */
+#define	STOPB_2		4	/* 2 stop bits */
+
+/* Action on break condition */
+#define	BRK_INTR	0	/* generate an exception interrupt */
+#define	BRK_NULL	1	/* translate to a NULL character */
+#define	BRK_RESERVED	2	/* reserved */
+#define	BRK_DISCARD	3	/* discard character */
+
+/* Parity/framing error actions */
+#define	PERR_INTR	0	/* generate an exception interrupt */
+#define	PERR_NULL	1	/* translate to a NULL character */
+#define	PERR_IGNORE	2	/* ignore error; char passed as good data */
+#define	PERR_DISCARD	3	/* discard error character */
+#define	PERR_FFNULL	5	/* translate to FF NULL char */
+
+typedef struct {		/* async channel option register 1 */
+	unsigned charlen : 4;	/* character length, 5..8 */
+	unsigned ignpar : 1;	/* ignore parity */
+	unsigned parmode : 2;	/* parity mode */
+	unsigned parity : 1;	/* parity */
+} cx_cor1_async_t;
+
+typedef struct {		/* async channel option register 2 */
+	unsigned dsrae : 1;	/* DSR automatic enable */
+	unsigned ctsae : 1;	/* CTS automatic enable */
+	unsigned rtsao : 1;	/* RTS automatic output enable */
+	unsigned rlm : 1;	/* remote loopback mode enable */
+	unsigned zero : 1;
+	unsigned etc : 1;	/* embedded transmitter cmd enable */
+	unsigned ixon : 1;	/* in-band XON/XOFF enable */
+	unsigned ixany : 1;	/* XON on any character */
+} cx_cor2_async_t;
+
+typedef struct {		/* async channel option register 3 */
+	unsigned stopb : 3;	/* stop bit length */
+	unsigned zero : 1;
+	unsigned scde : 1;	/* special char detection enable */
+	unsigned flowct : 1;	/* flow control transparency mode */
+	unsigned rngde : 1;	/* range detect enable */
+	unsigned escde : 1;	/* extended spec. char detect enable */
+} cx_cor3_async_t;
+
+typedef struct {		/* async channel option register 6 */
+	unsigned parerr : 3;	/* parity/framing error actions */
+	unsigned brk : 2;	/* action on break condition */
+	unsigned inlcr : 1;	/* translate NL to CR on input */
+	unsigned icrnl : 1;	/* translate CR to NL on input */
+	unsigned igncr : 1;	/* discard CR on input */
+} cx_cor6_async_t;
+
+typedef struct {		/* async channel option register 7 */
+	unsigned ocrnl : 1;	/* translate CR to NL on output */
+	unsigned onlcr : 1;	/* translate NL to CR on output */
+	unsigned zero : 3;
+	unsigned fcerr : 1;	/* process flow ctl err chars enable */
+	unsigned lnext : 1;	/* LNext option enable */
+	unsigned istrip : 1;	/* strip 8-bit on input */
+} cx_cor7_async_t;
+
+typedef struct {		/* async channel options */
+	cx_cor1_async_t cor1;   /* channel option register 1 */
+	cx_cor2_async_t cor2;   /* channel option register 2 */
+	cx_cor3_async_t cor3;   /* option register 3 */
+	cx_cor6_async_t cor6;   /* channel option register 6 */
+	cx_cor7_async_t cor7;   /* channel option register 7 */
+	unsigned char schr1;	/* special character register 1 (XON) */
+	unsigned char schr2;	/* special character register 2 (XOFF) */
+	unsigned char schr3;	/* special character register 3 */
+	unsigned char schr4;	/* special character register 4 */
+	unsigned char scrl;	/* special character range low */
+	unsigned char scrh;	/* special character range high */
+	unsigned char lnxt;	/* LNext character */
+} cx_opt_async_t;
+
+/*
+ * HDLC channel mode ---------------------------------------------------------
+ */
+/* Address field length option */
+#define	AFLO_1OCT	0	/* address field is 1 octet in length */
+#define	AFLO_2OCT	1	/* address field is 2 octet in length */
+
+/* Clear detect for X.21 data transfer phase */
+#define	CLRDET_DISABLE	0	/* clear detect disabled */
+#define	CLRDET_ENABLE	1	/* clear detect enabled */
+
+/* Addressing mode */
+#define	ADMODE_NOADDR	0	/* no address */
+#define	ADMODE_4_1	1	/* 4 * 1 byte */
+#define	ADMODE_2_2	2	/* 2 * 2 byte */
+
+/* FCS append */
+#define	FCS_NOTPASS	0	/* receive CRC is not passed to the host */
+#define	FCS_PASS	1	/* receive CRC is passed to the host */
+
+/* CRC modes */
+#define	CRC_INVERT	0	/* CRC is transmitted inverted (CRC V.41) */
+#define	CRC_DONT_INVERT	1	/* CRC is not transmitted inverted (CRC-16) */
+
+/* Send sync pattern */
+#define	SYNC_00		0	/* send 00h as pad char (NRZI encoding) */
+#define	SYNC_AA		1	/* send AAh (Manchester/NRZ encoding) */
+
+/* FCS preset */
+#define	FCSP_ONES	0	/* FCS is preset to all ones (CRC V.41) */
+#define	FCSP_ZEROS	1	/* FCS is preset to all zeros (CRC-16) */
+
+/* idle mode */
+#define	IDLE_FLAG	0	/* idle in flag */
+#define	IDLE_MARK	1	/* idle in mark */
+
+/* CRC polynomial select */
+#define	POLY_V41	0	/* x^16+x^12+x^5+1 (HDLC, preset to 1) */
+#define	POLY_16		1	/* x^16+x^15+x^2+1 (bisync, preset to 0) */
+
+typedef struct {		/* hdlc channel option register 1 */
+	unsigned ifflags : 4;	/* number of inter-frame flags sent */
+	unsigned admode : 2;	/* addressing mode */
+	unsigned clrdet : 1;	/* clear detect for X.21 data transfer phase */
+	unsigned aflo : 1;	/* address field length option */
+} cx_cor1_hdlc_t;
+
+typedef struct {		/* hdlc channel option register 2 */
+	unsigned dsrae : 1;	/* DSR automatic enable */
+	unsigned ctsae : 1;	/* CTS automatic enable */
+	unsigned rtsao : 1;	/* RTS automatic output enable */
+	unsigned zero1 : 1;
+	unsigned crcninv : 1;	/* CRC invertion option */
+	unsigned zero2 : 1;
+	unsigned fcsapd : 1;	/* FCS append */
+	unsigned zero3 : 1;
+} cx_cor2_hdlc_t;
+
+typedef struct {		/* hdlc channel option register 3 */
+	unsigned padcnt : 3;	/* pad character count */
+	unsigned idle : 1;	/* idle mode */
+	unsigned nofcs : 1;	/* FCS disable */
+	unsigned fcspre : 1;	/* FCS preset */
+	unsigned syncpat : 1;	/* send sync pattern */
+	unsigned sndpad : 1;	/* send pad characters before flag enable */
+} cx_cor3_hdlc_t;
+
+typedef struct {		/* hdlc channel options */
+	cx_cor1_hdlc_t cor1;    /* hdlc channel option register 1 */
+	cx_cor2_hdlc_t cor2;    /* hdlc channel option register 2 */
+	cx_cor3_hdlc_t cor3;    /* hdlc channel option register 3 */
+	unsigned char rfar1;	/* receive frame address register 1 */
+	unsigned char rfar2;	/* receive frame address register 2 */
+	unsigned char rfar3;	/* receive frame address register 3 */
+	unsigned char rfar4;	/* receive frame address register 4 */
+	unsigned char cpsr;	/* CRC polynomial select */
+} cx_opt_hdlc_t;
+
+/*
+ * CD2400 channel state structure --------------------------------------------
+ */
+
+/* Signal encoding */
+#define ENCOD_NRZ        0      /* NRZ mode */
+#define ENCOD_NRZI       1      /* NRZI mode */
+#define ENCOD_MANCHESTER 2      /* Manchester mode */
+
+/* Clock source */
+#define CLK_0           0      /* clock 0 */
+#define CLK_1           1      /* clock 1 */
+#define CLK_2           2      /* clock 2 */
+#define CLK_3           3      /* clock 3 */
+#define CLK_4           4      /* clock 4 */
+#define CLK_EXT         6      /* external clock */
+#define CLK_RCV         7      /* receive clock */
+
+/* Board type */
+#define B_SIGMA_XXX     0       /* old Sigmas */
+#define B_SIGMA_2X      1       /* Sigma-22 */
+#define B_SIGMA_800     2       /* Sigma-800 */
+
+/* Channel type */
+#define T_NONE          0       /* no channel */
+#define T_ASYNC         1       /* pure asynchronous RS-232 channel */
+#define T_SYNC_RS232    2       /* pure synchronous RS-232 channel */
+#define T_SYNC_V35      3       /* pure synchronous V.35 channel */
+#define T_SYNC_RS449    4       /* pure synchronous RS-449 channel */
+#define T_UNIV_RS232    5       /* sync/async RS-232 channel */
+#define T_UNIV_RS449    6       /* sync/async RS-232/RS-449 channel */
+#define T_UNIV_V35      7       /* sync/async RS-232/V.35 channel */
+#define T_UNIV          8       /* sync/async, unknown interface */
+
+#define M_ASYNC         0	/* asynchronous mode */
+#define M_HDLC          1	/* bit-sync mode (HDLC) */
+
+typedef struct {		/* channel option register 4 */
+	unsigned thr : 4;	/* FIFO threshold */
+	unsigned zero : 1;
+	unsigned cts_zd : 1;	/* detect 1 to 0 transition on the CTS */
+	unsigned cd_zd : 1;	/* detect 1 to 0 transition on the CD */
+	unsigned dsr_zd : 1;	/* detect 1 to 0 transition on the DSR */
+} cx_cor4_t;
+
+typedef struct {		/* channel option register 5 */
+	unsigned rx_thr : 4;	/* receive flow control FIFO threshold */
+	unsigned zero : 1;
+	unsigned cts_od : 1;	/* detect 0 to 1 transition on the CTS */
+	unsigned cd_od : 1;	/* detect 0 to 1 transition on the CD */
+	unsigned dsr_od : 1;	/* detect 0 to 1 transition on the DSR */
+} cx_cor5_t;
+
+typedef struct {		/* receive clock option register */
+	unsigned clk : 3;	/* receive clock source */
+	unsigned encod : 2;     /* signal encoding NRZ/NRZI/Manchester */
+	unsigned dpll : 1;      /* DPLL enable */
+	unsigned zero : 1;
+	unsigned tlval : 1;	/* transmit line value */
+} cx_rcor_t;
+
+typedef struct {		/* transmit clock option register */
+	unsigned zero1 : 1;
+	unsigned llm : 1;	/* local loopback mode */
+	unsigned zero2 : 1;
+	unsigned ext1x : 1;	/* external 1x clock mode */
+	unsigned zero3 : 1;
+	unsigned clk : 3;	/* transmit clock source */
+} cx_tcor_t;
+
+typedef struct {
+	cx_cor4_t cor4;         /* channel option register 4 */
+	cx_cor5_t cor5;         /* channel option register 5 */
+	cx_rcor_t rcor;         /* receive clock option register */
+	cx_tcor_t tcor;         /* transmit clock option register */
+} cx_chan_opt_t;
+
+typedef enum {                  /* line break mode */
+	BRK_IDLE,               /* normal line mode */
+	BRK_SEND,               /* start sending break */
+	BRK_STOP,               /* stop sending break */
+} cx_break_t;
+
+#define BUS_NORMAL	0	/* normal bus timing */
+#define BUS_FAST	1	/* fast bus timing (Sigma-22 and -800) */
+#define BUS_FAST2	2	/* fast bus timing (Sigma-800) */
+#define BUS_FAST3	3	/* fast bus timing (Sigma-800) */
+
+typedef struct {                /* board options */
+	unsigned char fast;	/* bus master timing (Sigma-22 and -800) */
+} cx_board_opt_t;
+
+#define NCHIP    4		/* the number of controllers per board */
+#define NCHAN    16		/* the number of channels on the board */
+
+typedef struct {
+	unsigned char tbuffer [2] [DMABUFSZ];
+	unsigned char rbuffer [2] [DMABUFSZ];
+} cx_buf_t;
+
+typedef struct _cx_chan_t {
+	struct _cx_board_t *board;      /* board pointer */
+	unsigned char type;             /* channel type */
+	unsigned char num;              /* channel number, 0..15 */
+	port_t port;                    /* base port address */
+	unsigned long oscfreq;		/* oscillator frequency in Hz */
+	unsigned long rxbaud;		/* receiver speed */
+	unsigned long txbaud;		/* transmitter speed */
+	unsigned char mode;             /* channel mode */
+	cx_chan_opt_t opt;              /* common channel options */
+	cx_opt_async_t aopt;            /* async mode options */
+	cx_opt_hdlc_t hopt;             /* hdlc mode options */
+	unsigned char *arbuf;           /* receiver A dma buffer */
+	unsigned char *brbuf;           /* receiver B dma buffer */
+	unsigned char *atbuf;           /* transmitter A dma buffer */
+	unsigned char *btbuf;           /* transmitter B dma buffer */
+	unsigned long arphys;           /* receiver A phys address */
+	unsigned long brphys;           /* receiver B phys address */
+	unsigned long atphys;           /* transmitter A phys address */
+	unsigned long btphys;           /* transmitter B phys address */
+	unsigned char dtr;              /* DTR signal value */
+	unsigned char rts;              /* RTS signal value */
+
+	unsigned long rintr;            /* receive interrupts */
+	unsigned long tintr;            /* transmit interrupts */
+	unsigned long mintr;            /* modem interrupts */
+	unsigned long ibytes;           /* input bytes */
+	unsigned long ipkts;            /* input packets */
+	unsigned long ierrs;            /* input errors */
+	unsigned long obytes;           /* output bytes */
+	unsigned long opkts;            /* output packets */
+	unsigned long oerrs;            /* output errors */
+
+	void *sys;
+	int debug;
+	void *attach [2];
+	char *received_data;
+	int received_len;
+	int overflow;
+
+	void (*call_on_rx) (struct _cx_chan_t*, char*, int);
+	void (*call_on_tx) (struct _cx_chan_t*, void*, int);
+	void (*call_on_msig) (struct _cx_chan_t*);
+	void (*call_on_err) (struct _cx_chan_t*, int);
+
+} cx_chan_t;
+
+typedef struct _cx_board_t {
+	unsigned char type;             /* board type */
+	unsigned char num;		/* board number, 0..2 */
+	port_t port;                    /* base board port, 0..3f0 */
+	unsigned char irq;              /* irq {3 5 7 10 11 12 15} */
+	unsigned char dma;              /* DMA request {5 6 7} */
+	char name[16];                  /* board version name */
+	unsigned char nuniv;            /* number of universal channels */
+	unsigned char nsync;            /* number of sync. channels */
+	unsigned char nasync;           /* number of async. channels */
+	unsigned char if0type;          /* chan0 interface RS-232/RS-449/V.35 */
+	unsigned char if8type;          /* chan8 interface RS-232/RS-449/V.35 */
+	unsigned short bcr0;            /* BCR0 image */
+	unsigned short bcr0b;           /* BCR0b image */
+	unsigned short bcr1;            /* BCR1 image */
+	unsigned short bcr1b;           /* BCR1b image */
+	cx_board_opt_t opt;             /* board options */
+	cx_chan_t chan[NCHAN];          /* channel structures */
+	void *sys;
+} cx_board_t;
+
+extern long cx_rxbaud, cx_txbaud;
+extern int cx_univ_mode, cx_sync_mode, cx_iftype;
+
+extern cx_chan_opt_t chan_opt_dflt;     /* default mode-independent options */
+extern cx_opt_async_t opt_async_dflt;   /* default async options */
+extern cx_opt_hdlc_t opt_hdlc_dflt;     /* default hdlc options */
+extern cx_board_opt_t board_opt_dflt;   /* default board options */
+
+struct _cr_dat_tst;
+int cx_probe_board (port_t port, int irq, int dma);
+void cx_init (cx_board_t *b, int num, port_t port, int irq, int dma);
+void cx_init_board (cx_board_t *b, int num, port_t port, int irq, int dma,
+	int chain, int rev, int osc, int mod, int rev2, int osc2, int mod2);
+void cx_init_2x (cx_board_t *b, int num, port_t port, int irq, int dma,
+	int rev, int osc);
+void cx_init_800 (cx_board_t *b, int num, port_t port, int irq, int dma,
+	int chain);
+int cx_download (port_t port, const unsigned char *firmware, long bits,
+	const struct _cr_dat_tst *tst);
+int cx_setup_board (cx_board_t *b, const unsigned char *firmware,
+	long bits, const struct _cr_dat_tst *tst);
+void cx_setup_chan (cx_chan_t *c);
+void cx_update_chan (cx_chan_t *c);
+void cx_set_dtr (cx_chan_t *c, int on);
+void cx_set_rts (cx_chan_t *c, int on);
+void cx_led (cx_board_t *b, int on);
+void cx_cmd (port_t base, int cmd);
+void cx_disable_dma (cx_board_t *b);
+void cx_reinit_board (cx_board_t *b);
+int cx_get_dsr (cx_chan_t *c);
+int cx_get_cts (cx_chan_t *c);
+int cx_get_cd (cx_chan_t *c);
+void cx_clock (long hz, long ba, int *clk, int *div);
+
+/* DDK errors */
+#define CX_FRAME	 1
+#define CX_CRC		 2
+#define CX_OVERRUN	 3
+#define CX_OVERFLOW	 4
+#define CX_UNDERRUN	 5
+#define CX_BREAK	 6
+
+/* clock sources */
+#define CX_CLK_INT	 0
+#define CX_CLK_EXT	 6
+#define CX_CLK_RCV	 7
+#define CX_CLK_DPLL	 8
+#define CX_CLK_DPLL_EXT	 14
+
+/* functions dealing with interrupt vector in DOS */
+#if defined (MSDOS) || defined (__MSDOS__)
+int ddk_int_alloc (int irq, void (*func)(), void *arg);
+int ddk_int_restore (int irq);
+#endif
+
+int cx_probe_irq (cx_board_t *b, int irq);
+void cx_int_handler (cx_board_t *b);
+
+int cx_find (port_t *board_ports);
+int cx_open_board (cx_board_t *b, int num, port_t port, int irq, int dma);
+void cx_close_board (cx_board_t *b);
+
+void cx_start_chan (cx_chan_t *c, cx_buf_t *cb, unsigned long phys);
+
+/*
+ Set port type for old models of Sigma
+ */
+void cx_set_port (cx_chan_t *c, int iftype);
+
+/*
+ Get port type for old models of Sigma
+ -1 Fixed port type or auto detect
+  0 RS232
+  1 V35
+  2 RS449
+ */
+int cx_get_port (cx_chan_t *c);
+
+void cx_enable_receive (cx_chan_t *c, int on);
+void cx_enable_transmit (cx_chan_t *c, int on);
+int cx_receive_enabled (cx_chan_t *c);
+int cx_transmit_enabled (cx_chan_t *c);
+
+void cx_set_baud (cx_chan_t *, unsigned long baud);
+int  cx_set_mode (cx_chan_t *c, int mode);
+void cx_set_loop (cx_chan_t *c, int on);
+void cx_set_nrzi (cx_chan_t *c, int nrzi);
+void cx_set_dpll (cx_chan_t *c, int on);
+
+unsigned long cx_get_baud (cx_chan_t *c);
+int cx_get_loop (cx_chan_t *c);
+int cx_get_nrzi (cx_chan_t *c);
+int cx_get_dpll (cx_chan_t *c);
+
+int cx_send_packet (cx_chan_t *c, char *data, int len, void *attachment);
+int cx_buf_free (cx_chan_t *c);
+
+void cx_register_transmit (cx_chan_t *c,
+	void (*func) (cx_chan_t *c, void *attachment, int len));
+void cx_register_receive (cx_chan_t *c,
+	void (*func) (cx_chan_t *c, char *data, int len));
+void cx_register_modem (cx_chan_t *c, void (*func) (cx_chan_t *c));
+void cx_register_error (cx_chan_t *c, void (*func) (cx_chan_t *c, int data));
+void	cx_intr_off (cx_board_t *b);
+void	cx_intr_on (cx_board_t *b);
+int	cx_checkintr (cx_board_t *b);
+
+/* Async functions */
+void cx_transmitter_ctl (cx_chan_t *c, int start);
+void cx_flush_transmit (cx_chan_t *c);
+void cx_xflow_ctl (cx_chan_t *c, int on);
+void cx_send_break (cx_chan_t *c, int msec);
+void cx_set_async_param (cx_chan_t *c, int baud, int bits, int parity,
+	int stop2, int ignpar, int rtscts,
+	int ixon, int ixany, int symstart, int symstop);
diff --git a/sys/dev/cx/cxreg.h b/sys/dev/cx/cxreg.h
new file mode 100644
index 0000000..0cfc6b0
--- /dev/null
+++ b/sys/dev/cx/cxreg.h
@@ -0,0 +1,486 @@
+/*
+ * Defines for Cronyx-Sigma adapter, based on Cirrus Logic multiprotocol
+ * controller RISC processor CL-CD2400/2401.
+ *
+ * Copyright (C) 1994-2000 Cronyx Engineering.
+ * Author: Serge Vakulenko, <vak@cronyx.ru>
+ *
+ * This software is distributed with NO WARRANTIES, not even the implied
+ * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Authors grant any other persons or organisations permission to use
+ * or modify this software as long as this message is kept with the software,
+ * all derivative works or modified versions.
+ *
+ * Cronyx Id: cxreg.h,v 1.1.2.1 2003/11/12 17:13:41 rik Exp $
+ * $FreeBSD$
+ */
+#define REVCL_MIN   7		/* CD2400 min. revision number G */
+#define REVCL_MAX   13		/* CD2400 max. revision number M */
+#define REVCL31_MIN 0x33	/* CD2431 min. revision number C */
+#define REVCL31_MAX 0x34	/* CD2431 max. revision number D */
+
+#define BRD_INTR_LEVEL 0x5a	/* interrupt level (arbitrary PILR value) */
+
+#define CS0(p)	((p) | 0x8000)	/* chip select 0 */
+#define CS1(p)	((p) | 0xc000)	/* chip select 1 */
+#define CS1A(p)	((p) | 0x8010)	/* chip select 1 for agp-compatible models */
+#define BSR(p)	(p)		/* board status register, read only */
+#define BCR0(p)	(p)		/* board command register 0, write only */
+#define BCR1(p)	((p) | 0x2000)	/* board command register 1, write only */
+
+/*
+ * For Sigma-800 only.
+ */
+#define BDET(p)	((p) | 0x2000)	/* board detection register, read only */
+#define BCR2(p)	((p) | 0x4000)	/* board command register 2, write only */
+
+/*
+ * Chip register address, B is chip base port, R is chip register number.
+ */
+#define R(b,r) ((b) | (((r)<<6 & 0x3c00) | ((r) & 0xf)))
+
+/*
+ * Interrupt acknowledge register, P is board port, L is interrupt level,
+ * as prodrammed in PILR.
+ */
+#define IACK(p,l)   (R(p,l) | 0x4000)
+
+/*
+ * Global registers.
+ */
+#define GFRCR(b)    R(b,0x82)	/* global firmware revision code register */
+#define CAR(b)      R(b,0xec)	/* channel access register */
+
+/*
+ * Option registers.
+ */
+#define CMR(b)      R(b,0x18)	/* channel mode register */
+#define COR1(b)     R(b,0x13)	/* channel option register 1 */
+#define COR2(b)     R(b,0x14)	/* channel option register 2 */
+#define COR3(b)     R(b,0x15)	/* channel option register 3 */
+#define COR4(b)     R(b,0x16)	/* channel option register 4 */
+#define COR5(b)     R(b,0x17)	/* channel option register 5 */
+#define COR6(b)     R(b,0x1b)	/* channel option register 6 */
+#define COR7(b)     R(b,0x04)	/* channel option register 7 */
+#define SCHR1(b)    R(b,0x1c)	/* special character register 1 */
+#define SCHR2(b)    R(b,0x1d)	/* special character register 2 */
+#define SCHR3(b)    R(b,0x1e)	/* special character register 3 */
+#define SCHR4(b)    R(b,0x1f)	/* special character register 4 */
+#define SCRL(b)     R(b,0x20)	/* special character range low */
+#define SCRH(b)     R(b,0x21)	/* special character range high */
+#define LNXT(b)     R(b,0x2d)	/* LNext character */
+#define RFAR1(b)    R(b,0x1c)	/* receive frame address register 1 */
+#define RFAR2(b)    R(b,0x1d)	/* receive frame address register 2 */
+#define RFAR3(b)    R(b,0x1e)	/* receive frame address register 3 */
+#define RFAR4(b)    R(b,0x1f)	/* receive frame address register 4 */
+#define CPSR(b)     R(b,0xd4)	/* CRC polynomial select register */
+
+/*
+ * Bit rate and clock option registers.
+ */
+#define RBPR(b)     R(b,0xc9)	/* receive baud rate period register */
+#define RCOR(b)     R(b,0xca)	/* receive clock option register */
+#define TBPR(b)     R(b,0xc1)	/* transmit baud rate period register */
+#define TCOR(b)     R(b,0xc2)	/* receive clock option register */
+
+/*
+ * Channel command and status registers.
+ */
+#define CCR(b)      R(b,0x10)	/* channel command register */
+#define STCR(b)     R(b,0x11)	/* special transmit command register */
+#define CSR(b)      R(b,0x19)	/* channel status register */
+#define MSVR(b)     R(b,0xdc)	/* modem signal value register */
+#define MSVR_RTS(b) R(b,0xdc)	/* modem RTS setup register */
+#define MSVR_DTR(b) R(b,0xdd)	/* modem DTR setup register */
+
+/*
+ * Interrupt registers.
+ */
+#define LIVR(b)     R(b,0x0a)	/* local interrupt vector register */
+#define IER(b)      R(b,0x12)	/* interrupt enable register */
+#define LICR(b)     R(b,0x25)	/* local interrupting channel register */
+#define STK(b)      R(b,0xe0)	/* stack register */
+
+/*
+ * Receive interrupt registers.
+ */
+#define RPILR(b)    R(b,0xe3)	/* receive priority interrupt level register */
+#define RIR(b)      R(b,0xef)	/* receive interrupt register */
+#define RISR(b)     R(b,0x8a)	/* receive interrupt status register */
+#define RISRL(b)    R(b,0x8a)	/* receive interrupt status register low */
+#define RISRH(b)    R(b,0x8b)	/* receive interrupt status register high */
+#define RFOC(b)     R(b,0x33)	/* receive FIFO output count */
+#define RDR(b)      R(b,0xf8)	/* receive data register */
+#define REOIR(b)    R(b,0x87)	/* receive end of interrupt register */
+
+/*
+ * Transmit interrupt registers.
+ */
+#define TPILR(b)    R(b,0xe2)	/* transmit priority interrupt level reg */
+#define TIR(b)      R(b,0xee)	/* transmit interrupt register */
+#define TISR(b)     R(b,0x89)	/* transmit interrupt status register */
+#define TFTC(b)     R(b,0x83)	/* transmit FIFO transfer count */
+#define TDR(b)      R(b,0xf8)	/* transmit data register */
+#define TEOIR(b)    R(b,0x86)	/* transmit end of interrupt register */
+
+/*
+ * Modem interrupt registers.
+ */
+#define MPILR(b)    R(b,0xe1)	/* modem priority interrupt level register */
+#define MIR(b)      R(b,0xed)	/* modem interrupt register */
+#define MISR(b)     R(b,0x88)	/* modem/timer interrupt status register */
+#define MEOIR(b)    R(b,0x85)	/* modem end of interrupt register */
+
+/*
+ * DMA registers.
+ */
+#define DMR(b)      R(b,0xf4)	/* DMA mode register */
+#define BERCNT(b)   R(b,0x8d)	/* bus error retry count */
+#define DMABSTS(b)  R(b,0x1a)	/* DMA buffer status */
+
+/*
+ * DMA receive registers.
+ */
+#define ARBADRL(b)  R(b,0x40)	/* A receive buffer address lower */
+#define ARBADRU(b)  R(b,0x42)	/* A receive buffer address upper */
+#define BRBADRL(b)  R(b,0x44)	/* B receive buffer address lower */
+#define BRBADRU(b)  R(b,0x46)	/* B receive buffer address upper */
+#define ARBCNT(b)   R(b,0x48)	/* A receive buffer byte count */
+#define BRBCNT(b)   R(b,0x4a)	/* B receive buffer byte count */
+#define ARBSTS(b)   R(b,0x4c)	/* A receive buffer status */
+#define BRBSTS(b)   R(b,0x4d)	/* B receive buffer status */
+#define RCBADRL(b)  R(b,0x3c)	/* receive current buffer address lower */
+#define RCBADRU(b)  R(b,0x3e)	/* receive current buffer address upper */
+
+/*
+ * DMA transmit registers.
+ */
+#define ATBADRL(b)  R(b,0x50)	/* A transmit buffer address lower */
+#define ATBADRU(b)  R(b,0x52)	/* A transmit buffer address upper */
+#define BTBADRL(b)  R(b,0x54)	/* B transmit buffer address lower */
+#define BTBADRU(b)  R(b,0x56)	/* B transmit buffer address upper */
+#define ATBCNT(b)   R(b,0x58)	/* A transmit buffer byte count */
+#define BTBCNT(b)   R(b,0x5a)	/* B transmit buffer byte count */
+#define ATBSTS(b)   R(b,0x5c)	/* A transmit buffer status */
+#define BTBSTS(b)   R(b,0x5d)	/* B transmit buffer status */
+#define TCBADRL(b)  R(b,0x38)	/* transmit current buffer address lower */
+#define TCBADRU(b)  R(b,0x3a)	/* transmit current buffer address upper */
+
+/*
+ * Timer registers.
+ */
+#define TPR(b)      R(b,0xd8)	/* timer period register */
+#define RTPR(b)     R(b,0x26)	/* receive timeout period register */
+#define RTPRL(b)    R(b,0x26)	/* receive timeout period register low */
+#define RTPTH(b)    R(b,0x27)	/* receive timeout period register high */
+#define GT1(b)      R(b,0x28)	/* general timer 1 */
+#define GT1L(b)     R(b,0x28)	/* general timer 1 low */
+#define GT1H(b)     R(b,0x29)	/* general timer 1 high */
+#define GT2(b)      R(b,0x2a)	/* general timer 2 */
+#define TTR(b)      R(b,0x2a)	/* transmit timer register */
+
+/*
+ * Board status register bits, for all models.
+ */
+#define BSR_NOINTR     0x01	/* no interrupt pending flag */
+#define BSR_NOCHAIN    0x80	/* no daisy chained board, all but Sigma-22 */
+
+/*
+ * For old Sigmas only.
+ */
+#define BSR_VAR_MASK   0x66	/* adapter variant mask */
+#define BSR_OSC_MASK   0x18	/* oscillator frequency mask */
+#define BSR_OSC_20     0x18	/* 20 MHz */
+#define BSR_OSC_18432  0x10	/* 18.432 MHz */
+
+#define BSR_NODSR(n)   (0x100 << (n))	/* DSR from channels 0-3, inverted */
+#define BSR_NOCD(n)    (0x1000 << (n))	/* CD from channels 0-3, inverted */
+
+/*
+ * Board status register bits for Sigma-2x.
+ */
+#define BSR2X_OSC_33     0x08	/* oscillator 33/20 MHz bit */
+#define BSR2X_VAR_MASK   0x30	/* Sigma-2x variant mask */
+
+/*
+ * Board status register bits for Sigma-800.
+ */
+#define BSR800_NU0       0x02	/* no channels 0-3 installed */
+#define BSR800_NU1       0x04	/* no channels 4-7 installed */
+#define BSR800_LERR      0x08	/* firmware load error */
+#define BSR800_MIRQ      0x10	/* modem IRQ active */
+#define BSR800_TIRQ      0x20	/* transmit IRQ active */
+#define BSR800_RIRQ      0x40	/* receive IRQ active */
+
+#define BDET_IB          0x08	/* identification bit */
+#define BDET_IB_NEG      0x80	/* negated identification bit */
+
+/*
+ * Sigma-800 control register 2 bits.
+ */
+#define BCR2_BUS0       0x01	/* bus timing control */
+#define BCR2_BUS1       0x02	/* bus timing control */
+#define BCR2_TMS  	0x08	/* firmware download signal */
+#define BCR2_TDI  	0x80	/* firmware download signal */
+
+/*
+ * Board revision mask.
+ */
+#define BSR_REV_MASK     (BSR_OSC_MASK|BSR_VAR_MASK|BSR_NOCHAIN)
+#define BSR2X_REV_MASK   (BSR_OSC_MASK|BSR_VAR_MASK)
+
+/*
+ * Sigma-2x variants.
+ */
+#define CRONYX_22	0x20
+#define CRONYX_24	0x00
+
+/*
+ * Sigma-XXX variants.
+ */
+#define CRONYX_100	0x64
+#define CRONYX_400	0x62
+#define CRONYX_500	0x60
+#define CRONYX_410	0x24
+#define CRONYX_810	0x20
+#define CRONYX_410s	0x04
+#define CRONYX_810s	0x00
+#define CRONYX_440	0x44
+#define CRONYX_840	0x40
+#define CRONYX_401	0x26
+#define CRONYX_801	0x22
+#define CRONYX_401s	0x06
+#define CRONYX_801s	0x02
+#define CRONYX_404	0x46
+#define CRONYX_703	0x42
+
+/*
+ * Board control register 0 bits.
+ */
+#define BCR0_IRQ_DIS  0x00	/* no interrupt generated */
+#define BCR0_IRQ_3    0x01	/* select IRQ number 3 */
+#define BCR0_IRQ_5    0x02	/* select IRQ number 5 */
+#define BCR0_IRQ_7    0x03	/* select IRQ number 7 */
+#define BCR0_IRQ_10   0x04	/* select IRQ number 10 */
+#define BCR0_IRQ_11   0x05	/* select IRQ number 11 */
+#define BCR0_IRQ_12   0x06	/* select IRQ number 12 */
+#define BCR0_IRQ_15   0x07	/* select IRQ number 15 */
+#define BCR0_IRQ_MASK 0x07	/* irq select mask */
+
+#define BCR0_DMA_DIS  0x00	/* no interrupt generated */
+#define BCR0_DMA_5    0x10	/* select DMA channel 5 */
+#define BCR0_DMA_6    0x20	/* select DMA channel 6 */
+#define BCR0_DMA_7    0x30	/* select DMA channel 7 */
+#define BCR0_DMA_MASK 0x30	/* drq select mask */
+
+/* For old Sigmas only. */
+#define BCR0_NORESET  0x08	/* CD2400 reset flag (inverted) */
+
+#define BCR0_UM_ASYNC 0x00	/* channel 0 mode - async */
+#define BCR0_UM_SYNC  0x80	/* channel 0 mode - sync */
+#define BCR0_UI_RS232 0x00	/* channel 0 interface - RS-232 */
+#define BCR0_UI_RS449 0x40	/* channel 0 interface - RS-449/V.35 */
+#define BCR0_UMASK    0xc0	/* channel 0 interface mask */
+
+/* For Sigma-22 only. */
+#define BCR02X_FAST   0x40	/* fast bus timing */
+#define BCR02X_LED    0x80	/* LED control */
+
+/* For Sigma-800 only. */
+#define BCR0800_TCK   0x80	/* firmware download signal */
+
+/*
+ * Board control register 1 bits.
+ */
+/* For old Sigmas only. */
+#define BCR1_DTR(n)    (0x100 << (n))	/* DTR for channels 0-3 sync */
+
+/* For Sigma-800 only. */
+#define BCR1800_DTR(n) (1 << ((n) & 7))	/* DTR for channels 0-7 sync */
+
+/*
+ * Channel commands (CCR).
+ */
+#define CCR_CLRCH  0x40		/* clear channel */
+#define CCR_INITCH 0x20		/* initialize channel */
+#define CCR_RSTALL 0x10		/* reset all channels */
+#define CCR_ENTX   0x08		/* enable transmitter */
+#define CCR_DISTX  0x04		/* disable transmitter */
+#define CCR_ENRX   0x02		/* enable receiver */
+#define CCR_DISRX  0x01		/* disable receiver */
+#define CCR_CLRT1  0xc0		/* clear timer 1 */
+#define CCR_CLRT2  0xa0		/* clear timer 2 */
+#define CCR_CLRRCV 0x90		/* clear receiver */
+#define CCR_CLRTX  0x88		/* clear transmitter */
+
+/*
+ * Interrupt enable register (IER) bits.
+ */
+#define IER_MDM    0x80		/* modem status changed */
+#define IER_RET    0x20		/* receive exception timeout */
+#define IER_RXD    0x08		/* data received */
+#define IER_TIMER  0x04		/* timer expired */
+#define IER_TXMPTY 0x02		/* transmitter empty */
+#define IER_TXD    0x01		/* data transmitted */
+
+/*
+ * Modem signal values register bits (MSVR).
+ */
+#define MSV_DSR    0x80		/* state of Data Set Ready input */
+#define MSV_CD     0x40		/* state of Carrier Detect input */
+#define MSV_CTS    0x20		/* state of Clear to Send input */
+#define MSV_TXCOUT 0x10		/* TXCout/DTR pin output flag */
+#define MSV_PORTID 0x04		/* device is CL-CD2401 (not 2400) */
+#define MSV_DTR    0x02		/* state of Data Terminal Ready output */
+#define MSV_RTS    0x01		/* state of Request to Send output */
+#define MSV_BITS "\20\1rts\2dtr\3cd2400\5txcout\6cts\7cd\10dsr"
+
+/*
+ * DMA buffer status register bits (DMABSTS).
+ */
+#define DMABSTS_TDALIGN 0x80	/* internal data alignment in transmit FIFO */
+#define DMABSTS_RSTAPD  0x40	/* reset append mode */
+#define DMABSTS_CRTTBUF 0x20	/* internal current transmit buffer in use */
+#define DMABSTS_APPEND  0x10	/* append buffer is in use */
+#define DMABSTS_NTBUF   0x08	/* next transmit buffer is B (not A) */
+#define DMABSTS_TBUSY   0x04	/* current transmit buffer is in use */
+#define DMABSTS_NRBUF   0x02	/* next receive buffer is B (not A) */
+#define DMABSTS_RBUSY   0x01	/* current receive buffer is in use */
+
+/*
+ * Buffer status register bits ([AB][RT]BSTS).
+ */
+#define BSTS_BUSERR 0x80	/* bus error */
+#define BSTS_EOFR   0x40	/* end of frame */
+#define BSTS_EOBUF  0x20	/* end of buffer */
+#define BSTS_APPEND 0x08	/* append mode */
+#define BSTS_INTR   0x02	/* interrupt required */
+#define BSTS_OWN24  0x01	/* buffer is (free to be) used by CD2400 */
+#define BSTS_BITS "\20\1own24\2intr\4append\6eobuf\7eofr\10buserr"
+
+/*
+ * Receive interrupt status register (RISR) bits.
+ */
+#define RIS_OVERRUN   0x0008	/* overrun error */
+#define RIS_BB        0x0800	/* buffer B status (not A) */
+#define RIS_EOBUF     0x2000	/* end of buffer reached */
+#define RIS_EOFR      0x4000	/* frame reception complete */
+#define RIS_BUSERR    0x8000	/* bus error */
+
+#define RISH_CLRDCT   0x0001	/* X.21 clear detect */
+#define RISH_RESIND   0x0004	/* residual indication */
+#define RISH_CRCERR   0x0010	/* CRC error */
+#define RISH_RXABORT  0x0020	/* abort sequence received */
+#define RISH_EOFR     0x0040	/* complete frame received */
+#define RISH_BITS "\20\1clrdct\3resind\4overrun\5crcerr\6rxabort\7eofr\14bb\16eobuf\17eofr\20buserr"
+
+#define RISA_BREAK    0x0001	/* break signal detected */
+#define RISA_FRERR    0x0002	/* frame error (bad stop bits) */
+#define RISA_PARERR   0x0004	/* parity error */
+#define RISA_SCMASK   0x0070	/* special character detect mask */
+#define RISA_SCHR1    0x0010	/* special character 1 detected */
+#define RISA_SCHR2    0x0020	/* special character 2 detected */
+#define RISA_SCHR3    0x0030	/* special character 3 detected */
+#define RISA_SCHR4    0x0040	/* special character 4 detected */
+#define RISA_SCRANGE  0x0070	/* special character in range detected */
+#define RISA_TIMEOUT  0x0080	/* receive timeout, no data */
+#define RISA_BITS "\20\1break\2frerr\3parerr\4overrun\5schr1\6schr2\7schr4\10timeout\14bb\16eobuf\17eofr\20buserr"
+
+#define RISB_CRCERR   0x0010	/* CRC error */
+#define RISB_RXABORT  0x0020	/* abort sequence received */
+#define RISB_EOFR     0x0040	/* complete frame received */
+
+#define RISX_LEADCHG  0x0001	/* CTS lead change */
+#define RISX_PARERR   0x0004	/* parity error */
+#define RISX_SCMASK   0x0070	/* special character detect mask */
+#define RISX_SCHR1    0x0010	/* special character 1 detected */
+#define RISX_SCHR2    0x0020	/* special character 2 detected */
+#define RISX_SCHR3    0x0030	/* special character 3 detected */
+#define RISX_ALLZERO  0x0040	/* all 0 condition detected */
+#define RISX_ALLONE   0x0050	/* all 1 condition detected */
+#define RISX_ALTOZ    0x0060	/* alternating 1 0 condition detected */
+#define RISX_SYN      0x0070	/* SYN detected */
+#define RISX_LEAD     0x0080	/* leading value */
+
+/*
+ * Channel mode register (CMR) bits.
+ */
+#define CMR_RXDMA     0x80	/* DMA receive transfer mode */
+#define CMR_TXDMA     0x40	/* DMA transmit transfer mode */
+#define CMR_HDLC      0x00	/* HDLC protocol mode */
+#define CMR_BISYNC    0x01	/* BISYNC protocol mode */
+#define CMR_ASYNC     0x02	/* ASYNC protocol mode */
+#define CMR_X21       0x03	/* X.21 protocol mode */
+
+/*
+ * Modem interrupt status register (MISR) bits.
+ */
+#define MIS_CDSR      0x80	/* DSR changed */
+#define MIS_CCD       0x40	/* CD changed */
+#define MIS_CCTS      0x20	/* CTS changed */
+#define MIS_CGT2      0x02	/* GT2 timer expired */
+#define MIS_CGT1      0x01	/* GT1 timer expired */
+#define MIS_BITS "\20\1gt1\2gt2\6ccts\7ccd\10cdsr"
+
+/*
+ * Transmit interrupt status register (TISR) bits.
+ */
+#define TIS_BUSERR    0x80	/* Bus error */
+#define TIS_EOFR      0x40	/* End of frame */
+#define TIS_EOBUF     0x20	/* end of transmit buffer reached */
+#define TIS_UNDERRUN  0x10	/* transmit underrun */
+#define TIS_BB        0x08	/* buffer B status (not A) */
+#define TIS_TXEMPTY   0x02	/* transmitter empty */
+#define TIS_TXDATA    0x01	/* transmit data below threshold */
+#define TIS_BITS "\20\1txdata\2txempty\4bb\5underrun\6eobuf\7eofr\10buserr"
+
+/*
+ * Local interrupt vector register (LIVR) bits.
+ */
+#define LIV_EXCEP     0
+#define LIV_MODEM     1
+#define LIV_TXDATA    2
+#define LIV_RXDATA    3
+
+/*
+ * Transmit end of interrupt registers (TEOIR) bits.
+ */
+#define TEOI_TERMBUFF  0x80	/* force current buffer to be discarded */
+#define TEOI_EOFR      0x40	/* end of frame in interrupt mode */
+#define TEOI_SETTM2    0x20	/* set general timer 2 in sync mode */
+#define TEOI_SETTM1    0x10	/* set general timer 1 in sync mode */
+#define TEOI_NOTRANSF  0x08	/* no transfer of data on this interrupt */
+
+/*
+ * Receive end of interrupt registers (REOIR) bits.
+ */
+#define REOI_TERMBUFF  0x80	/* force current buffer to be terminated */
+#define REOI_DISCEXC   0x40	/* discard exception character */
+#define REOI_SETTM2    0x20	/* set general timer 2 */
+#define REOI_SETTM1    0x10	/* set general timer 1 */
+#define REOI_NOTRANSF  0x08	/* no transfer of data */
+#define REOI_GAP_MASK  0x07	/* optional gap size to leave in buffer */
+
+/*
+ * Special transmit command register (STCR) bits.
+ */
+#define STC_ABORTTX   0x40	/* abort transmission (HDLC mode) */
+#define STC_APPDCMP   0x20	/* append complete (async DMA mode) */
+#define STC_SNDSPC    0x08	/* send special characters (async mode) */
+#define STC_SSPC_MASK 0x07	/* special character select */
+#define STC_SSPC_1    0x01	/* send special character #1 */
+#define STC_SSPC_2    0x02	/* send special character #2 */
+#define STC_SSPC_3    0x03	/* send special character #3 */
+#define STC_SSPC_4    0x04	/* send special character #4 */
+
+/*
+ * Channel status register (CSR) bits, asynchronous mode.
+ */
+#define CSRA_RXEN    0x80       /* receiver enable */
+#define CSRA_RXFLOFF 0x40       /* receiver flow off */
+#define CSRA_RXFLON  0x20       /* receiver flow on */
+#define CSRA_TXEN    0x08       /* transmitter enable */
+#define CSRA_TXFLOFF 0x04       /* transmitter flow off */
+#define CSRA_TXFLON  0x02       /* transmitter flow on */
+#define CSRA_BITS "\20\2txflon\3txfloff\4txen\6rxflon\7rxfloff\10rxen"
diff --git a/sys/dev/cx/if_cx.c b/sys/dev/cx/if_cx.c
new file mode 100644
index 0000000..db7e283
--- /dev/null
+++ b/sys/dev/cx/if_cx.c
@@ -0,0 +1,3240 @@
+/*
+ * Cronyx-Sigma adapter driver for FreeBSD.
+ * Supports PPP/HDLC and Cisco/HDLC protocol in synchronous mode,
+ * and asyncronous channels with full modem control.
+ * Keepalive protocol implemented in both Cisco and PPP modes.
+ *
+ * Copyright (C) 1994-2002 Cronyx Engineering.
+ * Author: Serge Vakulenko, <vak@cronyx.ru>
+ *
+ * Copyright (C) 1999-2003 Cronyx Engineering.
+ * Rewritten on DDK, ported to NETGRAPH, rewritten for FreeBSD 3.x-5.x by
+ * Kurakin Roman, <rik@cronyx.ru>
+ *
+ * This software is distributed with NO WARRANTIES, not even the implied
+ * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Authors grant any other persons or organisations a permission to use,
+ * modify and redistribute this software in source and binary forms,
+ * as long as this message is kept with the software, all derivative
+ * works or modified versions.
+ *
+ * Cronyx Id: if_cx.c,v 1.1.2.18 2003/11/27 14:30:03 rik Exp $
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+
+#if __FreeBSD_version >= 500000
+#   define NCX 1
+#else
+#   include "cx.h"
+#endif
+
+#if NCX > 0
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/proc.h>
+#include <sys/mbuf.h>
+#include <sys/sockio.h>
+#include <sys/malloc.h>
+#include <sys/socket.h>
+#include <sys/conf.h>
+#include <sys/errno.h>
+#include <sys/tty.h>
+#if __FreeBSD_version >= 400000
+#   include <sys/bus.h>
+#   include <machine/bus.h>
+#   include <sys/rman.h>
+#   include <isa/isavar.h>
+#endif
+#include <sys/fcntl.h>
+#include <sys/interrupt.h>
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <net/if.h>
+#include <machine/cpufunc.h>
+#include <machine/cserial.h>
+#include <machine/clock.h>
+#if __FreeBSD_version < 500000
+#include <machine/ipl.h>
+#include <i386/isa/isa_device.h>
+#endif
+#if __FreeBSD_version >= 400000
+#   include <machine/resource.h>
+#if __FreeBSD_version <= 501000
+#       include <i386/isa/intr_machdep.h>
+#   endif
+#endif
+#if __FreeBSD_version >= 500000
+#   include <dev/cx/machdep.h>
+#   include <dev/cx/cxddk.h>
+#   include <dev/cx/cronyxfw.h>
+#else
+#   include <i386/isa/cronyx/machdep.h>
+#   include <i386/isa/cronyx/cxddk.h>
+#   include <i386/isa/cronyx/cronyxfw.h>
+#endif
+#include "opt_ng_cronyx.h"
+#ifdef NETGRAPH_CRONYX
+#   include "opt_netgraph.h"
+#   include <netgraph/ng_message.h>
+#   include <netgraph/netgraph.h>
+#   if __FreeBSD_version >= 500000
+#       include <dev/cx/ng_cx.h>
+#   else
+#       include <netgraph/ng_cx.h>
+#   endif
+#else
+#   include <net/if_types.h>
+#   if __FreeBSD_version < 500000
+#   include "sppp.h"
+#   if NSPPP <= 0
+#	error The device cp requires sppp or netgraph.
+#   endif
+#   endif
+#   include <net/if_sppp.h>
+#   define PP_CISCO IFF_LINK2
+#if __FreeBSD_version < 400000
+#   include <bpfilter.h>
+#   if NBPFILTER > 0
+#      include <net/bpf.h>
+#   endif
+#else
+#   if __FreeBSD_version < 500000
+#       include <bpf.h>
+#   endif
+#   include <net/bpf.h>
+#   define NBPFILTER NBPF
+#endif
+#endif
+
+#define CX_DEBUG(d,s)	({if (d->chan->debug) {\
+				printf ("%s: ", d->name); printf s;}})
+#define CX_DEBUG2(d,s)	({if (d->chan->debug>1) {\
+				printf ("%s: ", d->name); printf s;}})
+
+#define UNIT(d)         (minor(d) & 0x3f)
+#define IF_CUNIT(d)     (minor(d) & 0x40)
+#define UNIT_CTL        0x3f
+#define CALLOUT(d)      (minor(d) & 0x80)
+#define CDEV_MAJOR	42
+
+typedef struct _async_q {
+	int beg;
+	int end;
+	#define BF_SZ 14400
+	int buf[BF_SZ+1];
+} async_q;
+
+#define AQ_GSZ(q)	((BF_SZ + (q)->end - (q)->beg)%BF_SZ)
+#define AQ_PUSH(q,c)	{*((q)->buf + (q)->end) = c;\
+			(q)->end = ((q)->end + 1)%BF_SZ;}
+#define AQ_POP(q,c)	{c = *((q)->buf + (q)->beg);\
+			(q)->beg = ((q)->beg + 1)%BF_SZ;}
+
+#if __FreeBSD_version >= 400000
+static void cx_identify		__P((driver_t *, device_t));
+static int cx_probe		__P((device_t));
+static int cx_attach		__P((device_t));
+static int cx_detach		__P((device_t));
+
+static device_method_t cx_isa_methods [] = {
+	DEVMETHOD(device_identify,	cx_identify),
+	DEVMETHOD(device_probe,		cx_probe),
+	DEVMETHOD(device_attach,	cx_attach),
+	DEVMETHOD(device_detach,	cx_detach),
+	{0, 0}
+};
+
+typedef struct _bdrv_t {
+	cx_board_t	*board;
+	struct resource	*base_res;
+	struct resource	*drq_res;
+	struct resource	*irq_res;
+	int		base_rid;
+	int		drq_rid;
+	int		irq_rid;
+	void		*intrhand;
+} bdrv_t;
+
+static driver_t cx_isa_driver = {
+	"cx",
+	cx_isa_methods,
+	sizeof (bdrv_t),
+};
+
+static devclass_t cx_devclass;
+#endif
+
+typedef struct _drv_t {
+	char name [8];
+	cx_chan_t *chan;
+	cx_board_t *board;
+	cx_buf_t buf;
+	struct tty tty;
+	struct callout_handle dcd_timeout_handle;
+	unsigned dtrwait;
+	unsigned dtroff;
+	unsigned callout;
+	unsigned lock;
+	int open_dev;
+	int cd;
+	int running;
+	struct	callout_handle dtr_timeout_handle;
+#ifdef NETGRAPH
+	char	nodename [NG_NODELEN+1];
+	hook_p	hook;
+	hook_p	debug_hook;
+	node_p	node;
+	struct	ifqueue lo_queue;
+	struct	ifqueue hi_queue;
+	short	timeout;
+	struct	callout_handle timeout_handle;
+#else
+	struct sppp pp;
+#endif
+#if __FreeBSD_version >= 400000
+	dev_t  devt[3];
+#endif
+	async_q aqueue;
+	#define CX_READ 1
+	#define CX_WRITE 2
+	int intr_action;
+	short atimeout;
+} drv_t;
+
+extern long csigma_fw_len;
+extern const char *csigma_fw_version;
+extern const char *csigma_fw_date;
+extern const char *csigma_fw_copyright;
+extern const cr_dat_tst_t csigma_fw_tvec[];
+extern const u_char csigma_fw_data[];
+static void cx_oproc (struct tty *tp);
+static int cx_param (struct tty *tp, struct termios *t);
+static void cx_stop (struct tty *tp, int flag);
+static void cx_dtrwakeup (void *a);
+static void cx_receive (cx_chan_t *c, char *data, int len);
+static void cx_transmit (cx_chan_t *c, void *attachment, int len);
+static void cx_error (cx_chan_t *c, int data);
+static void cx_modem (cx_chan_t *c);
+static void cx_up (drv_t *d);
+static void cx_start (drv_t *d);
+static void disc_optim(struct tty *tp, struct termios *t);
+#if __FreeBSD_version < 500000
+static swihand_t cx_softintr;
+#else
+static void cx_softintr (void *);
+static void *cx_slow_ih;
+static void *cx_fast_ih;
+#endif
+static void cx_down (drv_t *d);
+static void cx_watchdog (drv_t *d);
+static void cx_carrier (void *arg);
+
+#ifdef NETGRAPH
+extern struct ng_type typestruct;
+#else
+static void cx_ifstart (struct ifnet *ifp);
+static void cx_tlf (struct sppp *sp);
+static void cx_tls (struct sppp *sp);
+static void cx_ifwatchdog (struct ifnet *ifp);
+static int cx_sioctl (struct ifnet *ifp, u_long cmd, caddr_t data);
+static void cx_initialize (void *softc);
+#endif
+
+static cx_board_t *adapter [NCX];
+static drv_t *channel [NCX*NCHAN];
+static struct callout_handle led_timo [NCX];
+static struct callout_handle timeout_handle;
+#if __FreeBSD_version >= 400000
+	extern struct cdevsw cx_cdevsw;
+#endif
+
+static int MY_SOFT_INTR;
+
+/*
+ * Print the mbuf chain, for debug purposes only.
+ */
+static void printmbuf (struct mbuf *m)
+{
+	printf ("mbuf:");
+	for (; m; m=m->m_next) {
+		if (m->m_flags & M_PKTHDR)
+			printf (" HDR %d:", m->m_pkthdr.len);
+		if (m->m_flags & M_EXT)
+			printf (" EXT:");
+		printf (" %d", m->m_len);
+	}
+	printf ("\n");
+}
+
+/*
+ * Make an mbuf from data.
+ */
+static struct mbuf *makembuf (void *buf, u_int len)
+{
+	struct mbuf *m, *o, *p;
+
+	MGETHDR (m, M_DONTWAIT, MT_DATA);
+
+	if (! m)
+		return 0;
+
+	if (len >= MINCLSIZE)
+		MCLGET (m, M_DONTWAIT);
+
+	m->m_pkthdr.len = len;
+	m->m_len = 0;
+
+	p = m;
+	while (len) {
+		u_int n = M_TRAILINGSPACE (p);
+		if (n > len)
+			n = len;
+		if (! n) {
+			/* Allocate new mbuf. */
+			o = p;
+			MGET (p, M_DONTWAIT, MT_DATA);
+			if (! p) {
+				m_freem (m);
+				return 0;
+			}
+			if (len >= MINCLSIZE)
+				MCLGET (p, M_DONTWAIT);
+			p->m_len = 0;
+			o->m_next = p;
+
+			n = M_TRAILINGSPACE (p);
+			if (n > len)
+				n = len;
+		}
+		bcopy (buf, mtod (p, caddr_t) + p->m_len, n);
+
+		p->m_len += n;
+		buf = n + (char*) buf;
+		len -= n;
+	}
+	return m;
+}
+
+/*
+ * Recover after lost transmit interrupts.
+ */
+static void cx_timeout (void *arg)
+{
+	drv_t *d;
+	int s, i;
+
+	for (i=0; i<NCX*NCHAN; ++i) {
+		d = channel[i];
+		if (! d)
+			continue;
+		s = splhigh ();
+		if (d->atimeout == 1 && d->tty.t_state & TS_BUSY) {
+			d->tty.t_state &= ~TS_BUSY;
+			if (d->tty.t_dev) {
+				d->intr_action |= CX_WRITE;
+				MY_SOFT_INTR = 1;
+#if __FreeBSD_version >= 500000
+				swi_sched (cx_fast_ih, 0);
+#else
+				setsofttty ();
+#endif
+			}
+			CX_DEBUG (d, ("cx_timeout\n"));
+		}
+		if (d->atimeout)
+			d->atimeout--;
+		splx (s);
+	}
+	timeout_handle = timeout (cx_timeout, 0, hz*5);
+}
+
+static void cx_led_off (void *arg)
+{
+	cx_board_t *b = arg;
+	int s = splhigh ();
+
+	cx_led (b, 0);
+	led_timo[b->num].callout = 0;
+	splx (s);
+}
+
+/*
+ * Activate interupt handler from DDK.
+ */
+#if __FreeBSD_version >= 400000
+static void cx_intr (void *arg)
+{
+	bdrv_t *bd = arg;
+	cx_board_t *b = bd->board;
+#else
+static void cx_intr (int bnum)
+{
+	cx_board_t *b = adapter [bnum];
+#endif
+	int s = splhigh ();
+
+	/* Turn LED on. */
+	cx_led (b, 1);
+
+	cx_int_handler (b);
+
+	/* Turn LED off 50 msec later. */
+	if (! led_timo[b->num].callout)
+		led_timo[b->num] = timeout (cx_led_off, b, hz/20);
+	splx (s);
+}
+
+static int probe_irq (cx_board_t *b, int irq)
+{
+	int mask, busy, cnt;
+
+	/* Clear pending irq, if any. */
+	cx_probe_irq (b, -irq);
+	DELAY (100);
+	for (cnt=0; cnt<5; ++cnt) {
+		/* Get the mask of pending irqs, assuming they are busy.
+		 * Activate the adapter on given irq. */
+		busy = cx_probe_irq (b, irq);
+		DELAY (100);
+
+		/* Get the mask of active irqs.
+		 * Deactivate our irq. */
+		mask = cx_probe_irq (b, -irq);
+		DELAY (100);
+		if ((mask & ~busy) == 1 << irq) {
+			cx_probe_irq (b, 0);
+			/* printf ("cx%d: irq %d ok, mask=0x%04x, busy=0x%04x\n",
+				b->num, irq, mask, busy); */
+			return 1;
+		}
+	}
+	/* printf ("cx%d: irq %d not functional, mask=0x%04x, busy=0x%04x\n",
+		b->num, irq, mask, busy); */
+	cx_probe_irq (b, 0);
+	return 0;
+}
+
+static short porttab [] = {
+	0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0,
+	0x300, 0x320, 0x340, 0x360, 0x380, 0x3a0, 0x3c0, 0x3e0, 0
+};
+static char dmatab [] = { 7, 6, 5, 0 };
+static char irqtab [] = { 5, 10, 11, 7, 3, 15, 12, 0 };
+
+#if __FreeBSD_version >= 400000
+static int cx_is_free_res (device_t dev, int rid, int type, u_long start,
+	u_long end, u_long count)
+{
+	struct resource *res;
+	
+	if (!(res = bus_alloc_resource (dev, type, &rid, start, end, count,
+	    RF_ALLOCATED)))
+		return 0;
+		
+	bus_release_resource (dev, type, rid, res);
+	
+	return 1;
+}
+
+static void cx_identify (driver_t *driver, device_t dev)
+{
+	u_long iobase, rescount;
+	int devcount;
+	device_t *devices;
+	device_t child;
+	devclass_t my_devclass;
+	int i, k;
+
+	if ((my_devclass = devclass_find ("cx")) == NULL)
+		return;
+
+	devclass_get_devices (my_devclass, &devices, &devcount);
+
+	if (devcount == 0) {
+		/* We should find all devices by our self. We could alter other
+		 * devices, but we don't have a choise
+		 */
+		for (i = 0; (iobase = porttab [i]) != 0; i++) {
+			if (!cx_is_free_res (dev, 1, SYS_RES_IOPORT,
+			    iobase, iobase + NPORT, NPORT))
+				continue;
+			if (cx_probe_board (iobase, -1, -1) == 0)
+				continue;
+			
+			devcount++;
+
+			child = BUS_ADD_CHILD (dev, ISA_ORDER_SPECULATIVE, "cx",
+			    -1);
+
+			if (child == NULL)
+				return;
+
+			device_set_desc_copy (child, "Cronyx Sigma");
+			device_set_driver (child, driver);
+			bus_set_resource (child, SYS_RES_IOPORT, 0,
+			    iobase, NPORT);
+
+			if (devcount >= NCX)
+				break;
+		}
+	} else {
+		static short porttab [] = {
+			0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0,
+			0x300, 0x320, 0x340, 0x360, 0x380, 0x3a0, 0x3c0, 0x3e0, 0
+		};
+		/* Lets check user choise.
+		 */
+		for (k = 0; k < devcount; k++) {
+			if (bus_get_resource (devices[k], SYS_RES_IOPORT, 0,
+			    &iobase, &rescount) != 0)
+				continue;
+
+			for (i = 0; porttab [i] != 0; i++) {
+				if (porttab [i] != iobase)
+					continue;
+				if (!cx_is_free_res (devices[k], 1, SYS_RES_IOPORT,
+				    iobase, iobase + NPORT, NPORT))
+					continue;
+				if (cx_probe_board (iobase, -1, -1) == 0)
+					continue;
+				porttab [i] = -1;
+				device_set_desc_copy (devices[k], "Cronyx Sigma");
+				break;
+			}
+
+			if (porttab [i] == 0) {
+				device_delete_child (
+				    device_get_parent (devices[k]),
+				    devices [k]);
+				devices[k] = 0;
+				continue;
+			}
+		}
+		for (k = 0; k < devcount; k++) {
+			if (devices[k] == 0)
+				continue;
+			if (bus_get_resource (devices[k], SYS_RES_IOPORT, 0,
+			    &iobase, &rescount) == 0)
+				continue;
+			for (i = 0; (iobase = porttab [i]) != 0; i++) {
+				if (porttab [i] == -1) {
+					continue;
+				}
+				if (!cx_is_free_res (devices[k], 1, SYS_RES_IOPORT,
+				    iobase, iobase + NPORT, NPORT))
+					continue;
+				if (cx_probe_board (iobase, -1, -1) == 0)
+					continue;
+			
+				bus_set_resource (devices[k], SYS_RES_IOPORT, 0,
+				    iobase, NPORT);
+				porttab [i] = -1;
+				device_set_desc_copy (devices[k], "Cronyx Sigma");
+				break;
+			}
+			if (porttab [i] == 0) {
+				device_delete_child (
+				    device_get_parent (devices[k]),
+				    devices [k]);
+			}
+		}		
+		free (devices, M_TEMP);
+	}
+	
+	return;
+}
+
+static int cx_probe (device_t dev)
+{
+	int unit = device_get_unit (dev);
+	int i;
+	u_long iobase, rescount;
+
+	if (!device_get_desc (dev) ||
+	    strcmp (device_get_desc (dev), "Cronyx Sigma"))
+		return ENXIO;
+	
+	if (bus_get_resource (dev, SYS_RES_IOPORT, 0, &iobase, &rescount) != 0) {
+		printf ("cx%d: Couldn't get IOPORT\n", unit);
+		return ENXIO;
+	}
+
+	if (!cx_is_free_res (dev, 1, SYS_RES_IOPORT,
+	    iobase, iobase + NPORT, NPORT)) {
+		printf ("cx%d: Resource IOPORT isn't free %lx\n", unit, iobase);
+		return ENXIO;
+	}
+		
+	for (i = 0; porttab [i] != 0; i++) {
+		if (porttab [i] == iobase) {
+			porttab [i] = -1;
+			break;
+		}
+	}
+	
+	if (porttab [i] == 0) {
+		return ENXIO;
+	}
+	
+	if (!cx_probe_board (iobase, -1, -1)) {
+		printf ("cx%d: probing for Sigma at %lx faild\n", unit, iobase);
+		return ENXIO;
+	}
+	
+	return 0;
+}
+#else /* __FreeBSD_version < 400000 */
+static int cx_probe (struct isa_device *id)
+{
+	cx_board_t *b;
+	int i;
+
+#ifndef NETGRAPH
+	if (! sppp_attach) {
+		printf ("cx%d: no synchronous PPP driver configured\n",
+			id->id_unit);
+		return 0;
+	}
+#endif
+	if (id->id_iobase < 0) {
+		/* Autodetect the adapter. */
+		for (i=0; ; i++) {
+			if (! porttab[i]) {
+				id->id_iobase = -1;
+				return 0;
+			}
+			id->id_iobase = porttab[i];
+			if (id->id_unit > 0 && adapter[0] && adapter[0]->port == id->id_iobase)
+				continue;
+			if (id->id_unit > 1 && adapter[1] && adapter[1]->port == id->id_iobase)
+				continue;
+			if (! haveseen_isadev (id, CC_IOADDR | CC_QUIET) &&
+ 			    cx_probe_board (id->id_iobase, -1, -1))
+ 				break;
+		}
+	} else if (! cx_probe_board (id->id_iobase, -1, -1))
+		return 0;
+
+	if (id->id_drq < 0) {
+		/* Find available 16-bit DRQ. */
+
+		for (i=0; ; ++i) {
+			if (! dmatab[i]) {
+				printf ("cx%d: no available drq found\n",
+					id->id_unit);
+				id->id_drq = -1;
+				return 0;
+			}
+			id->id_drq = dmatab[i];
+			if (! haveseen_isadev (id, CC_DRQ | CC_QUIET)
+			    && !isa_dma_acquire (id->id_drq))
+ 				break;
+		}
+	}
+
+	b = malloc (sizeof (cx_board_t), M_DEVBUF, M_WAITOK);
+	if (!b) {
+		printf ("cx:%d: Couldn't allocate memory\n", id->id_unit);
+		return (ENXIO);
+	}
+	adapter[id->id_unit] = b;
+	bzero (b, sizeof(cx_board_t));
+
+	if (! cx_open_board (b, id->id_unit, id->id_iobase,
+	    id->id_irq ? ffs (id->id_irq) - 1 : -1, id->id_drq)) {
+		printf ("cx%d: cannot initialize adapter\n", id->id_unit);
+		isa_dma_release (id->id_drq);
+		adapter[id->id_unit] = 0;
+		free (b, M_DEVBUF);
+		return 0;
+	}
+
+	if (id->id_irq) {
+		if (! probe_irq (b, ffs (id->id_irq) - 1))
+			printf ("cx%d: irq %d not functional\n",
+				id->id_unit, ffs (id->id_irq) - 1);
+	} else {
+		/* Find available IRQ. */
+
+		for (i=0; ; ++i) {
+			if (! irqtab[i]) {
+				printf ("cx%d: no available irq found\n",
+					id->id_unit);
+				id->id_irq = -1;
+				isa_dma_release (id->id_drq);
+				adapter[id->id_unit] = 0;
+				free (b, M_DEVBUF);
+				return 0;
+			}
+			id->id_irq = 1 << irqtab[i];
+			if (haveseen_isadev (id, CC_IRQ | CC_QUIET))
+				continue;
+#ifdef KLD_MODULE
+			if (register_intr (irqtab[i], 0, 0, (inthand2_t*)
+			    cx_intr, &net_imask, id->id_unit) != 0)
+				continue;
+			unregister_intr (irqtab[i], (inthand2_t*) cx_intr);
+#endif
+ 			if (probe_irq (b, irqtab[i]))
+ 				break;
+		}
+	}
+	cx_init (b, b->num, b->port, ffs (id->id_irq) - 1, b->dma);
+	cx_setup_board (b, 0, 0, 0);
+
+	return 1;
+}
+#endif /* __FreeBSD_version < 400000 */
+
+/*
+ * The adapter is present, initialize the driver structures.
+ */
+#if __FreeBSD_version < 400000
+static int cx_attach (struct isa_device *id)
+{
+#else
+static int cx_attach (device_t dev)
+{
+	bdrv_t *bd = device_get_softc (dev);
+	u_long iobase, drq, irq, rescount;
+	int unit = device_get_unit (dev);
+	int i;
+	int s;
+#endif
+	cx_board_t *b;
+	cx_chan_t *c;
+	drv_t *d;
+
+#if __FreeBSD_version >= 400000
+	KASSERT ((bd != NULL), ("cx%d: NULL device softc\n", unit));
+	
+	bus_get_resource (dev, SYS_RES_IOPORT, 0, &iobase, &rescount);
+	bd->base_rid = 0;
+	bd->base_res = bus_alloc_resource (dev, SYS_RES_IOPORT, &bd->base_rid,
+		iobase, iobase + NPORT, NPORT, RF_ACTIVE);
+	if (! bd->base_res) {
+		printf ("cx%d: cannot allocate base address\n", unit);
+		return ENXIO;
+	}
+	
+	if (bus_get_resource (dev, SYS_RES_DRQ, 0, &drq, &rescount) != 0) {
+		for (i = 0; (drq = dmatab [i]) != 0; i++) {
+			if (!cx_is_free_res (dev, 1, SYS_RES_DRQ,
+			    drq, drq + 1, 1))
+				continue;
+			bus_set_resource (dev, SYS_RES_DRQ, 0, drq, 1);
+			break;
+		}
+		
+		if (dmatab[i] == 0) {	
+			bus_release_resource (dev, SYS_RES_IOPORT, bd->base_rid,
+				bd->base_res);
+			printf ("cx%d: Couldn't get DRQ\n", unit);
+			return ENXIO;
+		}
+	}
+	
+	bd->drq_rid = 0;
+	bd->drq_res = bus_alloc_resource (dev, SYS_RES_DRQ, &bd->drq_rid,
+		drq, drq + 1, 1, RF_ACTIVE);
+	if (! bd->drq_res) {
+		printf ("cx%d: cannot allocate drq\n", unit);
+		bus_release_resource (dev, SYS_RES_IOPORT, bd->base_rid,
+			bd->base_res);
+		return ENXIO;
+	}	
+	
+	if (bus_get_resource (dev, SYS_RES_IRQ, 0, &irq, &rescount) != 0) {
+		for (i = 0; (irq = irqtab [i]) != 0; i++) {
+			if (!cx_is_free_res (dev, 1, SYS_RES_IRQ,
+			    irq, irq + 1, 1))
+				continue;
+			bus_set_resource (dev, SYS_RES_IRQ, 0, irq, 1);
+			break;
+		}
+		
+		if (irqtab[i] == 0) {	
+			bus_release_resource (dev, SYS_RES_DRQ, bd->drq_rid,
+				bd->drq_res);
+			bus_release_resource (dev, SYS_RES_IOPORT, bd->base_rid,
+				bd->base_res);
+			printf ("cx%d: Couldn't get IRQ\n", unit);
+			return ENXIO;
+		}
+	}
+	
+	bd->irq_rid = 0;
+	bd->irq_res = bus_alloc_resource (dev, SYS_RES_IRQ, &bd->irq_rid,
+		irq, irq + 1, 1, RF_ACTIVE);
+	if (! bd->irq_res) {
+		printf ("cx%d: Couldn't allocate irq\n", unit);
+		bus_release_resource (dev, SYS_RES_DRQ, bd->drq_rid,
+			bd->drq_res);
+		bus_release_resource (dev, SYS_RES_IOPORT, bd->base_rid,
+			bd->base_res);
+		return ENXIO;
+	}
+	
+	b = malloc (sizeof (cx_board_t), M_DEVBUF, M_WAITOK);
+	if (!b) {
+		printf ("cx:%d: Couldn't allocate memory\n", unit);
+		return (ENXIO);
+	}
+	adapter[unit] = b;
+	bzero (b, sizeof(cx_board_t));
+	
+	if (! cx_open_board (b, unit, iobase, irq, drq)) {
+		printf ("cx%d: error loading firmware\n", unit);
+		free (b, M_DEVBUF);
+		bus_release_resource (dev, SYS_RES_IRQ, bd->irq_rid,
+			bd->irq_res);
+		bus_release_resource (dev, SYS_RES_DRQ, bd->drq_rid,
+			bd->drq_res);
+		bus_release_resource (dev, SYS_RES_IOPORT, bd->base_rid,
+			bd->base_res);
+ 		return ENXIO;
+	}
+
+	bd->board = b;
+	
+	if (! probe_irq (b, irq)) {
+		printf ("cx%d: irq %ld not functional\n", unit, irq);
+		bd->board = 0;
+		adapter [unit] = 0;
+		free (b, M_DEVBUF);
+		bus_release_resource (dev, SYS_RES_IRQ, bd->irq_rid,
+			bd->irq_res);
+		bus_release_resource (dev, SYS_RES_DRQ, bd->drq_rid,
+			bd->drq_res);
+		bus_release_resource (dev, SYS_RES_IOPORT, bd->base_rid,
+			bd->base_res);
+ 		return ENXIO;
+	}
+	
+	s = splhigh ();
+	if (bus_setup_intr (dev, bd->irq_res, INTR_TYPE_NET, cx_intr, bd,
+	    &bd->intrhand)) {
+		printf ("cx%d: Can't setup irq %ld\n", unit, irq);
+		bd->board = 0;
+		adapter [unit] = 0;
+		free (b, M_DEVBUF);
+		bus_release_resource (dev, SYS_RES_IRQ, bd->irq_rid,
+			bd->irq_res);
+		bus_release_resource (dev, SYS_RES_DRQ, bd->drq_rid,
+			bd->drq_res);
+		bus_release_resource (dev, SYS_RES_IOPORT, bd->base_rid,
+			bd->base_res);
+		splx (s);
+ 		return ENXIO;		
+	}
+	
+	cx_init (b, b->num, b->port, irq, drq);
+	cx_setup_board (b, 0, 0, 0);
+#else /* __FreeBSD_version >= 400000 */
+	b = adapter[id->id_unit];
+#endif /* __FreeBSD_version >= 400000 */
+
+	printf ("cx%d: <Cronyx-Sigma-%s>\n", b->num, b->name);
+#if __FreeBSD_version < 400000
+	id->id_ointr = cx_intr;
+#endif
+
+	for (c=b->chan; c<b->chan+NCHAN; ++c) {
+#if __FreeBSD_version >= 400000
+		char *dnmt="tty %x";
+		char *dnmc="cua %x";
+#endif
+		if (c->type == T_NONE)
+			continue;
+		d = contigmalloc (sizeof(drv_t), M_DEVBUF, M_WAITOK,
+			0x100000, 0x1000000, 16, 0);
+		channel [b->num*NCHAN + c->num] = d;
+		bzero (d, sizeof(drv_t));
+		sprintf (d->name, "cx%d.%d", b->num, c->num);
+		d->board = b;
+		d->chan = c;
+		d->tty.t_oproc = cx_oproc;
+		d->tty.t_param = cx_param;
+#if __FreeBSD_version >= 400000
+		d->tty.t_stop  = cx_stop;
+#endif
+		d->dtrwait = 3 * hz;	/* Default DTR off timeout is 3 seconds. */
+		d->open_dev = 0;
+		c->sys = d;
+
+		switch (c->type) {
+		case T_SYNC_RS232:
+		case T_SYNC_V35:
+		case T_SYNC_RS449:
+		case T_UNIV:
+		case T_UNIV_RS232:
+		case T_UNIV_RS449:
+		case T_UNIV_V35:
+#ifdef NETGRAPH
+		if (ng_make_node_common (&typestruct, &d->node) != 0) {
+			printf ("%s: cannot make common node\n", d->name);
+			channel [b->num*NCHAN + c->num] = 0;
+			c->sys = 0;
+			contigfree (d, sizeof (d), M_DEVBUF);
+			continue;
+		}
+#if __FreeBSD_version >= 500000
+		NG_NODE_SET_PRIVATE (d->node, d);
+#else
+		d->node->private = d;
+#endif
+		sprintf (d->nodename, "%s%d", NG_CX_NODE_TYPE,
+			 c->board->num*NCHAN + c->num);
+		if (ng_name_node (d->node, d->nodename)) {
+			printf ("%s: cannot name node\n", d->nodename);
+#if __FreeBSD_version >= 500000
+			NG_NODE_UNREF (d->node);
+#else
+			ng_rmnode (d->node);
+			ng_unref (d->node);
+#endif
+			channel [b->num*NCHAN + c->num] = 0;
+			c->sys = 0;
+			contigfree (d, sizeof (d), M_DEVBUF);
+			continue;
+		}
+		d->lo_queue.ifq_maxlen = IFQ_MAXLEN;
+		d->hi_queue.ifq_maxlen = IFQ_MAXLEN;
+#if __FreeBSD_version >= 500000
+		mtx_init (&d->lo_queue.ifq_mtx, "cx_queue_lo", NULL, MTX_DEF);
+		mtx_init (&d->hi_queue.ifq_mtx, "cx_queue_hi", NULL, MTX_DEF);
+#endif		
+#else /*NETGRAPH*/
+		d->pp.pp_if.if_softc    = d;
+#if __FreeBSD_version > 501000
+		if_initname (&d->pp.pp_if, "cx", b->num * NCHAN + c->num);
+#else
+		d->pp.pp_if.if_unit     = b->num * NCHAN + c->num;
+		d->pp.pp_if.if_name     = "cx";
+#endif
+		d->pp.pp_if.if_mtu      = PP_MTU;
+		d->pp.pp_if.if_flags    = IFF_POINTOPOINT | IFF_MULTICAST;
+		d->pp.pp_if.if_ioctl    = cx_sioctl;
+		d->pp.pp_if.if_start    = cx_ifstart;
+		d->pp.pp_if.if_watchdog = cx_ifwatchdog;
+		d->pp.pp_if.if_init     = cx_initialize;
+		sppp_attach (&d->pp.pp_if);
+		if_attach (&d->pp.pp_if);
+		d->pp.pp_tlf            = cx_tlf;
+		d->pp.pp_tls		= cx_tls;
+#if __FreeBSD_version >= 400000 || NBPFILTER > 0
+		/* If BPF is in the kernel, call the attach for it.
+		 * Size of PPP header is 4 bytes. */
+		bpfattach (&d->pp.pp_if, DLT_PPP, 4);
+#endif
+#endif /*NETGRAPH*/
+		}
+		cx_start_chan (c, &d->buf, vtophys (&d->buf));
+		cx_register_receive (c, &cx_receive);
+		cx_register_transmit (c, &cx_transmit);
+		cx_register_error (c, &cx_error);
+		cx_register_modem (c, &cx_modem);
+#if __FreeBSD_version >= 400000
+		dnmt[3] = 'x'+b->num;
+		dnmc[3] = 'x'+b->num;
+		d->devt[0] = make_dev (&cx_cdevsw, b->num*NCHAN + c->num, UID_ROOT, GID_WHEEL, 0644, dnmt, b->num*NCHAN + c->num);
+		d->devt[1] = make_dev (&cx_cdevsw, b->num*NCHAN + c->num + 64, UID_ROOT, GID_WHEEL, 0600, "cx%d", b->num*NCHAN + c->num);
+		d->devt[2] = make_dev (&cx_cdevsw, b->num*NCHAN + c->num + 128, UID_ROOT, GID_WHEEL, 0660, dnmc, b->num*NCHAN + c->num);
+	}
+	splx (s);
+
+	return 0;
+#else /* __FreeBSD_version < 400000 */
+	}
+
+	return 1;
+#endif
+}
+
+#if __FreeBSD_version >= 400000
+static int cx_detach (device_t dev)
+{
+	bdrv_t *bd = device_get_softc (dev);
+	cx_board_t *b = bd->board;
+	cx_chan_t *c;
+	int s = splhigh ();
+	
+	/* Check if the device is busy (open). */
+	for (c = b->chan; c < b->chan + NCHAN; ++c) {
+		drv_t *d = (drv_t*) c->sys;
+
+		if (!d || d->chan->type == T_NONE)
+			continue;
+		if (d->lock) {
+			splx (s);
+			return EBUSY;
+		}
+		if (c->mode == M_ASYNC && (d->tty.t_state & TS_ISOPEN) &&
+		    (d->open_dev|0x2)) {
+			splx (s);
+			return EBUSY;
+		}
+		if (d->running) {
+			splx (s);
+			return EBUSY;
+		}
+	}
+
+	/* Deactivate the timeout routine. And soft interrupt*/
+	if (led_timo[b->num].callout)
+		untimeout (cx_led_off, b, led_timo[b->num]);
+
+	for (c = b->chan; c < b->chan + NCHAN; ++c) {
+		drv_t *d = c->sys;
+
+		if (!d || d->chan->type == T_NONE)
+			continue;
+
+		if (d->dtr_timeout_handle.callout)
+			untimeout (cx_dtrwakeup, d, d->dtr_timeout_handle);
+		if (d->dcd_timeout_handle.callout)
+			untimeout (cx_carrier, c, d->dcd_timeout_handle);
+	}
+	bus_teardown_intr (dev, bd->irq_res, bd->intrhand);
+	bus_deactivate_resource (dev, SYS_RES_IRQ, bd->irq_rid, bd->irq_res);
+	bus_release_resource (dev, SYS_RES_IRQ, bd->irq_rid, bd->irq_res);
+	
+	bus_deactivate_resource (dev, SYS_RES_DRQ, bd->drq_rid, bd->drq_res);
+	bus_release_resource (dev, SYS_RES_DRQ, bd->drq_rid, bd->drq_res);
+	
+	bus_deactivate_resource (dev, SYS_RES_IOPORT, bd->base_rid, bd->irq_res);
+	bus_release_resource (dev, SYS_RES_IOPORT, bd->base_rid, bd->base_res);
+
+	cx_close_board (b);
+
+	/* Detach the interfaces, free buffer memory. */
+	for (c = b->chan; c < b->chan + NCHAN; ++c) {
+		drv_t *d = (drv_t*) c->sys;
+
+		if (!d || d->chan->type == T_NONE)
+			continue;
+#ifdef NETGRAPH
+#if __FreeBSD_version >= 500000
+		if (d->node) {
+			ng_rmnode_self (d->node);
+			NG_NODE_UNREF (d->node);
+			d->node = NULL;
+		}
+		mtx_destroy (&d->lo_queue.ifq_mtx);
+		mtx_destroy (&d->hi_queue.ifq_mtx);
+#else
+		ng_rmnode (d->node);
+		d->node = NULL;
+#endif		
+#else
+#if __FreeBSD_version >= 410000 && NBPFILTER > 0
+		/* Detach from the packet filter list of interfaces. */
+		bpfdetach (&d->pp.pp_if);
+#endif
+		/* Detach from the sync PPP list. */
+		sppp_detach (&d->pp.pp_if);
+
+		if_detach (&d->pp.pp_if);
+#endif		
+		destroy_dev (d->devt[0]);
+		destroy_dev (d->devt[1]);
+		destroy_dev (d->devt[2]);
+	}
+
+	cx_led_off (b);
+	if (led_timo[b->num].callout)
+		untimeout (cx_led_off, b, led_timo[b->num]);
+	splx (s);
+	
+	s = splhigh ();
+	for (c = b->chan; c < b->chan + NCHAN; ++c) {
+		drv_t *d = (drv_t*) c->sys;
+
+		if (!d || d->chan->type == T_NONE)
+			continue;
+		
+		/* Deallocate buffers. */
+		contigfree (d, sizeof(d), M_DEVBUF);
+	}
+	bd->board = 0;
+	adapter [b->num] = 0;
+	free (b, M_DEVBUF);
+	splx (s);
+	
+	return 0;	
+}
+#endif
+
+#ifndef NETGRAPH
+static void cx_ifstart (struct ifnet *ifp)
+{
+        drv_t *d = ifp->if_softc;
+
+	cx_start (d);
+}
+
+static void cx_ifwatchdog (struct ifnet *ifp)
+{
+        drv_t *d = ifp->if_softc;
+
+	cx_watchdog (d);
+}
+
+static void cx_tlf (struct sppp *sp)
+{
+	drv_t *d = sp->pp_if.if_softc;
+
+	CX_DEBUG (d, ("cx_tlf\n"));
+/*	cx_set_dtr (d->chan, 0);*/
+/*	cx_set_rts (d->chan, 0);*/
+	sp->pp_down (sp);
+}
+
+static void cx_tls (struct sppp *sp)
+{
+	drv_t *d = sp->pp_if.if_softc;
+
+	CX_DEBUG (d, ("cx_tls\n"));
+	sp->pp_up (sp);
+}
+
+/*
+ * Initialization of interface.
+ * It seems to be never called by upper level.
+ */
+static void cx_initialize (void *softc)
+{
+	drv_t *d = softc;
+
+	CX_DEBUG (d, ("cx_initialize\n"));
+}
+
+/*
+ * Process an ioctl request.
+ */
+static int cx_sioctl (struct ifnet *ifp, u_long cmd, caddr_t data)
+{
+	drv_t *d = ifp->if_softc;
+	int error, s, was_up, should_be_up;
+
+	/* No socket ioctls while the channel is in async mode. */
+	if (d->chan->type == T_NONE || d->chan->mode == M_ASYNC)
+		return EBUSY;
+
+	/* Socket ioctls on slave subchannels are not allowed. */
+	was_up = (ifp->if_flags & IFF_RUNNING) != 0;
+	error = sppp_ioctl (ifp, cmd, data);
+	if (error)
+		return error;
+
+	if (! (ifp->if_flags & IFF_DEBUG))
+		d->chan->debug = 0;
+	else if (! d->chan->debug)
+		d->chan->debug = 1;
+
+	switch (cmd) {
+	default:           CX_DEBUG2 (d, ("ioctl 0x%lx\n", cmd)); return 0;
+	case SIOCADDMULTI: CX_DEBUG2 (d, ("SIOCADDMULTI\n"));     return 0;
+	case SIOCDELMULTI: CX_DEBUG2 (d, ("SIOCDELMULTI\n"));     return 0;
+	case SIOCSIFFLAGS: CX_DEBUG2 (d, ("SIOCSIFFLAGS\n"));     break;
+	case SIOCSIFADDR:  CX_DEBUG2 (d, ("SIOCSIFADDR\n"));      break;
+	}
+
+	/* We get here only in case of SIFFLAGS or SIFADDR. */
+	s = splhigh ();
+	should_be_up = (ifp->if_flags & IFF_RUNNING) != 0;
+	if (!was_up && should_be_up) {
+		/* Interface goes up -- start it. */
+		cx_up (d);
+		cx_start (d);
+	} else if (was_up && !should_be_up) {
+		/* Interface is going down -- stop it. */
+		/* if ((d->pp.pp_flags & PP_FR) || (ifp->if_flags & PP_CISCO))*/
+		cx_down (d);
+	}
+	splx (s);
+	return 0;
+}
+#endif /*NETGRAPH*/
+
+/*
+ * Stop the interface.  Called on splimp().
+ */
+static void cx_down (drv_t *d)
+{
+	int s = splhigh ();
+	CX_DEBUG (d, ("cx_down\n"));
+	cx_set_dtr (d->chan, 0);
+	cx_set_rts (d->chan, 0);
+	d->running = 0;
+	splx (s);
+}
+
+/*
+ * Start the interface.  Called on splimp().
+ */
+static void cx_up (drv_t *d)
+{
+	int s = splhigh ();
+	CX_DEBUG (d, ("cx_up\n"));
+	cx_set_dtr (d->chan, 1);
+	cx_set_rts (d->chan, 1);
+	d->running = 1;
+	splx (s);
+}
+
+/*
+ * Start output on the (slave) interface.  Get another datagram to send
+ * off of the interface queue, and copy it to the interface
+ * before starting the output.
+ */
+static void cx_send (drv_t *d)
+{
+	struct mbuf *m;
+	u_short len;
+
+	CX_DEBUG2 (d, ("cx_send\n"));
+
+	/* No output if the interface is down. */
+	if (! d->running)
+		return;
+
+	/* No output if the modem is off. */
+	if (! cx_get_dsr (d->chan) && ! cx_get_loop(d->chan))
+		return;
+
+	if (cx_buf_free (d->chan)) {
+		/* Get the packet to send. */
+#ifdef NETGRAPH
+		IF_DEQUEUE (&d->hi_queue, m);
+		if (! m)
+			IF_DEQUEUE (&d->lo_queue, m);
+#else
+		m = sppp_dequeue (&d->pp.pp_if);
+#endif
+		if (! m)
+			return;
+#if (__FreeBSD_version >= 400000 || NBPFILTER > 0) && !defined (NETGRAPH)
+		if (d->pp.pp_if.if_bpf)
+#if __FreeBSD_version >= 500000
+			BPF_MTAP (&d->pp.pp_if, m);
+#else
+			bpf_mtap (&d->pp.pp_if, m);
+#endif
+#endif
+		len = m->m_pkthdr.len;
+		if (! m->m_next)
+			cx_send_packet (d->chan, (u_char*)mtod (m, caddr_t),
+				len, 0);
+		else {
+			u_char buf [DMABUFSZ];
+			m_copydata (m, 0, len, buf);
+			cx_send_packet (d->chan, buf, len, 0);
+		}
+		m_freem (m);
+
+		/* Set up transmit timeout, 10 seconds. */
+#ifdef NETGRAPH
+		d->timeout = 10;
+#else
+		d->pp.pp_if.if_timer = 10;
+#endif
+	}
+#ifndef NETGRAPH
+	d->pp.pp_if.if_flags |= IFF_OACTIVE;
+#endif
+}
+
+/*
+ * Start output on the interface.
+ * Always called on splimp().
+ */
+static void cx_start (drv_t *d)
+{
+	int s = splhigh ();
+	if (d->running) {
+		if (! d->chan->dtr)
+			cx_set_dtr (d->chan, 1);
+		if (! d->chan->rts)
+			cx_set_rts (d->chan, 1);
+		cx_send (d);
+	}
+	splx (s);
+}
+
+/*
+ * Handle transmit timeouts.
+ * Recover after lost transmit interrupts.
+ * Always called on splimp().
+ */
+static void cx_watchdog (drv_t *d)
+{
+	int s = splhigh ();
+	CX_DEBUG (d, ("device timeout\n"));
+	if (d->running) {
+		cx_setup_chan (d->chan);
+		cx_start_chan (d->chan, 0, 0);
+		cx_set_dtr (d->chan, 1);
+		cx_set_rts (d->chan, 1);
+		cx_start (d);
+	}
+	splx (s);
+}
+
+/*
+ * Transmit callback function.
+ */
+static void cx_transmit (cx_chan_t *c, void *attachment, int len)
+{
+	drv_t *d = c->sys;
+
+	if (!d)
+		return;
+		
+	if (c->mode == M_ASYNC) {
+		d->tty.t_state &= ~(TS_BUSY | TS_FLUSH);
+		d->atimeout = 0;
+		if (d->tty.t_dev) {
+			d->intr_action |= CX_WRITE;
+			MY_SOFT_INTR = 1;
+#if __FreeBSD_version >= 500000
+			swi_sched (cx_fast_ih, 0);
+#else
+			setsofttty ();
+#endif
+		}
+		return;
+	}
+#ifdef NETGRAPH
+	d->timeout = 0;
+#else
+	++d->pp.pp_if.if_opackets;
+	d->pp.pp_if.if_flags &= ~IFF_OACTIVE;
+	d->pp.pp_if.if_timer = 0;
+#endif
+	cx_start (d);
+}
+
+/*
+ * Process the received packet.
+ */
+static void cx_receive (cx_chan_t *c, char *data, int len)
+{
+	drv_t *d = c->sys;
+	struct mbuf *m;
+	char *cc = data;
+#if __FreeBSD_version >= 500000 && defined NETGRAPH
+	int error;
+#endif
+
+	if (!d)
+		return;
+		
+	if (c->mode == M_ASYNC) {
+		if (d->tty.t_state & TS_ISOPEN) {
+			async_q *q = &d->aqueue;
+			int size = BF_SZ - 1 - AQ_GSZ (q);
+
+			if (len <= 0 && !size)
+				return;
+
+			if (len > size) {
+			        c->ierrs++;
+				cx_error (c, CX_OVERRUN);
+				len = size - 1;
+			}
+
+			while (len--) {
+				AQ_PUSH (q, *(unsigned char *)cc);
+				cc++;
+			}
+
+			d->intr_action |= CX_READ;
+			MY_SOFT_INTR = 1;
+#if __FreeBSD_version >= 500000
+			swi_sched (cx_fast_ih, 0);
+#else
+			setsofttty ();
+#endif
+		}
+		return;
+	}
+	if (! d->running)
+		return;
+
+	m = makembuf (data, len);
+	if (! m) {
+		CX_DEBUG (d, ("no memory for packet\n"));
+#ifndef NETGRAPH
+		++d->pp.pp_if.if_iqdrops;
+#endif
+		return;
+	}
+	if (c->debug > 1)
+		printmbuf (m);
+#ifdef NETGRAPH
+	m->m_pkthdr.rcvif = 0;
+#if __FreeBSD_version >= 500000
+	NG_SEND_DATA_ONLY (error, d->hook, m);
+#else
+	ng_queue_data (d->hook, m, 0);
+#endif
+#else
+	++d->pp.pp_if.if_ipackets;
+	m->m_pkthdr.rcvif = &d->pp.pp_if;
+#if __FreeBSD_version >= 400000 || NBPFILTER > 0
+	/* Check if there's a BPF listener on this interface.
+	 * If so, hand off the raw packet to bpf. */
+	if (d->pp.pp_if.if_bpf)
+#if __FreeBSD_version >= 500000
+		BPF_TAP (&d->pp.pp_if, data, len);
+#else
+		bpf_tap (&d->pp.pp_if, data, len);
+#endif
+#endif
+	sppp_input (&d->pp.pp_if, m);
+#endif
+}
+
+#define CONDITION(t,tp) (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))\
+	    && (!(tp->t_iflag & BRKINT) || (tp->t_iflag & IGNBRK))\
+	    && (!(tp->t_iflag & PARMRK)\
+		|| (tp->t_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))\
+	    && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))\
+	    && linesw[tp->t_line].l_rint == ttyinput)
+
+/*
+ * Error callback function.
+ */
+static void cx_error (cx_chan_t *c, int data)
+{
+	drv_t *d = c->sys;
+	async_q *q;
+
+	if (!d)
+		return;
+
+	q = &(d->aqueue);
+
+	switch (data) {
+	case CX_FRAME:
+		CX_DEBUG (d, ("frame error\n"));
+		if (c->mode == M_ASYNC && (d->tty.t_state & TS_ISOPEN)
+			&& (AQ_GSZ (q) < BF_SZ - 1)
+			&& (!CONDITION((&d->tty.t_termios), (&d->tty))
+			|| !(d->tty.t_iflag & (IGNPAR | PARMRK)))) {
+			AQ_PUSH (q, TTY_FE);
+			d->intr_action |= CX_READ;
+			MY_SOFT_INTR = 1;
+#if __FreeBSD_version >= 500000
+			swi_sched (cx_fast_ih, 0);
+#else
+			setsofttty ();
+#endif
+		}
+#ifndef NETGRAPH
+		else
+			++d->pp.pp_if.if_ierrors;
+#endif
+		break;
+	case CX_CRC:
+		CX_DEBUG (d, ("crc error\n"));
+		if (c->mode == M_ASYNC && (d->tty.t_state & TS_ISOPEN)
+			&& (AQ_GSZ (q) < BF_SZ - 1)
+			&& (!CONDITION((&d->tty.t_termios), (&d->tty))
+			|| !(d->tty.t_iflag & INPCK)
+			|| !(d->tty.t_iflag & (IGNPAR | PARMRK)))) {
+			AQ_PUSH (q, TTY_PE);
+			d->intr_action |= CX_READ;
+			MY_SOFT_INTR = 1;
+#if __FreeBSD_version >= 500000
+			swi_sched (cx_fast_ih, 0);
+#else
+			setsofttty ();
+#endif
+		}
+#ifndef NETGRAPH
+		else
+			++d->pp.pp_if.if_ierrors;
+#endif
+		break;
+	case CX_OVERRUN:
+		CX_DEBUG (d, ("overrun error\n"));
+#ifdef TTY_OE
+		if (c->mode == M_ASYNC && (d->tty.t_state & TS_ISOPEN)
+			&& (AQ_GSZ (q) < BF_SZ - 1)
+			&& (!CONDITION((&d->tty.t_termios), (&d->tty)))) {
+			AQ_PUSH (q, TTY_OE);
+			d->intr_action |= CX_READ;
+			MY_SOFT_INTR = 1;
+#if __FreeBSD_version >= 500000
+			swi_sched (cx_fast_ih, 0);
+#else
+			setsofttty ();
+#endif
+		}
+#endif
+#ifndef NETGRAPH
+		else {
+			++d->pp.pp_if.if_collisions;
+			++d->pp.pp_if.if_ierrors;
+		}
+#endif
+		break;
+	case CX_OVERFLOW:
+		CX_DEBUG (d, ("overflow error\n"));
+#ifndef NETGRAPH
+		if (c->mode != M_ASYNC)
+			++d->pp.pp_if.if_ierrors;
+#endif
+		break;
+	case CX_UNDERRUN:
+		CX_DEBUG (d, ("underrun error\n"));
+		if (c->mode != M_ASYNC) {
+#ifdef NETGRAPH
+			d->timeout = 0;
+#else
+			++d->pp.pp_if.if_oerrors;
+			d->pp.pp_if.if_flags &= ~IFF_OACTIVE;
+			d->pp.pp_if.if_timer = 0;
+			cx_start (d);
+#endif
+		}
+		break;
+	case CX_BREAK:
+		CX_DEBUG (d, ("break error\n"));
+		if (c->mode == M_ASYNC && (d->tty.t_state & TS_ISOPEN)
+			&& (AQ_GSZ (q) < BF_SZ - 1)
+			&& (!CONDITION((&d->tty.t_termios), (&d->tty))
+			|| !(d->tty.t_iflag & (IGNBRK | BRKINT | PARMRK)))) {
+			AQ_PUSH (q, TTY_BI);
+			d->intr_action |= CX_READ;
+			MY_SOFT_INTR = 1;
+#if __FreeBSD_version >= 500000
+			swi_sched (cx_fast_ih, 0);
+#else
+			setsofttty ();
+#endif
+		}
+#ifndef NETGRAPH
+		else
+			++d->pp.pp_if.if_ierrors;
+#endif
+		break;
+	default:
+		CX_DEBUG (d, ("error #%d\n", data));
+	}
+}
+
+#if __FreeBSD_version < 500000
+static int cx_open (dev_t dev, int flag, int mode, struct proc *p)
+#else
+static int cx_open (dev_t dev, int flag, int mode, struct thread *td)
+#endif
+{
+	int unit = UNIT (dev);
+	drv_t *d;
+	int error;
+
+	if (unit >= NCX*NCHAN || ! (d = channel[unit]))
+		return ENXIO;
+	CX_DEBUG2 (d, ("cx_open unit=%d, flag=0x%x, mode=0x%x\n",
+		    unit, flag, mode));
+
+	if (d->chan->mode != M_ASYNC || IF_CUNIT(dev)) {
+		d->open_dev |= 0x1;
+		return 0;
+	}
+#if __FreeBSD_version >= 400000
+	dev->si_tty = &d->tty;
+#endif
+	d->tty.t_dev = dev;
+again:
+	if (d->dtroff) {
+		error = tsleep (&d->dtrwait, TTIPRI | PCATCH, "cxdtr", 0);
+		if (error)
+			return error;
+		goto again;
+	}
+
+	if ((d->tty.t_state & TS_ISOPEN) && (d->tty.t_state & TS_XCLUDE) &&
+#if __FreeBSD_version >= 500000
+		suser (td))
+#else
+	    p->p_ucred->cr_uid != 0)
+#endif
+		return EBUSY;
+
+	if (d->tty.t_state & TS_ISOPEN) {
+		/*
+		 * Cannot open /dev/cua if /dev/tty already opened.
+		 */
+		if (CALLOUT (dev) && ! d->callout)
+			return EBUSY;
+
+		/*
+		 * Opening /dev/tty when /dev/cua is already opened.
+		 * Wait for close, then try again.
+		 */
+		if (! CALLOUT (dev) && d->callout) {
+			if (flag & O_NONBLOCK)
+				return EBUSY;
+			error = tsleep (d, TTIPRI | PCATCH, "cxbi", 0);
+			if (error)
+				return error;
+			goto again;
+		}
+	} else if (d->lock && ! CALLOUT (dev) && (flag & O_NONBLOCK))
+		/*
+		 * We try to open /dev/tty in non-blocking mode
+		 * while somebody is already waiting for carrier on it.
+		 */
+		return EBUSY;
+	else {
+		ttychars (&d->tty);
+		if (d->tty.t_ispeed == 0) {
+			d->tty.t_iflag = 0;
+			d->tty.t_oflag = 0;
+			d->tty.t_lflag = 0;
+			d->tty.t_cflag = CREAD | CS8 | HUPCL;
+			d->tty.t_ispeed = d->chan->rxbaud;
+			d->tty.t_ospeed = d->chan->txbaud;
+		}
+		if (CALLOUT (dev))
+			d->tty.t_cflag |= CLOCAL;
+		else
+			d->tty.t_cflag &= ~CLOCAL;
+		cx_param (&d->tty, &d->tty.t_termios);
+		ttsetwater (&d->tty);
+	}
+
+	splhigh ();
+	if (! (d->tty.t_state & TS_ISOPEN)) {
+		cx_start_chan (d->chan, 0, 0);
+		cx_set_dtr (d->chan, 1);
+		cx_set_rts (d->chan, 1);
+		d->cd = cx_get_cd (d->chan);
+		if (CALLOUT (dev) || cx_get_cd (d->chan))
+			(*linesw[d->tty.t_line].l_modem) (&d->tty, 1);
+	}
+
+	if (! (flag & O_NONBLOCK) && ! (d->tty.t_cflag & CLOCAL) &&
+	    ! (d->tty.t_state & TS_CARR_ON)) {
+		/* Lock the channel against cxconfig while we are
+		 * waiting for carrier. */
+		d->lock++;
+		error = tsleep (&d->tty.t_rawq, TTIPRI | PCATCH, "cxdcd", 0);
+		/* Unlock the channel. */
+		d->lock--;
+		spl0 ();
+		if (error)
+			goto failed;
+		goto again;
+	}
+
+	error = (*linesw[d->tty.t_line].l_open) (dev, &d->tty);
+	disc_optim (&d->tty, &d->tty.t_termios);
+	spl0 ();
+	if (error) {
+failed:         if (! (d->tty.t_state & TS_ISOPEN)) {
+			splhigh ();
+			cx_set_dtr (d->chan, 0);
+			cx_set_rts (d->chan, 0);
+			if (d->dtrwait) {
+				d->dtr_timeout_handle =
+				    timeout (cx_dtrwakeup, d, d->dtrwait);
+				d->dtroff = 1;
+			}
+			spl0 ();
+		}
+		return error;
+	}
+
+	if (d->tty.t_state & TS_ISOPEN)
+		d->callout = CALLOUT (dev) ? 1 : 0;
+
+	d->open_dev |= 0x2;
+	CX_DEBUG2 (d, ("cx_open done\n"));
+	return 0;
+}
+
+#if __FreeBSD_version < 500000
+static int cx_close (dev_t dev, int flag, int mode, struct proc *p)
+#else
+static int cx_close (dev_t dev, int flag, int mode, struct thread *td)
+#endif
+{
+	drv_t *d = channel [UNIT (dev)];
+	int s;
+
+	CX_DEBUG2 (d, ("cx_close\n"));
+	if ((!(d->open_dev&0x2)) || IF_CUNIT(dev)){
+		d->open_dev &= ~0x1;
+		return 0;
+	}
+	s = splhigh ();
+	(*linesw[d->tty.t_line].l_close) (&d->tty, flag);
+	disc_optim (&d->tty, &d->tty.t_termios);
+
+	/* Disable receiver.
+	 * Transmitter continues sending the queued data. */
+	cx_enable_receive (d->chan, 0);
+
+	/* Clear DTR and RTS. */
+	if ((d->tty.t_cflag & HUPCL) || ! (d->tty.t_state & TS_ISOPEN)) {
+		cx_set_dtr (d->chan, 0);
+		cx_set_rts (d->chan, 0);
+		if (d->dtrwait) {
+			d->dtr_timeout_handle =
+			    timeout (cx_dtrwakeup, d, d->dtrwait);
+			d->dtroff = 1;
+		}
+	}
+	ttyclose (&d->tty);
+	splx (s);
+	d->callout = 0;
+
+	/* Wake up bidirectional opens. */
+	wakeup (d);
+	d->open_dev &= ~0x2;
+
+	return 0;
+}
+
+static int cx_read (dev_t dev, struct uio *uio, int flag)
+{
+	drv_t *d = channel [UNIT (dev)];
+
+	if (d)	CX_DEBUG2 (d, ("cx_read\n"));
+	if (!d || d->chan->mode != M_ASYNC || IF_CUNIT(dev))
+		return EBADF;
+
+	return (*linesw[d->tty.t_line].l_read) (&d->tty, uio, flag);
+}
+
+static int cx_write (dev_t dev, struct uio *uio, int flag)
+{
+	drv_t *d = channel [UNIT (dev)];
+
+	if (d) CX_DEBUG2 (d, ("cx_write\n"));
+	if (!d || d->chan->mode != M_ASYNC || IF_CUNIT(dev))
+		return EBADF;
+
+	return (*linesw[d->tty.t_line].l_write) (&d->tty, uio, flag);
+}
+
+static int cx_modem_status (drv_t *d)
+{
+	int status = 0, s = splhigh ();
+	/* Already opened by someone or network interface is up? */
+	if ((d->chan->mode == M_ASYNC && (d->tty.t_state & TS_ISOPEN) &&
+	    (d->open_dev|0x2)) || (d->chan->mode != M_ASYNC && d->running))
+		status = TIOCM_LE;      /* always enabled while open */
+
+	if (cx_get_dsr (d->chan)) status |= TIOCM_DSR;
+	if (cx_get_cd  (d->chan)) status |= TIOCM_CD;
+	if (cx_get_cts (d->chan)) status |= TIOCM_CTS;
+	if (d->chan->dtr)	  status |= TIOCM_DTR;
+	if (d->chan->rts)	  status |= TIOCM_RTS;
+	splx (s);
+	return status;
+}
+
+#if __FreeBSD_version < 500000
+static int cx_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p)
+#else
+static int cx_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, struct thread *td)
+#endif
+{
+	drv_t *d = channel [UNIT (dev)];
+	cx_chan_t *c;
+	struct serial_statistics *st;
+	int error, s;
+	char mask[16];
+
+	if (!d || !(c = d->chan))
+		return EINVAL;
+		
+	switch (cmd) {
+	case SERIAL_GETREGISTERED:
+	        CX_DEBUG2 (d, ("ioctl: getregistered\n"));
+		bzero (mask, sizeof(mask));
+		for (s=0; s<NCX*NCHAN; ++s)
+			if (channel [s])
+				mask [s/8] |= 1 << (s & 7);
+	        bcopy (mask, data, sizeof (mask));
+		return 0;
+
+	case SERIAL_GETPORT:
+	        CX_DEBUG2 (d, ("ioctl: getport\n"));
+		s = splhigh ();
+	        *(int *)data = cx_get_port (c);
+		splx (s);
+		if (*(int *)data<0)
+			return (EINVAL);
+		else
+			return 0;
+
+	case SERIAL_SETPORT:
+	        CX_DEBUG2 (d, ("ioctl: setproto\n"));
+	        /* Only for superuser! */
+#if __FreeBSD_version < 400000
+	        error = suser (p->p_ucred, &p->p_acflag);
+#elif __FreeBSD_version < 500000
+	        error = suser (p);
+#else /* __FreeBSD_version >= 500000 */
+	        error = suser (td);
+#endif /* __FreeBSD_version >= 500000 */
+	        if (error)
+	                return error;
+
+		s = splhigh ();
+		cx_set_port (c, *(int *)data);
+		splx (s);
+	        return 0;
+
+#ifndef NETGRAPH
+	case SERIAL_GETPROTO:
+	        CX_DEBUG2 (d, ("ioctl: getproto\n"));
+		s = splhigh ();
+	        strcpy ((char*)data, (c->mode == M_ASYNC) ? "async" :
+			/*(d->pp.pp_flags & PP_FR) ? "fr" :*/
+			(d->pp.pp_if.if_flags & PP_CISCO) ? "cisco" : "ppp");
+		splx (s);
+	        return 0;
+
+	case SERIAL_SETPROTO:
+	        CX_DEBUG2 (d, ("ioctl: setproto\n"));
+	        /* Only for superuser! */
+#if __FreeBSD_version < 400000
+	        error = suser (p->p_ucred, &p->p_acflag);
+#elif __FreeBSD_version < 500000
+	        error = suser (p);
+#else /* __FreeBSD_version >= 500000 */
+	        error = suser (td);
+#endif /* __FreeBSD_version >= 500000 */
+	        if (error)
+	                return error;
+	        if (c->mode == M_ASYNC)
+	                return EBUSY;
+		if (d->pp.pp_if.if_flags & IFF_RUNNING)
+			return EBUSY;
+	        if (! strcmp ("cisco", (char*)data)) {
+/*	                d->pp.pp_flags &= ~(PP_FR);*/
+	                d->pp.pp_flags |= PP_KEEPALIVE;
+	                d->pp.pp_if.if_flags |= PP_CISCO;
+/*	        } else if (! strcmp ("fr", (char*)data)) {*/
+/*	                d->pp.pp_if.if_flags &= ~(PP_CISCO);*/
+/*	                d->pp.pp_flags |= PP_FR | PP_KEEPALIVE;*/
+	        } else if (! strcmp ("ppp", (char*)data)) {
+	                d->pp.pp_flags &= ~(/*PP_FR |*/ PP_KEEPALIVE);
+	                d->pp.pp_if.if_flags &= ~(PP_CISCO);
+	        } else
+			return EINVAL;
+	        return 0;
+
+	case SERIAL_GETKEEPALIVE:
+	        CX_DEBUG2 (d, ("ioctl: getkeepalive\n"));
+	        if (/*(d->pp.pp_flags & PP_FR) ||*/
+		    (d->pp.pp_if.if_flags & PP_CISCO) ||
+		    (c->mode == M_ASYNC))
+			return EINVAL;
+		s = splhigh ();
+	        *(int*)data = (d->pp.pp_flags & PP_KEEPALIVE) ? 1 : 0;
+		splx (s);
+	        return 0;
+
+	case SERIAL_SETKEEPALIVE:
+	        CX_DEBUG2 (d, ("ioctl: setkeepalive\n"));
+	        /* Only for superuser! */
+#if __FreeBSD_version < 400000
+	        error = suser (p->p_ucred, &p->p_acflag);
+#elif __FreeBSD_version < 500000
+	        error = suser (p);
+#else /* __FreeBSD_version >= 500000 */
+	        error = suser (td);
+#endif /* __FreeBSD_version >= 500000 */
+	        if (error)
+	                return error;
+	        if (/*(d->pp.pp_flags & PP_FR) ||*/
+			(d->pp.pp_if.if_flags & PP_CISCO))
+			return EINVAL;
+		s = splhigh ();
+	        if (*(int*)data)
+	                d->pp.pp_flags |= PP_KEEPALIVE;
+		else
+	                d->pp.pp_flags &= ~PP_KEEPALIVE;
+		splx (s);
+	        return 0;
+#endif /*NETGRAPH*/
+
+	case SERIAL_GETMODE:
+	        CX_DEBUG2 (d, ("ioctl: getmode\n"));
+		s = splhigh ();
+		*(int*)data = (c->mode == M_ASYNC) ?
+			SERIAL_ASYNC : SERIAL_HDLC;
+		splx (s);
+	        return 0;
+
+	case SERIAL_SETMODE:
+	        CX_DEBUG2 (d, ("ioctl: setmode\n"));
+	        /* Only for superuser! */
+#if __FreeBSD_version < 400000
+	        error = suser (p->p_ucred, &p->p_acflag);
+#elif __FreeBSD_version < 500000
+	        error = suser (p);
+#else /* __FreeBSD_version >= 500000 */
+	        error = suser (td);
+#endif /* __FreeBSD_version >= 500000 */
+	        if (error)
+	                return error;
+
+	        /* Somebody is waiting for carrier? */
+	        if (d->lock)
+	                return EBUSY;
+	        /* /dev/ttyXX is already opened by someone? */
+	        if (c->mode == M_ASYNC && (d->tty.t_state & TS_ISOPEN) &&
+		    (d->open_dev|0x2))
+	                return EBUSY;
+	        /* Network interface is up?
+	         * Cannot change to async mode. */
+	        if (c->mode != M_ASYNC && d->running &&
+	            (*(int*)data == SERIAL_ASYNC))
+	                return EBUSY;
+
+		s = splhigh ();
+		if (c->mode == M_HDLC && *(int*)data == SERIAL_ASYNC) {
+			cx_set_mode (c, M_ASYNC);
+			cx_enable_receive (c, 0);
+			cx_enable_transmit (c, 0);
+		} else if (c->mode == M_ASYNC && *(int*)data == SERIAL_HDLC) {
+			cx_set_mode (c, M_HDLC);
+			cx_enable_receive (c, 1);
+			cx_enable_transmit (c, 1);
+		}
+	        splx (s);
+		return 0;
+
+	case SERIAL_GETSTAT:
+	        CX_DEBUG2 (d, ("ioctl: getestat\n"));
+	        st = (struct serial_statistics*) data;
+		s = splhigh ();
+	        st->rintr  = c->rintr;
+	        st->tintr  = c->tintr;
+	        st->mintr  = c->mintr;
+	        st->ibytes = c->ibytes;
+	        st->ipkts  = c->ipkts;
+	        st->ierrs  = c->ierrs;
+	        st->obytes = c->obytes;
+	        st->opkts  = c->opkts;
+	        st->oerrs  = c->oerrs;
+		splx (s);
+	        return 0;
+
+	case SERIAL_CLRSTAT:
+	        CX_DEBUG2 (d, ("ioctl: clrstat\n"));
+	        /* Only for superuser! */
+#if __FreeBSD_version < 400000
+	        error = suser (p->p_ucred, &p->p_acflag);
+#elif __FreeBSD_version < 500000
+	        error = suser (p);
+#else /* __FreeBSD_version >= 500000 */
+	        error = suser (td);
+#endif /* __FreeBSD_version >= 500000 */
+	        if (error)
+	                return error;
+		s = splhigh ();
+		c->rintr = 0;
+	        c->tintr = 0;
+	        c->mintr = 0;
+	        c->ibytes = 0;
+	        c->ipkts = 0;
+	        c->ierrs = 0;
+	        c->obytes = 0;
+	        c->opkts = 0;
+	        c->oerrs = 0;
+		splx (s);
+	        return 0;
+
+	case SERIAL_GETBAUD:
+	        CX_DEBUG2 (d, ("ioctl: getbaud\n"));
+	        if (c->mode == M_ASYNC)
+	                return EINVAL;
+		s = splhigh ();
+	        *(long*)data = cx_get_baud(c);
+		splx (s);
+	        return 0;
+
+	case SERIAL_SETBAUD:
+	        CX_DEBUG2 (d, ("ioctl: setbaud\n"));
+	        /* Only for superuser! */
+#if __FreeBSD_version < 400000
+	        error = suser (p->p_ucred, &p->p_acflag);
+#elif __FreeBSD_version < 500000
+	        error = suser (p);
+#else /* __FreeBSD_version >= 500000 */
+	        error = suser (td);
+#endif /* __FreeBSD_version >= 500000 */
+	        if (error)
+	                return error;
+	        if (c->mode == M_ASYNC)
+	                return EINVAL;
+		s = splhigh ();
+	        cx_set_baud (c, *(long*)data);
+	        splx (s);
+	        return 0;
+
+	case SERIAL_GETLOOP:
+	        CX_DEBUG2 (d, ("ioctl: getloop\n"));
+	        if (c->mode == M_ASYNC)
+	                return EINVAL;
+		s = splhigh ();
+	        *(int*)data = cx_get_loop (c);
+		splx (s);
+	        return 0;
+
+	case SERIAL_SETLOOP:
+	        CX_DEBUG2 (d, ("ioctl: setloop\n"));
+	        /* Only for superuser! */
+#if __FreeBSD_version < 400000
+	        error = suser (p->p_ucred, &p->p_acflag);
+#elif __FreeBSD_version < 500000
+	        error = suser (p);
+#else /* __FreeBSD_version >= 500000 */
+	        error = suser (td);
+#endif /* __FreeBSD_version >= 500000 */
+	        if (error)
+	                return error;
+	        if (c->mode == M_ASYNC)
+	                return EINVAL;
+		s = splhigh ();
+	        cx_set_loop (c, *(int*)data);
+	        splx (s);
+	        return 0;
+
+	case SERIAL_GETDPLL:
+	        CX_DEBUG2 (d, ("ioctl: getdpll\n"));
+	        if (c->mode == M_ASYNC)
+	                return EINVAL;
+		s = splhigh ();
+	        *(int*)data = cx_get_dpll (c);
+		splx (s);
+	        return 0;
+
+	case SERIAL_SETDPLL:
+	        CX_DEBUG2 (d, ("ioctl: setdpll\n"));
+	        /* Only for superuser! */
+#if __FreeBSD_version < 400000
+	        error = suser (p->p_ucred, &p->p_acflag);
+#elif __FreeBSD_version < 500000
+	        error = suser (p);
+#else /* __FreeBSD_version >= 500000 */
+	        error = suser (td);
+#endif /* __FreeBSD_version >= 500000 */
+	        if (error)
+	                return error;
+	        if (c->mode == M_ASYNC)
+	                return EINVAL;
+		s = splhigh ();
+	        cx_set_dpll (c, *(int*)data);
+	        splx (s);
+	        return 0;
+
+	case SERIAL_GETNRZI:
+	        CX_DEBUG2 (d, ("ioctl: getnrzi\n"));
+	        if (c->mode == M_ASYNC)
+	                return EINVAL;
+		s = splhigh ();
+	        *(int*)data = cx_get_nrzi (c);
+		splx (s);
+	        return 0;
+
+	case SERIAL_SETNRZI:
+	        CX_DEBUG2 (d, ("ioctl: setnrzi\n"));
+	        /* Only for superuser! */
+#if __FreeBSD_version < 400000
+	        error = suser (p->p_ucred, &p->p_acflag);
+#elif __FreeBSD_version < 500000
+	        error = suser (p);
+#else /* __FreeBSD_version >= 500000 */
+	        error = suser (td);
+#endif /* __FreeBSD_version >= 500000 */
+	        if (error)
+	                return error;
+	        if (c->mode == M_ASYNC)
+	                return EINVAL;
+		s = splhigh ();
+	        cx_set_nrzi (c, *(int*)data);
+	        splx (s);
+	        return 0;
+
+	case SERIAL_GETDEBUG:
+	        CX_DEBUG2 (d, ("ioctl: getdebug\n"));
+		s = splhigh ();
+	        *(int*)data = c->debug;
+		splx (s);
+	        return 0;
+
+	case SERIAL_SETDEBUG:
+	        CX_DEBUG2 (d, ("ioctl: setdebug\n"));
+	        /* Only for superuser! */
+#if __FreeBSD_version < 400000
+	        error = suser (p->p_ucred, &p->p_acflag);
+#elif __FreeBSD_version < 500000
+	        error = suser (p);
+#else /* __FreeBSD_version >= 500000 */
+	        error = suser (td);
+#endif /* __FreeBSD_version >= 500000 */
+	        if (error)
+	                return error;
+		s = splhigh ();
+	        c->debug = *(int*)data;
+		splx (s);
+#ifndef	NETGRAPH
+		if (d->chan->debug)
+			d->pp.pp_if.if_flags |= IFF_DEBUG;
+		else
+			d->pp.pp_if.if_flags &= (~IFF_DEBUG);
+#endif
+	        return 0;
+	}
+
+	if (c->mode == M_ASYNC) {
+#if __FreeBSD_version >= 500000
+		error = (*linesw[d->tty.t_line].l_ioctl) (&d->tty, cmd, data, flag, td);
+#else
+		error = (*linesw[d->tty.t_line].l_ioctl) (&d->tty, cmd, data, flag, p);
+#endif
+		disc_optim (&d->tty, &d->tty.t_termios);
+		if (error != ENOIOCTL) {
+			if (error)
+			CX_DEBUG2 (d, ("l_ioctl: 0x%lx, error %d\n", cmd, error));
+			return error;
+		}
+		error = ttioctl (&d->tty, cmd, data, flag);
+		disc_optim (&d->tty, &d->tty.t_termios);
+		if (error != ENOIOCTL) {
+			if (error)
+			CX_DEBUG2 (d, ("ttioctl: 0x%lx, error %d\n", cmd, error));
+			return error;
+		}
+	}
+
+	switch (cmd) {
+	case TIOCSBRK:          /* Start sending line break */
+	        CX_DEBUG2 (d, ("ioctl: tiocsbrk\n"));
+		s = splhigh ();
+		cx_send_break (c, 500);
+		splx (s);
+	        return 0;
+
+	case TIOCCBRK:          /* Stop sending line break */
+	        CX_DEBUG2 (d, ("ioctl: tioccbrk\n"));
+	        return 0;
+
+	case TIOCSDTR:          /* Set DTR */
+	        CX_DEBUG2 (d, ("ioctl: tiocsdtr\n"));
+		s = splhigh ();
+		cx_set_dtr (c, 1);
+		splx (s);
+	        return 0;
+
+	case TIOCCDTR:          /* Clear DTR */
+	        CX_DEBUG2 (d, ("ioctl: tioccdtr\n"));
+		s = splhigh ();
+		cx_set_dtr (c, 0);
+		splx (s);
+	        return 0;
+
+	case TIOCMSET:          /* Set DTR/RTS */
+	        CX_DEBUG2 (d, ("ioctl: tiocmset\n"));
+		s = splhigh ();
+		cx_set_dtr (c, (*(int*)data & TIOCM_DTR) ? 1 : 0);
+		cx_set_rts (c, (*(int*)data & TIOCM_RTS) ? 1 : 0);
+		splx (s);
+	        return 0;
+
+	case TIOCMBIS:          /* Add DTR/RTS */
+	        CX_DEBUG2 (d, ("ioctl: tiocmbis\n"));
+		s = splhigh ();
+		if (*(int*)data & TIOCM_DTR) cx_set_dtr (c, 1);
+		if (*(int*)data & TIOCM_RTS) cx_set_rts (c, 1);
+		splx (s);
+	        return 0;
+
+	case TIOCMBIC:          /* Clear DTR/RTS */
+	        CX_DEBUG2 (d, ("ioctl: tiocmbic\n"));
+		s = splhigh ();
+		if (*(int*)data & TIOCM_DTR) cx_set_dtr (c, 0);
+		if (*(int*)data & TIOCM_RTS) cx_set_rts (c, 0);
+		splx (s);
+	        return 0;
+
+	case TIOCMGET:          /* Get modem status */
+	        CX_DEBUG2 (d, ("ioctl: tiocmget\n"));
+		*(int*)data = cx_modem_status (d);
+	        return 0;
+
+#ifdef TIOCMSDTRWAIT
+	case TIOCMSDTRWAIT:
+	        CX_DEBUG2 (d, ("ioctl: tiocmsdtrwait\n"));
+	        /* Only for superuser! */
+#if __FreeBSD_version < 400000
+	        error = suser (p->p_ucred, &p->p_acflag);
+#elif __FreeBSD_version < 500000
+	        error = suser (p);
+#else /* __FreeBSD_version >= 500000 */
+	        error = suser (td);
+#endif /* __FreeBSD_version >= 500000 */
+		if (error)
+			return error;
+		s = splhigh ();
+		d->dtrwait = *(int*)data * hz / 100;
+		splx (s);
+	        return 0;
+#endif
+
+#ifdef TIOCMGDTRWAIT
+	case TIOCMGDTRWAIT:
+	        CX_DEBUG2 (d, ("ioctl: tiocmgdtrwait\n"));
+		s = splhigh ();
+		*(int*)data = d->dtrwait * 100 / hz;
+		splx (s);
+	        return 0;
+#endif
+	}
+        CX_DEBUG2 (d, ("ioctl: 0x%lx\n", cmd));
+	return ENOTTY;
+}
+
+/*
+ * Wake up opens() waiting for DTR ready.
+ */
+static void cx_dtrwakeup (void *arg)
+{
+	drv_t *d = arg;
+
+	d->dtroff = 0;
+	wakeup (&d->dtrwait);
+}
+
+
+static void
+disc_optim(tp, t)
+	struct tty	*tp;
+	struct termios	*t;
+{
+	if (CONDITION(t,tp))
+		tp->t_state |= TS_CAN_BYPASS_L_RINT;
+	else
+		tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
+}
+
+#if __FreeBSD_version >= 500000
+void cx_softintr (void *unused)
+#else
+void cx_softintr ()
+#endif
+{
+	drv_t *d;
+	async_q *q;
+	int i, s, ic, k;
+	while (MY_SOFT_INTR) {
+		MY_SOFT_INTR = 0;
+		for (i=0; i<NCX*NCHAN; ++i) {
+			d = channel [i];
+			if (!d || !d->chan || d->chan->type == T_NONE
+			    || d->chan->mode != M_ASYNC || !d->tty.t_dev)
+				continue;
+			s = splhigh ();
+			if (d->intr_action & CX_READ) {
+				q = &(d->aqueue);
+				if (d->tty.t_state & TS_CAN_BYPASS_L_RINT) {
+					k = AQ_GSZ(q);
+					if (d->tty.t_rawq.c_cc + k >
+						d->tty.t_ihiwat
+					    && (d->tty.t_cflag & CRTS_IFLOW
+						|| d->tty.t_iflag & IXOFF)
+					    && !(d->tty.t_state & TS_TBLOCK))
+						ttyblock(&d->tty);
+					d->tty.t_rawcc += k;
+					while (k>0) {
+						k--;
+						AQ_POP (q, ic);
+						splx (s);
+						putc (ic, &d->tty.t_rawq);
+						s = splhigh ();
+					}
+					ttwakeup(&d->tty);
+					if (d->tty.t_state & TS_TTSTOP
+					    && (d->tty.t_iflag & IXANY
+						|| d->tty.t_cc[VSTART] ==
+						d->tty.t_cc[VSTOP])) {
+						d->tty.t_state &= ~TS_TTSTOP;
+						d->tty.t_lflag &= ~FLUSHO;
+						d->intr_action |= CX_WRITE;
+					}
+				} else {
+					while (q->end != q->beg) {
+						AQ_POP (q, ic);
+						splx (s);
+						(*linesw[d->tty.t_line].l_rint)
+							(ic, &d->tty);
+						s = splhigh ();
+					}
+				}
+				d->intr_action &= ~CX_READ;
+			}
+			splx (s);
+
+			s = splhigh ();
+			if (d->intr_action & CX_WRITE) {
+				if (d->tty.t_line)
+					(*linesw[d->tty.t_line].l_start) (&d->tty);
+				else
+					cx_oproc (&d->tty);
+				d->intr_action &= ~CX_WRITE;
+			}
+			splx (s);
+
+		}
+	}
+}
+
+/*
+ * Fill transmitter buffer with data.
+ */
+static void cx_oproc (struct tty *tp)
+{
+	int s = splhigh (), k;
+	drv_t *d = channel [UNIT (tp->t_dev)];
+	static u_char buf[DMABUFSZ];
+	u_char *p;
+	u_short len = 0, sublen = 0;
+
+	if (!d) {
+		splx (s);
+		return;
+	}
+		
+	CX_DEBUG2 (d, ("cx_oproc\n"));
+	if (tp->t_cflag & CRTSCTS && (tp->t_state & TS_TBLOCK) && d->chan->rts)
+		cx_set_rts (d->chan, 0);
+	else if (tp->t_cflag & CRTSCTS && ! (tp->t_state & TS_TBLOCK) && ! d->chan->rts)
+		cx_set_rts (d->chan, 1);
+
+	if (! (tp->t_state & (TS_TIMEOUT | TS_TTSTOP))) {
+		/* Start transmitter. */
+		cx_enable_transmit (d->chan, 1);
+
+		/* Is it busy? */
+		if (! cx_buf_free (d->chan)) {
+			tp->t_state |= TS_BUSY;
+			splx (s);
+			return;
+		}
+		if (tp->t_iflag & IXOFF) {
+			p = (buf + (DMABUFSZ/2));
+			sublen = q_to_b (&tp->t_outq, p, (DMABUFSZ/2));
+			k = sublen;
+			while (k--) {
+				/* Send XON/XOFF out of band. */
+				if (*p == tp->t_cc[VSTOP]) {
+					cx_xflow_ctl (d->chan, 0);
+					p++;
+					continue;
+				}
+				if (*p == tp->t_cc[VSTART]) {
+					cx_xflow_ctl (d->chan, 1);
+					p++;
+					continue;
+				}
+				buf[len] = *p;
+				len++;
+				p++;
+			}
+		} else {
+			p = buf;
+			len = q_to_b (&tp->t_outq, p, (DMABUFSZ/2));
+		}
+		if (len) {
+			cx_send_packet (d->chan, buf, len, 0);
+			tp->t_state |= TS_BUSY;
+			d->atimeout = 10;
+			CX_DEBUG2 (d, ("out %d bytes\n", len));
+		}
+	}
+	ttwwakeup (tp);
+	splx (s);
+}
+
+static int cx_param (struct tty *tp, struct termios *t)
+{
+	drv_t *d = channel [UNIT (tp->t_dev)];
+	int s, bits, parity;
+
+	if (!d)
+		return EINVAL;
+		
+	s = splhigh ();
+	if (t->c_ospeed == 0) {
+		/* Clear DTR and RTS. */
+		cx_set_dtr (d->chan, 0);
+		splx (s);
+		CX_DEBUG2 (d, ("cx_param (hangup)\n"));
+		return 0;
+	}
+	CX_DEBUG2 (d, ("cx_param\n"));
+
+	/* Check requested parameters. */
+	if (t->c_ospeed < 300 || t->c_ospeed > 256*1024) {
+		splx (s);
+                return EINVAL;
+	}
+	if (t->c_ispeed && (t->c_ispeed < 300 || t->c_ispeed > 256*1024)) {
+		splx (s);
+                return EINVAL;
+	}
+
+  	/* And copy them to tty and channel structures. */
+	tp->t_ispeed = t->c_ispeed = tp->t_ospeed = t->c_ospeed;
+	tp->t_cflag = t->c_cflag;
+
+	/* Set character length and parity mode. */
+	switch (t->c_cflag & CSIZE) {
+	default:
+	case CS8: bits = 8; break;
+	case CS7: bits = 7; break;
+	case CS6: bits = 6; break;
+	case CS5: bits = 5; break;
+	}
+
+	parity = ((t->c_cflag & PARENB) ? 1 : 0) *
+		 (1 + ((t->c_cflag & PARODD) ? 0 : 1));
+
+	/* Set current channel number. */
+	if (! d->chan->dtr)
+		cx_set_dtr (d->chan, 1);
+
+	disc_optim (&d->tty, &d->tty.t_termios);
+	cx_set_async_param (d->chan, t->c_ospeed, bits, parity, (t->c_cflag & CSTOPB),
+		!(t->c_cflag & PARENB), (t->c_cflag & CRTSCTS),
+		(t->c_iflag & IXON), (t->c_iflag & IXANY),
+		t->c_cc[VSTART], t->c_cc[VSTOP]);
+	splx (s);
+	return 0;
+}
+
+#if __FreeBSD_version < 400000
+static struct tty *cx_devtotty (dev_t dev)
+{
+	int unit = UNIT (dev);
+
+	if (unit == UNIT_CTL || unit >= NCX*NCHAN || ! channel[unit])
+		return 0;
+	return &channel[unit]->tty;
+}
+#endif
+
+/*
+ * Stop output on a line
+ */
+static void cx_stop (struct tty *tp, int flag)
+{
+	drv_t *d = channel [UNIT (tp->t_dev)];
+	int s;
+
+	if (!d)
+		return;
+		
+	s = splhigh ();
+
+	if (tp->t_state & TS_BUSY) {
+		/* Stop transmitter */
+		CX_DEBUG2 (d, ("cx_stop\n"));
+		cx_transmitter_ctl (d->chan, 0);
+	}
+	splx (s);
+}
+
+/*
+ * Process the (delayed) carrier signal setup.
+ */
+static void cx_carrier (void *arg)
+{
+	drv_t *d = arg;
+	cx_chan_t *c = d->chan;
+	int s, cd;
+
+	s = splhigh ();
+	cd = cx_get_cd (c);
+	if (d->cd != cd) {
+		if (cd) {
+			CX_DEBUG (d, ("carrier on\n"));
+			d->cd = 1;
+			splx (s);
+			(*linesw[d->tty.t_line].l_modem) (&d->tty, 1);
+		} else {
+			CX_DEBUG (d, ("carrier loss\n"));
+			d->cd = 0;
+			splx (s);
+			(*linesw[d->tty.t_line].l_modem) (&d->tty, 0);
+		}
+	}
+}
+
+/*
+ * Modem signal callback function.
+ */
+static void cx_modem (cx_chan_t *c)
+{
+	drv_t *d = c->sys;
+
+	if (!d || c->mode != M_ASYNC)
+		return;
+	/* Handle carrier detect/loss. */
+	untimeout (cx_carrier, c, d->dcd_timeout_handle);
+	/* Carrier changed - delay processing DCD for a while
+	 * to give both sides some time to initialize. */
+	d->dcd_timeout_handle = timeout (cx_carrier, d, hz/2);
+}
+
+#if __FreeBSD_version < 400000
+struct isa_driver cxdriver = { cx_probe, cx_attach, "cx" };
+static struct cdevsw cx_cdevsw = {
+	cx_open,	cx_close,	cx_read,	cx_write,
+	cx_ioctl,	cx_stop,	noreset,	cx_devtotty,
+	ttpoll,		nommap,		NULL,		"cx",
+	NULL,		-1,
+};
+#elif  __FreeBSD_version < 500000
+static struct cdevsw cx_cdevsw = {
+	cx_open,	cx_close,	cx_read,	cx_write,
+	cx_ioctl,	ttypoll,	nommap,		nostrategy,
+	"cx",		CDEV_MAJOR,	nodump,		nopsize,
+	D_TTY,		-1
+};
+#elif __FreeBSD_version == 500000
+static struct cdevsw cx_cdevsw = {
+	cx_open,	cx_close,	cx_read,	cx_write,
+	cx_ioctl,	ttypoll,	nommap,		nostrategy,
+	"cx",		CDEV_MAJOR,	nodump,		nopsize,
+	D_TTY,
+	};
+#elif __FreeBSD_version <= 501000 
+static struct cdevsw cx_cdevsw = {
+	.d_open     = cx_open,
+	.d_close    = cx_close,
+	.d_read     = cx_read,
+	.d_write    = cx_write,
+	.d_ioctl    = cx_ioctl,
+	.d_poll     = ttypoll,
+	.d_mmap	    = nommap,
+	.d_strategy = nostrategy,
+	.d_name     = "cx",
+	.d_maj      = CDEV_MAJOR,
+	.d_dump     = nodump,
+	.d_flags    = D_TTY,
+};
+#else /* __FreeBSD_version > 501000 */
+static struct cdevsw cx_cdevsw = {
+	.d_open     = cx_open,
+	.d_close    = cx_close,
+	.d_read     = cx_read,
+	.d_write    = cx_write,
+	.d_ioctl    = cx_ioctl,
+	.d_poll     = ttypoll,
+	.d_name     = "cx",
+	.d_maj      = CDEV_MAJOR,
+	.d_flags    = D_TTY,
+};
+#endif
+
+#ifdef NETGRAPH
+#if __FreeBSD_version >= 500000
+static int ng_cx_constructor (node_p node)
+{
+	drv_t *d = NG_NODE_PRIVATE (node);
+#else
+static int ng_cx_constructor (node_p *node)
+{
+	drv_t *d = (*node)->private;
+#endif
+	CX_DEBUG (d, ("Constructor\n"));
+	return EINVAL;
+}
+
+static int ng_cx_newhook (node_p node, hook_p hook, const char *name)
+{
+	int s;
+#if __FreeBSD_version >= 500000
+	drv_t *d = NG_NODE_PRIVATE (node);
+#else
+	drv_t *d = node->private;
+#endif
+
+	if (d->chan->mode == M_ASYNC)
+		return EINVAL;
+
+	/* Attach debug hook */
+	if (strcmp (name, NG_CX_HOOK_DEBUG) == 0) {
+#if __FreeBSD_version >= 500000
+		NG_HOOK_SET_PRIVATE (hook, NULL);
+#else
+		hook->private = 0;
+#endif
+		d->debug_hook = hook;
+		return 0;
+	}
+
+	/* Check for raw hook */
+	if (strcmp (name, NG_CX_HOOK_RAW) != 0)
+		return EINVAL;
+
+#if __FreeBSD_version >= 500000
+	NG_HOOK_SET_PRIVATE (hook, d);
+#else
+	hook->private = d;
+#endif
+	d->hook = hook;
+	s = splhigh ();
+	cx_up (d);
+	splx (s);
+	return 0;
+}
+
+static int print_modems (char *s, cx_chan_t *c, int need_header)
+{
+	int status = cx_modem_status (c->sys);
+	int length = 0;
+
+	if (need_header)
+		length += sprintf (s + length, "  LE   DTR  DSR  RTS  CTS  CD\n");
+	length += sprintf (s + length, "%4s %4s %4s %4s %4s %4s\n",
+		status & TIOCM_LE  ? "On" : "-",
+		status & TIOCM_DTR ? "On" : "-",
+		status & TIOCM_DSR ? "On" : "-",
+		status & TIOCM_RTS ? "On" : "-",
+		status & TIOCM_CTS ? "On" : "-",
+		status & TIOCM_CD  ? "On" : "-");
+	return length;
+}
+
+static int print_stats (char *s, cx_chan_t *c, int need_header)
+{
+	int length = 0;
+
+	if (need_header)
+		length += sprintf (s + length, "  Rintr   Tintr   Mintr   Ibytes   Ipkts   Ierrs   Obytes   Opkts   Oerrs\n");
+	length += sprintf (s + length, "%7ld %7ld %7ld %8ld %7ld %7ld %8ld %7ld %7ld\n",
+		c->rintr, c->tintr, c->mintr, c->ibytes, c->ipkts,
+		c->ierrs, c->obytes, c->opkts, c->oerrs);
+	return length;
+}
+
+static int print_chan (char *s, cx_chan_t *c)
+{
+	drv_t *d = c->sys;
+	int length = 0;
+
+	length += sprintf (s + length, "cx%d", c->board->num * NCHAN + c->num);
+	if (d->chan->debug)
+		length += sprintf (s + length, " debug=%d", d->chan->debug);
+
+	if (cx_get_baud (c))
+		length += sprintf (s + length, " %ld", cx_get_baud (c));
+	else
+		length += sprintf (s + length, " extclock");
+
+	if (c->mode == M_HDLC) {
+		length += sprintf (s + length, " dpll=%s", cx_get_dpll (c) ? "on" : "off");
+		length += sprintf (s + length, " nrzi=%s", cx_get_nrzi (c) ? "on" : "off");
+	}
+
+	length += sprintf (s + length, " loop=%s", cx_get_loop (c) ? "on\n" : "off\n");
+	return length;
+}
+
+#if __FreeBSD_version >= 500000
+static int ng_cx_rcvmsg (node_p node, item_p item, hook_p lasthook)
+{
+	drv_t *d = NG_NODE_PRIVATE (node);
+	struct ng_mesg *msg;
+#else
+static int ng_cx_rcvmsg (node_p node, struct ng_mesg *msg,
+	const char *retaddr, struct ng_mesg **rptr)
+{
+	drv_t *d = node->private;
+#endif
+	struct ng_mesg *resp = NULL;
+	int error = 0;
+
+	if (!d)
+		return EINVAL;
+		
+	CX_DEBUG (d, ("Rcvmsg\n"));
+#if __FreeBSD_version >= 500000
+	NGI_GET_MSG (item, msg);
+#endif
+	switch (msg->header.typecookie) {
+	default:
+		error = EINVAL;
+		break;
+
+	case NGM_CX_COOKIE:
+		printf ("Don't forget to implement\n");
+		error = EINVAL;
+		break;
+
+	case NGM_GENERIC_COOKIE:
+		switch (msg->header.cmd) {
+		default:
+			error = EINVAL;
+			break;
+
+		case NGM_TEXT_STATUS: {
+			char *s;
+			int l = 0;
+			int dl = sizeof (struct ng_mesg) + 730;
+
+#if __FreeBSD_version >= 500000	
+			NG_MKRESPONSE (resp, msg, dl, M_NOWAIT);
+			if (! resp) {
+				error = ENOMEM;
+				break;
+			}
+#else
+			MALLOC (resp, struct ng_mesg *, dl,
+				M_NETGRAPH, M_NOWAIT);
+			if (! resp) {
+				error = ENOMEM;
+				break;
+			}
+#endif
+			bzero (resp, dl);
+			s = (resp)->data;
+			l += print_chan (s + l, d->chan);
+			l += print_stats (s + l, d->chan, 1);
+			l += print_modems (s + l, d->chan, 1);
+#if __FreeBSD_version < 500000
+			(resp)->header.version = NG_VERSION;
+			(resp)->header.arglen = strlen (s) + 1;
+			(resp)->header.token = msg->header.token;
+			(resp)->header.typecookie = NGM_CX_COOKIE;
+			(resp)->header.cmd = msg->header.cmd;
+#endif
+			strncpy ((resp)->header.cmdstr, "status", NG_CMDSTRLEN);
+			}
+			break;
+		}
+		break;
+	}
+#if __FreeBSD_version >= 500000
+	NG_RESPOND_MSG (error, node, item, resp);
+	NG_FREE_MSG (msg);
+#else
+	*rptr = resp;
+	FREE (msg, M_NETGRAPH);
+#endif
+	return error;
+}
+
+#if __FreeBSD_version >= 500000
+static int ng_cx_rcvdata (hook_p hook, item_p item)
+{
+	drv_t *d = NG_NODE_PRIVATE (NG_HOOK_NODE(hook));
+	struct mbuf *m;
+	meta_p meta;
+#else
+static int ng_cx_rcvdata (hook_p hook, struct mbuf *m, meta_p meta)
+{
+	drv_t *d = hook->node->private;
+#endif
+	struct ifqueue *q;
+	int s;
+
+#if __FreeBSD_version >= 500000
+	NGI_GET_M (item, m);
+	NGI_GET_META (item, meta);
+	NG_FREE_ITEM (item);
+	if (! NG_HOOK_PRIVATE (hook) || ! d) {
+		NG_FREE_M (m);
+		NG_FREE_META (meta);
+#else
+	if (! hook->private || ! d) {
+		NG_FREE_DATA (m,meta);
+#endif
+		return ENETDOWN;
+	}
+	q = (meta && meta->priority > 0) ? &d->hi_queue : &d->lo_queue;
+	s = splhigh ();
+#if __FreeBSD_version >= 500000
+	IF_LOCK (q);
+	if (_IF_QFULL (q)) {
+		_IF_DROP (q);
+		IF_UNLOCK (q);
+		splx (s);
+		NG_FREE_M (m);
+		NG_FREE_META (meta);
+		return ENOBUFS;
+	}
+	_IF_ENQUEUE (q, m);
+	IF_UNLOCK (q);
+#else
+	if (IF_QFULL (q)) {
+		IF_DROP (q);
+		splx (s);
+		NG_FREE_DATA (m, meta);
+		return ENOBUFS;
+	}
+	IF_ENQUEUE (q, m);
+#endif
+	cx_start (d);
+	splx (s);
+	return 0;
+}
+
+static int ng_cx_rmnode (node_p node)
+{
+#if __FreeBSD_version >= 500000
+	drv_t *d = NG_NODE_PRIVATE (node);
+
+	CX_DEBUG (d, ("Rmnode\n"));
+	if (d && d->running) {
+		int s = splhigh ();
+		cx_down (d);
+		splx (s);
+	}
+#ifdef	KLD_MODULE
+	if (node->nd_flags & NG_REALLY_DIE) {
+		NG_NODE_SET_PRIVATE (node, NULL);
+		NG_NODE_UNREF (node);
+	}
+	node->nd_flags &= ~NG_INVALID;
+#endif
+#else /* __FreeBSD_version < 500000 */
+	drv_t *d = node->private;
+	int s;
+
+	s = splhigh ();
+	cx_down (d);
+	splx (s);
+	node->flags |= NG_INVALID;
+	ng_cutlinks (node);
+#ifdef	KLD_MODULE
+	ng_unname (node);
+	ng_unref (node);
+#else
+	node->flags &= ~NG_INVALID;
+#endif
+#endif
+	return 0;
+}
+
+static void ng_cx_watchdog (void *arg)
+{
+	drv_t *d = arg;
+
+	if (d->timeout == 1)
+		cx_watchdog (d);
+	if (d->timeout)
+		d->timeout--;
+	d->timeout_handle = timeout (ng_cx_watchdog, d, hz);
+}
+
+static int ng_cx_connect (hook_p hook)
+{
+#if __FreeBSD_version >= 500000
+	drv_t *d = NG_NODE_PRIVATE (NG_HOOK_NODE (hook));
+#else
+	drv_t *d = hook->node->private;
+#endif
+
+	d->timeout_handle = timeout (ng_cx_watchdog, d, hz);
+	return 0;
+}
+
+static int ng_cx_disconnect (hook_p hook)
+{
+#if __FreeBSD_version >= 500000
+	drv_t *d = NG_NODE_PRIVATE (NG_HOOK_NODE (hook));
+#else
+	drv_t *d = hook->node->private;
+#endif
+	int s;
+
+	s = splhigh ();
+#if __FreeBSD_version >= 500000
+	if (NG_HOOK_PRIVATE (hook))
+#else
+	if (hook->private)
+#endif
+		cx_down (d);
+	splx (s);
+	untimeout (ng_cx_watchdog, d, d->timeout_handle);
+	return 0;
+}
+#endif /*NETGRAPH*/
+
+#ifdef KLD_MODULE
+#if __FreeBSD_version < 400000
+/*
+ * Function called when loading the driver.
+ */
+static int cx_load (void)
+{
+	int i;
+
+	for (i=0;i<NCX; ++i) {
+		struct isa_device id = {-1, &cxdriver, -1, 0, -1, 0, 0, (inthand2_t *)cx_intr, i, 0, 0, 0, 0 ,0 ,1 ,0 ,0};
+
+		disable_intr();
+		if (!cx_probe (&id)) {
+			enable_intr();
+			break;
+		}
+		cx_attach (&id);
+		register_intr ((adapter [i])->irq, 0, 0, (inthand2_t*) cx_intr,
+				&net_imask, id.id_unit);
+		enable_intr();
+	}
+	if (!i) {
+		/* Deactivate the timeout routine. And soft interrupt*/
+		untimeout (cx_timeout, 0, timeout_handle);
+#if __FreeBSD_version >= 500000
+		ithread_remove_handler (cx_fast_ih);
+		ithread_remove_handler (cx_slow_ih);
+#else
+		unregister_swi (SWI_TTY, cx_softintr);
+#endif
+		return ENXIO;
+	}
+	return 0;
+}
+
+/*
+ * Function called when unloading the driver.
+ */
+static int cx_unload (void)
+{
+	int i, s;
+
+	/* Check if the device is busy (open). */
+	for (i=0; i<NCX*NCHAN; ++i) {
+		drv_t *d = channel[i];
+		cx_chan_t *c;
+
+		if (!d || (c=d->chan)->type == T_NONE)
+			continue;
+		if (d->lock)
+			return EBUSY;
+		if (c->mode == M_ASYNC && (d->tty.t_state & TS_ISOPEN) &&
+			(d->open_dev|0x2))
+				return EBUSY;
+		if (d->running)
+				return EBUSY;
+
+	}
+
+	s = splhigh ();
+
+	/* Deactivate the timeout routine. And soft interrupt*/
+	untimeout (cx_timeout, 0, timeout_handle);
+	unregister_swi (SWI_TTY, cx_softintr);
+
+	for (i=0; i<NCX*NCHAN; ++i) {
+		drv_t *d = channel[i];
+		cx_chan_t *c;
+
+		if (!d || (c=d->chan)->type == T_NONE)
+			continue;
+
+		if (d->dtr_timeout_handle.callout)
+			untimeout (cx_dtrwakeup, d, d->dtr_timeout_handle);
+		if (d->dcd_timeout_handle.callout)
+			untimeout (cx_carrier, c, d->dcd_timeout_handle);
+	}
+
+	/* Close all active boards. */
+	for (i=0; i<NCX; ++i) {
+		cx_board_t *b = adapter [i];
+
+		if (!b || ! b->port)
+			continue;
+
+		cx_close_board (b);
+	}
+
+	for (i=0; i<NCX; ++i) {
+		cx_board_t *b = adapter [i];
+
+		if (!b || ! b->port)
+			continue;
+
+		if (led_timo[i].callout)
+			untimeout (cx_led_off, b, led_timo[i]);
+	}
+
+	/* OK to unload the driver, unregister the interrupt first. */
+	for (i=0; i<NCX; ++i) {
+		cx_board_t *b = adapter [i];
+
+		if (!b || ! b->port)
+			continue;
+		/* Disable the interrupt request. */
+		disable_intr();
+		unregister_intr (b->irq, (inthand2_t *)cx_intr);
+		isa_dma_release (b->dma);
+		enable_intr();
+	}
+	splx (s);
+
+	s = splhigh ();
+	/* Detach the interfaces, free buffer memory. */
+	for (i=0; i<NCX*NCHAN; ++i) {
+		drv_t *d = channel[i];
+		cx_chan_t *c;
+
+		if (!d || (c=d->chan)->type == T_NONE)
+			continue;
+
+#ifndef NETGRAPH
+#if NBPFILTER > 0
+		/* Detach from the packet filter list of interfaces. */
+		{
+			struct bpf_if *q, **b = &bpf_iflist;
+
+			while ((q = *b)) {
+				if (q->bif_ifp == d->pp.pp_if) {
+					*b = q->bif_next;
+					free (q, M_DEVBUF);
+				}
+				b = &(q->bif_next);
+			}
+		}
+#endif /* NBPFILTER */
+		/* Detach from the sync PPP list. */
+		sppp_detach (&d->pp.pp_if);
+
+		/* Detach from the system list of interfaces. */
+		{
+			struct ifaddr *ifa;
+			TAILQ_FOREACH (ifa, &d->pp.pp_if.if_addrhead, ifa_link) {
+				TAILQ_REMOVE (&d->pp.pp_if.if_addrhead, ifa, ifa_link);
+				free (ifa, M_IFADDR);
+			}
+			TAILQ_REMOVE (&ifnet, &d->pp.pp_if, if_link);
+		}
+#endif /* !NETGRAPH */
+		/* Deallocate buffers. */
+/*		free (d, M_DEVBUF);*/
+	}
+
+	for (i=0; i<NCX; ++i) {
+		cx_board_t *b = adapter [i];
+		adapter [b->num] = 0;
+		free (b, M_DEVBUF);
+	}
+
+	splx (s);
+
+	return 0;
+}
+
+#define devsw(a)	cdevsw[major((a))]
+#endif /* __FreeBSD_version < 400000 */
+#endif /* KLD_MODULE */
+
+#if __FreeBSD_version < 400000
+#ifdef KLD_MODULE
+static int cx_modevent (module_t mod, int type, void *unused)
+{
+        dev_t dev;
+	int result;
+	static int load_count = 0;
+
+	dev = makedev (CDEV_MAJOR, 0);
+	switch (type) {
+	case MOD_LOAD:
+		if (devsw(dev))
+			return (ENXIO);
+		load_count ++;
+		cdevsw_add (&dev, &cx_cdevsw, NULL);
+ 		timeout_handle = timeout (cx_timeout, 0, hz*5);
+
+		/* Software interrupt. */
+		register_swi (SWI_TTY, cx_softintr);
+
+		result = cx_load ();
+ 		return result;
+	case MOD_UNLOAD:
+		result = cx_unload ();
+		if (result)
+			return result;
+		if (devsw(dev)&&!(load_count-1)) {
+		cdevsw_add (&dev, NULL, NULL);
+		}
+		load_count --;
+		return result;
+	case MOD_SHUTDOWN:
+		break;
+	}
+	return 0;
+}
+#endif /* KLD_MODULE */
+#else /* __FreeBSD_version >= 400000 */
+static int cx_modevent (module_t mod, int type, void *unused)
+{
+        dev_t dev;
+	static int load_count = 0;
+	struct cdevsw *cdsw;
+
+	dev = makedev (CDEV_MAJOR, 0);
+	switch (type) {
+	case MOD_LOAD:
+		if ((cdsw = devsw (dev)) && cdsw->d_maj == CDEV_MAJOR) {
+			printf ("Sigma driver is already in system\n");
+			return (EEXIST);
+		}
+#if __FreeBSD_version >= 500000 && defined NETGRAPH
+		if (ng_newtype (&typestruct))
+			printf ("Failed to register ng_cx\n");
+#endif
+		++load_count;
+#if __FreeBSD_version <= 500000
+		cdevsw_add (&cx_cdevsw);
+#endif
+		timeout_handle = timeout (cx_timeout, 0, hz*5);
+		/* Software interrupt. */
+#if __FreeBSD_version < 500000
+		register_swi (SWI_TTY, cx_softintr);
+#else
+		swi_add(&tty_ithd, "tty:cx", cx_softintr, NULL, SWI_TTY, 0,
+		    &cx_fast_ih);
+		swi_add(&clk_ithd, "tty:cx", cx_softintr, NULL, SWI_TTY, 0,
+		    &cx_slow_ih);
+#endif
+		break;
+	case MOD_UNLOAD:
+		if (load_count == 1) {
+			printf ("Removing device entry for Sigma\n");
+#if __FreeBSD_version <= 500000
+			cdevsw_remove (&cx_cdevsw);
+#endif
+#if __FreeBSD_version >= 500000 && defined NETGRAPH
+			ng_rmtype (&typestruct);
+#endif			
+		}
+		if (timeout_handle.callout)
+			untimeout (cx_timeout, 0, timeout_handle);
+#if __FreeBSD_version >= 500000
+		ithread_remove_handler (cx_fast_ih);
+		ithread_remove_handler (cx_slow_ih);
+#else
+		unregister_swi (SWI_TTY, cx_softintr);
+#endif
+		--load_count;
+		break;
+	case MOD_SHUTDOWN:
+		break;
+	}
+	return 0;
+}
+#endif  /* __FreeBSD_version >= 400000 */
+
+#ifdef NETGRAPH
+static struct ng_type typestruct = {
+#if __FreeBSD_version >= 500000
+	NG_ABI_VERSION,
+#else
+	NG_VERSION,
+#endif
+	NG_CX_NODE_TYPE,
+#if __FreeBSD_version < 500000 && defined KLD_MODULE
+	cx_modevent,
+#else
+	NULL,
+#endif
+	ng_cx_constructor,
+	ng_cx_rcvmsg,
+	ng_cx_rmnode,
+	ng_cx_newhook,
+	NULL,
+	ng_cx_connect,
+	ng_cx_rcvdata,
+#if __FreeBSD_version < 500000
+	NULL,
+#endif
+	ng_cx_disconnect
+};
+
+#if __FreeBSD_version < 400000
+NETGRAPH_INIT_ORDERED (cx, &typestruct, SI_SUB_DRIVERS,\
+	SI_ORDER_MIDDLE + CDEV_MAJOR);
+#endif
+#endif /*NETGRAPH*/
+
+#if __FreeBSD_version >= 500000
+#ifdef NETGRAPH
+MODULE_DEPEND (ng_cx, netgraph, NG_ABI_VERSION, NG_ABI_VERSION, NG_ABI_VERSION);
+#else
+MODULE_DEPEND (isa_cx, sppp, 1, 1, 1);
+#endif
+#ifdef KLD_MODULE
+DRIVER_MODULE (cxmod, isa, cx_isa_driver, cx_devclass, cx_modevent, NULL);
+#else
+DRIVER_MODULE (cx, isa, cx_isa_driver, cx_devclass, cx_modevent, NULL);
+#endif
+#elif __FreeBSD_version >= 400000
+#ifdef NETGRAPH
+DRIVER_MODULE(cx, isa, cx_isa_driver, cx_devclass, ng_mod_event, &typestruct);
+#else
+DRIVER_MODULE(cx, isa, cx_isa_driver, cx_devclass, cx_modevent, 0);
+#endif
+#else /* __FreeBSD_version < 400000 */
+#ifdef KLD_MODULE
+#ifndef NETGRAPH
+static moduledata_t cxmod = { "cx", cx_modevent, NULL};
+DECLARE_MODULE (cx, cxmod, SI_SUB_DRIVERS, SI_ORDER_MIDDLE + CDEV_MAJOR);
+#endif
+#else /* KLD_MODULE */
+
+/*
+ * Now for some driver initialisation.
+ * Occurs ONCE during boot (very early).
+ * This is if we are NOT a loadable module.
+ */
+static void cx_drvinit (void *unused)
+{
+#if __FreeBSD_version < 400000
+        dev_t dev;
+
+	dev = makedev (CDEV_MAJOR, 0);
+	cdevsw_add (&dev, &cx_cdevsw, NULL);
+#else
+	cdevsw_add (&cx_cdevsw);
+#endif
+
+	/* Activate the timeout routine. */
+	timeout_handle = timeout (cx_timeout, 0, hz*5);
+
+	/* Software interrupt. */
+	register_swi (SWI_TTY, cx_softintr);
+#ifdef NETGRAPH
+#if 0
+	/* Register our node type in netgraph */
+	if (ng_newtype (&typestruct))
+		printf ("Failed to register ng_cx\n");
+#endif
+#endif
+}
+
+SYSINIT (cxdev, SI_SUB_DRIVERS, SI_ORDER_MIDDLE+CDEV_MAJOR, cx_drvinit, 0)
+
+#endif /* KLD_MODULE */
+#endif /*  __FreeBSD_version < 400000 */
+#endif /* NCX */
diff --git a/sys/dev/cx/machdep.h b/sys/dev/cx/machdep.h
new file mode 100644
index 0000000..b88e900
--- /dev/null
+++ b/sys/dev/cx/machdep.h
@@ -0,0 +1,96 @@
+/*
+ * Cronyx DDK: platform dependent definitions.
+ *
+ * Copyright (C) 1998-1999 Cronyx Engineering
+ * Author: Alexander Kvitchenko, <aak@cronyx.ru>
+ *
+ * Copyright (C) 2001-2003 Cronyx Engineering.
+ * Author: Roman Kurakin, <rik@cronyx.ru>
+ *
+ * This software is distributed with NO WARRANTIES, not even the implied
+ * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Authors grant any other persons or organisations permission to use
+ * or modify this software as long as this message is kept with the software,
+ * all derivative works or modified versions.
+ *
+ * Cronyx Id: machdep.h,v 1.3.4.3 2003/11/27 14:21:58 rik Exp $
+ * $FreeBSD$
+ */
+
+/*
+ * DOS (Borland Turbo C++ 1.0)
+ */
+#if defined (MSDOS) || defined (__MSDOS__)
+#   include <dos.h>
+#   include <string.h>
+#   define inb(port)		inportb(port)
+#   define inw(port)		inport(port)
+#   define outb(port,b)		outportb(port,b)
+#   define outw(port,w)		outport(port,w)
+#   define GETTICKS()		biostime(0,0L)
+#else
+
+/*
+ * Windows NT
+ */
+#ifdef NDIS_MINIPORT_DRIVER
+#   include <string.h>
+#   define inb(port)		inp((unsigned short)(port))
+#   define inw(port)		inpw((unsigned short)(port))
+#   define outb(port,b)		outp((unsigned short)(port),b)
+#   define outw(port,w)		outpw((unsigned short)(port),(unsigned short)(w))
+#pragma warning (disable: 4761)
+#pragma warning (disable: 4242)
+#pragma warning (disable: 4244)
+#define ulong64			unsigned __int64
+#else
+
+/*
+ * Linux
+ */
+#ifdef __linux__
+#   undef REALLY_SLOW_IO
+#   include <asm/io.h>		/* should swap outb() arguments */
+#   include <linux/string.h>
+#   include <linux/delay.h>
+    static inline void __ddk_outb (unsigned port, unsigned char byte)
+    { outb (byte, port); }
+    static inline void __ddk_outw (unsigned port, unsigned short word)
+    { outw (word, port); }
+#   undef outb
+#   undef outw
+#   define outb(port,val)	__ddk_outb(port, val)
+#   define outw(port,val)	__ddk_outw(port, val)
+#   define GETTICKS()		(jiffies * 200 / 11 / HZ)
+#else
+
+/*
+ * FreeBSD and BSD/OS
+ */
+#ifdef __FreeBSD__
+#   include <sys/param.h>
+#   include <machine/cpufunc.h>
+#   include <sys/libkern.h>
+#   include <sys/systm.h>
+#   define memset(a,b,c)	bzero (a,c)
+#   if __FreeBSD_version > 501000
+#       define port_t int
+#   endif
+#endif
+
+#endif
+#endif
+#endif
+
+#ifndef inline
+#   if __GNUC__ >= 2
+#      define inline __inline__
+#   else
+#      define inline /**/
+#   endif
+#endif
+
+#ifndef ulong64
+#define ulong64 unsigned long long
+#endif
diff --git a/sys/dev/cx/ng_cx.h b/sys/dev/cx/ng_cx.h
new file mode 100644
index 0000000..8616b17
--- /dev/null
+++ b/sys/dev/cx/ng_cx.h
@@ -0,0 +1,30 @@
+/*
+ * Defines for Cronyx-Tau adapter driver.
+ *
+ * Copyright (C) 1999 Cronyx Engineering.
+ * Author: Kurakin Roman, <rik@cronyx.ru>
+ *
+ * This software is distributed with NO WARRANTIES, not even the implied
+ * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Authors grant any other persons or organisations a permission to use,
+ * modify and redistribute this software in source and binary forms,
+ * as long as this message is kept with the software, all derivative
+ * works or modified versions.
+ *
+ * $FreeBSD$
+ */
+
+#ifdef NETGRAPH
+
+#ifndef _CX_NETGRAPH_H_
+#define _CX_NETGRAPH_H_
+
+#define NG_CX_NODE_TYPE		"cx"
+#define NGM_CX_COOKIE		942763600
+#define NG_CX_HOOK_RAW		"rawdata"
+#define NG_CX_HOOK_DEBUG	"debug"
+
+#endif /* _CX_NETGRAPH_H_ */
+
+#endif /* NETGRAPH */