- Import the common MII bitbang'ing code from NetBSD and convert drivers to

  take advantage of it instead of duplicating it. This reduces the size of
  the i386 GENERIC kernel by about 4k. The only potential in-tree user left
  unconverted is xe(4), which generally should be changed to use miibus(4)
  instead of implementing PHY handling on its own, as otherwise it makes not
  much sense to add a dependency on miibus(4)/mii_bitbang(4) to xe(4) just
  for the MII bitbang'ing code. The common MII bitbang'ing code also is
  useful in the embedded space for using GPIO pins to implement MII access.
- Based on lessons learnt with dc(4) (see r185750), add bus barriers to the
  MII bitbang read and write functions of the other drivers converted in
  order to ensure the intended ordering. Given that register access via an
  index register as well as register bank/window switching is subject to the
  same problem, also add bus barriers to the respective functions of smc(4),
  tl(4) and xl(4).
- Sprinkle some const.

Thanks to the following testers:
Andrew Bliznak (nge(4)), nwhitehorn@ (bm(4)), yongari@ (sis(4) and ste(4))
Thanks to Hans-Joerg Sirtl for supplying hardware to test stge(4).

Reviewed by:	yongari (subset of drivers)
Obtained from:	NetBSD (partially)

3 files changed, 40 insertions, 200 deletions

diff --git a/sys/dev/bm/if_bm.c b/sys/dev/bm/if_bm.c
index 1977f92..c478e7b 100644
--- a/sys/dev/bm/if_bm.c
+++ b/sys/dev/bm/if_bm.c
@@ -63,6 +63,7 @@ __FBSDID("$FreeBSD$");
 #include <sys/rman.h>
 
 #include <dev/mii/mii.h>
+#include <dev/mii/mii_bitbang.h>
 #include <dev/mii/miivar.h>
 
 #include <dev/ofw/ofw_bus.h>
@@ -105,17 +106,28 @@ static void bm_tick		(void *xsc);
 static int bm_ifmedia_upd	(struct ifnet *);
 static void bm_ifmedia_sts	(struct ifnet *, struct ifmediareq *);
 
-static void bm_miicsr_dwrite	(struct bm_softc *, u_int16_t);
-static void bm_mii_writebit	(struct bm_softc *, int);
-static int bm_mii_readbit	(struct bm_softc *);
-static void bm_mii_sync		(struct bm_softc *);
-static void bm_mii_send		(struct bm_softc *, u_int32_t, int);
-static int bm_mii_readreg	(struct bm_softc *, struct bm_mii_frame *);
-static int bm_mii_writereg	(struct bm_softc *, struct bm_mii_frame *);
 static int bm_miibus_readreg	(device_t, int, int);
 static int bm_miibus_writereg	(device_t, int, int, int);
 static void bm_miibus_statchg	(device_t);
 
+/*
+ * MII bit-bang glue
+ */
+static uint32_t bm_mii_bitbang_read(device_t);
+static void bm_mii_bitbang_write(device_t, uint32_t);
+
+static const struct mii_bitbang_ops bm_mii_bitbang_ops = {
+	bm_mii_bitbang_read,
+	bm_mii_bitbang_write,
+	{
+		BM_MII_DATAOUT,	/* MII_BIT_MDO */
+		BM_MII_DATAIN,	/* MII_BIT_MDI */
+		BM_MII_CLK,	/* MII_BIT_MDC */
+		BM_MII_OENABLE,	/* MII_BIT_DIR_HOST_PHY */
+		0,		/* MII_BIT_DIR_PHY_HOST */
+	}
+};
+
 static device_method_t bm_methods[] = {
 	/* Device interface */
 	DEVMETHOD(device_probe,		bm_probe),
@@ -150,171 +162,36 @@ DRIVER_MODULE(miibus, bm, miibus_driver, miibus_devclass, 0, 0);
  */
 
 /*
- * Write to the MII csr, introducing a delay to allow valid
- * MII clock pulses to be formed
+ * Write the MII serial port for the MII bit-bang module.
  */
 static void
-bm_miicsr_dwrite(struct bm_softc *sc, u_int16_t val)
-{
-	CSR_WRITE_2(sc, BM_MII_CSR, val);
-	/*
-	 * Assume this is a clock toggle and generate a 1us delay
-	 * to cover both MII's 160ns high/low minimum and 400ns
-	 * cycle miniumum
-	 */
-	DELAY(1);
-}
-
-/*
- * Write a bit to the MII bus.
- */
-static void
-bm_mii_writebit(struct bm_softc *sc, int bit)
-{
-	u_int16_t regval;
-
-	regval = BM_MII_OENABLE;
-	if (bit)
-		regval |= BM_MII_DATAOUT;
-
-	bm_miicsr_dwrite(sc, regval);
-	bm_miicsr_dwrite(sc, regval | BM_MII_CLK);
-	bm_miicsr_dwrite(sc, regval);
-}
-
-/*
- * Read a bit from the MII bus.
- */
-static int
-bm_mii_readbit(struct bm_softc *sc)
-{
-	u_int16_t regval, bitin;
-
-	/* ~BM_MII_OENABLE */
-	regval = 0;
-
-	bm_miicsr_dwrite(sc, regval);
-	bm_miicsr_dwrite(sc, regval | BM_MII_CLK);
-	bm_miicsr_dwrite(sc, regval);
-	bitin = CSR_READ_2(sc, BM_MII_CSR) & BM_MII_DATAIN;
-
-	return (bitin == BM_MII_DATAIN);
-}
-
-/*
- * Sync the PHYs by setting data bit and strobing the clock 32 times.
- */
-static void
-bm_mii_sync(struct bm_softc *sc)
-{
-	int i;
-	u_int16_t regval;
-
-	regval = BM_MII_OENABLE | BM_MII_DATAOUT;
-
-	bm_miicsr_dwrite(sc, regval);
-	for (i = 0; i < 32; i++) {
-		bm_miicsr_dwrite(sc, regval | BM_MII_CLK);
-		bm_miicsr_dwrite(sc, regval);
-	}
-}
-
-/*
- * Clock a series of bits through the MII.
- */
-static void
-bm_mii_send(struct bm_softc *sc, u_int32_t bits, int cnt)
-{
-	int i;
-
-	for (i = (0x1 << (cnt - 1)); i; i >>= 1)
-		bm_mii_writebit(sc, bits & i);
-}
-
-/*
- * Read a PHY register through the MII.
- */
-static int
-bm_mii_readreg(struct bm_softc *sc, struct bm_mii_frame *frame)
+bm_mii_bitbang_write(device_t dev, uint32_t val)
 {
-	int i, ack, bit;
-
-	/*
-	 * Set up frame for RX.
-	 */
-	frame->mii_stdelim = BM_MII_STARTDELIM;
-	frame->mii_opcode = BM_MII_READOP;
-	frame->mii_turnaround = 0;
-	frame->mii_data = 0;
-
-	/*
-	 * Sync the PHYs
-	 */
-	bm_mii_sync(sc);
-
-	/*
-	 * Send command/address info
-	 */
-	bm_mii_send(sc, frame->mii_stdelim, 2);
-	bm_mii_send(sc, frame->mii_opcode, 2);
-	bm_mii_send(sc, frame->mii_phyaddr, 5);
-	bm_mii_send(sc, frame->mii_regaddr, 5);
-
-	/*
-	 * Check for ack.
-	 */
-	ack = bm_mii_readbit(sc);
-
-	/*
-	 * Now try reading data bits. If the ack failed, we still
-	 * need to clock through 16 cycles to keep the PHY(s) in sync.
-	 */
-	for (i = 0x8000; i; i >>= 1) {
-		bit = bm_mii_readbit(sc);
-		if (!ack && bit)
-			frame->mii_data |= i;
-	}
+	struct bm_softc *sc;
 
-	/*
-	 * Skip through idle bit-times
-	 */
-	bm_mii_writebit(sc, 0);
-	bm_mii_writebit(sc, 0);
+	sc = device_get_softc(dev);
 
-	return ((ack) ? 1 : 0);
+	CSR_WRITE_2(sc, BM_MII_CSR, val);
+	CSR_BARRIER(sc, BM_MII_CSR, 2,
+	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
 }
 
 /*
- * Write to a PHY register through the MII.
+ * Read the MII serial port for the MII bit-bang module.
  */
-static int
-bm_mii_writereg(struct bm_softc *sc, struct bm_mii_frame *frame)
+static uint32_t
+bm_mii_bitbang_read(device_t dev)
 {
-	/*
-	 * Set up frame for tx
-	 */
-	frame->mii_stdelim = BM_MII_STARTDELIM;
-	frame->mii_opcode = BM_MII_WRITEOP;
-	frame->mii_turnaround = BM_MII_TURNAROUND;
-
-	/*
-	 * Sync the phy and start the bitbang write sequence
-	 */
-	bm_mii_sync(sc);
+	struct bm_softc *sc;
+	uint32_t reg;
 
-	bm_mii_send(sc, frame->mii_stdelim, 2);
-	bm_mii_send(sc, frame->mii_opcode, 2);
-	bm_mii_send(sc, frame->mii_phyaddr, 5);
-	bm_mii_send(sc, frame->mii_regaddr, 5);
-	bm_mii_send(sc, frame->mii_turnaround, 2);
-	bm_mii_send(sc, frame->mii_data, 16);
+	sc = device_get_softc(dev);
 
-	/*
-	 * Idle bit.
-	 */
-	bm_mii_writebit(sc, 0);
+	reg = CSR_READ_2(sc, BM_MII_CSR);
+	CSR_BARRIER(sc, BM_MII_CSR, 2,
+	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
 
-	return (0);
+	return (reg);
 }
 
 /*
@@ -323,34 +200,15 @@ bm_mii_writereg(struct bm_softc *sc, struct bm_mii_frame *frame)
 static int
 bm_miibus_readreg(device_t dev, int phy, int reg)
 {
-	struct bm_softc *sc;
-	struct bm_mii_frame frame;
-
-	sc = device_get_softc(dev);
-	bzero(&frame, sizeof(frame));
-
-	frame.mii_phyaddr = phy;
-	frame.mii_regaddr = reg;
 
-	bm_mii_readreg(sc, &frame);
-
-	return (frame.mii_data);
+	return (mii_bitbang_readreg(dev, &bm_mii_bitbang_ops, phy, reg));
 }
 
 static int
 bm_miibus_writereg(device_t dev, int phy, int reg, int data)
 {
-	struct bm_softc *sc;
-	struct bm_mii_frame frame;
-
-	sc = device_get_softc(dev);
-	bzero(&frame, sizeof(frame));
-
-	frame.mii_phyaddr = phy;
-	frame.mii_regaddr = reg;
-	frame.mii_data = data;
 
-	bm_mii_writereg(sc, &frame);
+	mii_bitbang_readreg(dev, &bm_mii_bitbang_ops, phy, reg);
 
 	return (0);
 }
diff --git a/sys/dev/bm/if_bmreg.h b/sys/dev/bm/if_bmreg.h
index 15ee1fe..39d9b48 100644
--- a/sys/dev/bm/if_bmreg.h
+++ b/sys/dev/bm/if_bmreg.h
@@ -129,14 +129,6 @@
 #define BM_MII_DATAIN	0x0008		/* MDIO data in */
 
 /*
- * MII constants
- */
-#define BM_MII_STARTDELIM	0x01
-#define BM_MII_READOP		0x02
-#define BM_MII_WRITEOP		0x01
-#define BM_MII_TURNAROUND	0x02
-
-/*
  * Various flags
  */
 
@@ -174,3 +166,5 @@
 #define	CSR_READ_1(sc, reg)		\
 	bus_read_1(sc->sc_memr, reg)
 
+#define CSR_BARRIER(sc, reg, length, flags)				\
+	bus_barrier(sc->sc_memr, reg, length, flags)
diff --git a/sys/dev/bm/if_bmvar.h b/sys/dev/bm/if_bmvar.h
index 7d31489..b50d65b 100644
--- a/sys/dev/bm/if_bmvar.h
+++ b/sys/dev/bm/if_bmvar.h
@@ -46,7 +46,6 @@
 /*
  * software state for transmit job mbufs (may be elements of mbuf chains)
  */
-
 struct bm_txsoft {
 	struct mbuf *txs_mbuf;		/* head of our mbuf chain */
 	bus_dmamap_t txs_dmamap;	/* our DMA map */
@@ -71,7 +70,6 @@ struct bm_rxsoft {
 	bus_dma_segment_t segment;
 };
 
-
 struct bm_softc {
 	struct ifnet    	*sc_ifp;
 	struct mtx		sc_mtx;	
@@ -113,13 +111,3 @@ struct bm_softc {
 
 	dbdma_channel_t		*sc_txdma, *sc_rxdma;
 };
-
-struct bm_mii_frame {
-	u_int8_t		mii_stdelim;
-	u_int8_t		mii_opcode;
-	u_int8_t		mii_phyaddr;
-	u_int8_t		mii_regaddr;
-	u_int8_t		mii_turnaround;
-	u_int16_t		mii_data;
-};
-