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| author | yongari <yongari@FreeBSD.org> | 2013-07-20 07:09:50 +0000 |
|---|---|---|
| committer | yongari <yongari@FreeBSD.org> | 2013-07-20 07:09:50 +0000 |
| commit | 1e1d45f99dc9ee2c041d96659ef6912eeea141f2 (patch) | |
| tree | de19acd8ffad75cf2c28db026271de380069941c /sys/dev/bge | |
| parent | ee86b8d3488047bf943ab138bf7cd74742f97d09 (diff) | |
| download | FreeBSD-src-1e1d45f99dc9ee2c041d96659ef6912eeea141f2.zip FreeBSD-src-1e1d45f99dc9ee2c041d96659ef6912eeea141f2.tar.gz | |
Setup the PCIE Fast Training Sequence (FTS) value to prevent
transmit hangs for 57766 and non Ax versions of 57765.
While here, correct definition of BGE_CHIPREV_57765_AX.
Diffstat (limited to 'sys/dev/bge')
| -rw-r--r-- | sys/dev/bge/if_bge.c | 14 | ||||
| -rw-r--r-- | sys/dev/bge/if_bgereg.h | 5 |
2 files changed, 19 insertions, 0 deletions
diff --git a/sys/dev/bge/if_bge.c b/sys/dev/bge/if_bge.c index ee60626..a2c64b9 100644 --- a/sys/dev/bge/if_bge.c +++ b/sys/dev/bge/if_bge.c @@ -1796,6 +1796,20 @@ bge_chipinit(struct bge_softc *sc) pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2); } + if (sc->bge_asicrev == BGE_ASICREV_BCM57765 || + sc->bge_asicrev == BGE_ASICREV_BCM57766) { + /* + * For the 57766 and non Ax versions of 57765, bootcode + * needs to setup the PCIE Fast Training Sequence (FTS) + * value to prevent transmit hangs. + */ + if (sc->bge_chiprev != BGE_CHIPREV_57765_AX) { + CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, + CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) | + BGE_CPMU_PADRNG_CTL_RDIV2); + } + } + /* * Set up the PCI DMA control register. */ diff --git a/sys/dev/bge/if_bgereg.h b/sys/dev/bge/if_bgereg.h index 8ed8432..469fbd0 100644 --- a/sys/dev/bge/if_bgereg.h +++ b/sys/dev/bge/if_bgereg.h @@ -378,6 +378,7 @@ #define BGE_CHIPREV_5717_AX 0x57170 #define BGE_CHIPREV_5717_BX 0x57171 #define BGE_CHIPREV_5761_AX 0x57611 +#define BGE_CHIPREV_57765_AX 0x577850 #define BGE_CHIPREV_5784_AX 0x57841 /* PCI DMA Read/Write Control register */ @@ -1289,6 +1290,7 @@ #define BGE_CPMU_MUTEX_REQ 0x365C #define BGE_CPMU_MUTEX_GNT 0x3660 #define BGE_CPMU_PHY_STRAP 0x3664 +#define BGE_CPMU_PADRNG_CTL 0x3668 /* Central Power Management Unit (CPMU) register */ #define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200 @@ -1328,6 +1330,9 @@ /* CPMU GPHY Strap register */ #define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020 +/* CPMU Padring Control register */ +#define BGE_CPMU_PADRNG_CTL_RDIV2 0x00040000 + /* * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) */ |
