The Atheros AR71xx CPUs, when paired with the AR5212 parts, has a bug

that generates a fatal bus trap.  Normally, the chips are setup to do
128 byte DMA bursts, but when on this CPU, they can only safely due
4-byte DMA bursts due to this bug.  Details of the exact nature of the
bug are sketchy, but some can be found at
https://forum.openwrt.org/viewtopic.php?pid=70060 on pages 4, 5 and 6.
There's a small performance penalty associated with this workaround,
so it is only enabled when needed on the Atheros AR71xx platforms.

Unfortunately, this condition is impossible to detect at runtime
without MIPS specific ifdefs.  Rather than cast an overly-broad net
like Linux/OpenWRT dues (which enables this workaround all the time on
MIPS32 platforms), we put this option in the kernel for just the
affected machines.  Sam didn't like this aspect of the patch when he
reviewed it, and I'd love to hear sane proposals on how to fix it :)

Reviewed by:	sam@

1 files changed, 8 insertions, 0 deletions

diff --git a/sys/dev/ath/ath_hal/ar5212/ar5212_reset.c b/sys/dev/ath/ath_hal/ar5212/ar5212_reset.c
index fc937ea..8e6341a 100644
--- a/sys/dev/ath/ath_hal/ar5212/ar5212_reset.c
+++ b/sys/dev/ath/ath_hal/ar5212/ar5212_reset.c
@@ -283,6 +283,14 @@ ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
 	regWrites = ath_hal_ini_write(ah, &ahp->ah_ini_modes, modesIndex, 0);
 	regWrites = write_common(ah, &ahp->ah_ini_common, bChannelChange,
 		regWrites);
+#ifdef AH_RXCFG_SDMAMW_4BYTES
+	/*
+	 * Nala doesn't work with 128 byte bursts on pb42(hydra) (ar71xx),
+	 * use 4 instead.  Enabling it on all platforms would hurt performance,
+	 * so we only enable it on the ones that are affected by it.
+	 */
+	OS_REG_WRITE(ah, AR_RXCFG, 0);
+#endif
 	ahp->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites);
 
 	OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);