Revert part of the 9285 support because it breaks the 9280 support. I'll

try to do the 9285 support without interfering with any other chipset
revisions support.

7 files changed, 135 insertions, 446 deletions

diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c b/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c
index c03a744..e59a099 100644
--- a/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c
+++ b/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c
@@ -352,7 +352,7 @@ ar5416Attach(uint16_t devid, HAL_SOFTC sc,
 	}
 
 	ar5416AniSetup(ah);			/* Anti Noise Immunity */
-	ar5416InitNfHistBuff(ah, AH5416(ah)->ah_cal.nfCalHist);
+	ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
 
 	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
 
diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_cal.c b/sys/dev/ath/ath_hal/ar5416/ar5416_cal.c
index 56731f4..712f7e0 100644
--- a/sys/dev/ath/ath_hal/ar5416/ar5416_cal.c
+++ b/sys/dev/ath/ath_hal/ar5416/ar5416_cal.c
@@ -172,53 +172,8 @@ ar5416InitCal(struct ath_hal *ah, const struct ieee80211_channel *chan)
 
 	ichan = ath_hal_checkchannel(ah, chan);
 	HALASSERT(ichan != AH_NULL);
-	if (AR_SREV_KITE_12_OR_LATER(ah)) {
-		OS_REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
-		if (IEEE80211_IS_CHAN_HT20(chan)) {
-			OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL,
-			    AR_PHY_CL_CAL_ENABLE);
-			OS_REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL,
-			    AR_PHY_PARALLEL_CAL_ENABLE);
-			OS_REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
-			OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
-			    AR_PHY_AGC_CONTROL_FLTR_CAL);
-			OS_REG_CLR_BIT(ah, AR_PHY_TPCRG1,
-			    AR_PHY_TPCRG1_PD_CAL_ENABLE);
-			OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
-			    AR_PHY_AGC_CONTROL_CAL);
-			/* Poll for offset calibration complete */
-			if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL,
-			    AR_PHY_AGC_CONTROL_CAL, 0)) {
-				HALDEBUG(ah, HAL_DEBUG_ANY,
-				    "%s: HT offset calibration failed to "
-				    "complete in 1ms; noisy environment?\n",
-				    __func__);
-				return AH_FALSE;
-			}
-			OS_REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
-			OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL,
-			    AR_PHY_PARALLEL_CAL_ENABLE);
-		}
-		OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
-		OS_REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
-		OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
-		    AR_PHY_AGC_CONTROL_FLTR_CAL);
-		OS_REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
-		OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
 
-		/* Poll for offset calibration complete */
-		if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL,
-		    AR_PHY_AGC_CONTROL_CAL, 0)) {
-			HALDEBUG(ah, HAL_DEBUG_ANY,
-			    "%s: offset calibration did not complete in 1ms; "
-			    "noisy environment?\n", __func__);
-			return AH_FALSE;
-		}
-		OS_REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
-		OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
-		OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
-		    AR_PHY_AGC_CONTROL_FLTR_CAL);
-	} else if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
+	if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
 		/* Enable Rx Filter Cal */
 		OS_REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
 		OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
@@ -251,10 +206,9 @@ ar5416InitCal(struct ath_hal *ah, const struct ieee80211_channel *chan)
 	OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
 
 	/* Poll for offset calibration complete */
-	if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL,
-	    AR_PHY_AGC_CONTROL_CAL, 0)) {
+	if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
 		HALDEBUG(ah, HAL_DEBUG_ANY,
-		    "%s: AGC offset calibration did not complete in 1ms; "
+		    "%s: offset calibration did not complete in 1ms; "
 		    "noisy environment?\n", __func__);
 		return AH_FALSE;
 	}
@@ -612,15 +566,9 @@ ar5416LoadNF(struct ath_hal *ah, const struct ieee80211_channel *chan)
 }
 
 void
-ar5416InitNfHistBuff(struct ath_hal *ah, struct ar5212NfCalHist *h)
+ar5416InitNfHistBuff(struct ar5212NfCalHist *h)
 {
 	int i, j;
-	int16_t privNF;
-
-	if (AR_SREV_KITE(ah))
-		privNF = AR9285_CCA_MAX_GOOD_VALUE;
-	else
-		privNF = AR5416_CCA_MAX_GOOD_VALUE;
 
 	for (i = 0; i < AR5416_NUM_NF_READINGS; i ++) {
 		h[i].currIndex = 0;
diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_cal.h b/sys/dev/ath/ath_hal/ar5416/ar5416_cal.h
index 3619df5..e77f300 100644
--- a/sys/dev/ath/ath_hal/ar5416/ar5416_cal.h
+++ b/sys/dev/ath/ath_hal/ar5416/ar5416_cal.h
@@ -116,5 +116,5 @@ void	ar5416AdcGainCalCollect(struct ath_hal *ah);
 void	ar5416AdcGainCalibration(struct ath_hal *ah, uint8_t numChains);
 void	ar5416AdcDcCalCollect(struct ath_hal *ah);
 void	ar5416AdcDcCalibration(struct ath_hal *ah, uint8_t numChains);
-void	ar5416InitNfHistBuff(struct ath_hal *ah, struct ar5212NfCalHist *h);
+void	ar5416InitNfHistBuff(struct ar5212NfCalHist *h);
 #endif /* _ATH_AR5416_CAL_H_ */
diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c b/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c
index d2beb02..1b75715 100644
--- a/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c
+++ b/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c
@@ -23,7 +23,6 @@
 #include "ah_devid.h"
 
 #include "ah_eeprom_v14.h"
-#include "ah_eeprom_v4k.h"
 
 #include "ar5416/ar5416.h"
 #include "ar5416/ar5416reg.h"
@@ -60,17 +59,15 @@ static void ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *ch
 static HAL_BOOL ar5416SetBoardValues(struct ath_hal *, const struct ieee80211_channel *);
 static HAL_BOOL ar5416SetPowerPerRateTable(struct ath_hal *ah,
 	struct ar5416eeprom *pEepData, 
-	struct ar5416eeprom_4k *pEepData4k, 
 	const struct ieee80211_channel *chan, int16_t *ratesArray,
 	uint16_t cfgCtl, uint16_t AntennaReduction,
 	uint16_t twiceMaxRegulatoryPower, 
 	uint16_t powerLimit);
 static HAL_BOOL ar5416SetPowerCalTable(struct ath_hal *ah,
 	struct ar5416eeprom *pEepData,
-	struct ar5416eeprom_4k *pEepData4k,
 	const struct ieee80211_channel *chan,
 	int16_t *pTxPowerIndexOffset);
-static uint16_t ar5416GetMaxEdgePower(struct ath_hal *ah, uint16_t freq,
+static uint16_t ar5416GetMaxEdgePower(uint16_t freq,
 	CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2GHz);
 static void ar5416GetTargetPowers(struct ath_hal *ah, 
 	const struct ieee80211_channel *chan, CAL_TARGET_POWER_HT *powInfo,
@@ -86,7 +83,6 @@ static int16_t interpolate(uint16_t target, uint16_t srcLeft,
 static void ar5416Set11nRegs(struct ath_hal *ah, const struct ieee80211_channel *chan);
 static void ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah, 
 	const struct ieee80211_channel *chan, CAL_DATA_PER_FREQ *pRawDataSet,
-	CAL_DATA_PER_FREQ_4K *pRawDataSet4k,
 	uint8_t * bChans, uint16_t availPiers,
 	uint16_t tPdGainOverlap, int16_t *pMinCalPower,
 	uint16_t * pPdGainBoundaries, uint8_t * pPDADCValues,
@@ -481,12 +477,7 @@ ar5416InitDMA(struct ath_hal *ah)
 	 * reduce the number of usable entries in PCU TXBUF to avoid
 	 * wrap around.
 	 */
-	if (AR_SREV_KITE(ah))
-		OS_REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
-		    AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
-	else 
-		OS_REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
-		    AR_PCU_TXBUF_CTRL_USABLE_SIZE);
+	OS_REG_WRITE(ah, AR_PCU_TXBUF_CTRL, AR_PCU_TXBUF_CTRL_USABLE_SIZE);
 }
 
 static void
@@ -810,7 +801,6 @@ ar5416SetTransmitPower(struct ath_hal *ah,
 #define N(a)            (sizeof (a) / sizeof (a[0]))
 
     MODAL_EEP_HEADER	*pModal;
-    MODAL_EEP4K_HEADER	*pModal4k;
     struct ath_hal_5212 *ahp = AH5212(ah);
     int16_t		ratesArray[Ar5416RateSize];
     int16_t		txPowerIndexOffset = 0;
@@ -822,10 +812,8 @@ ar5416SetTransmitPower(struct ath_hal *ah,
     uint16_t		twiceAntennaReduction;
     uint16_t		twiceMaxRegulatoryPower;
     int16_t		maxPower;
-    HAL_EEPROM_v14 *ee;
-    HAL_EEPROM_v4k *ee4k;
-    struct ar5416eeprom	*pEepData;
-    struct ar5416eeprom_4k *pEepData4k;
+    HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;
+    struct ar5416eeprom	*pEepData = &ee->ee_base;
 
     HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);
 
@@ -835,32 +823,15 @@ ar5416SetTransmitPower(struct ath_hal *ah,
     powerLimit = chan->ic_maxregpower * 2;
     twiceAntennaReduction = chan->ic_maxantgain;
     twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); 
-    if (AR_SREV_KITE(ah)) {
-        ee4k = AH_PRIVATE(ah)->ah_eeprom;
-	pEepData4k = &ee4k->ee_base;
-	pModal4k = &pEepData4k->modalHeader;
-	ee = NULL;
-	pEepData = NULL;
-	pModal = NULL;
-    } else {
-	ee = AH_PRIVATE(ah)->ah_eeprom;
-	pEepData = &ee->ee_base;
-	pModal = &pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)];
-	ee4k = NULL;
-	pEepData4k = NULL;
-	pModal4k = NULL;
-    }
+    pModal = &pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)];
     HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n",
 	__func__,chan->ic_freq, cfgCtl );      
   
     if (IS_EEP_MINOR_V2(ah)) {
-	if (pModal)
-	    ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
-	else
-	    ht40PowerIncForPdadc = pModal4k->ht40PowerIncForPdadc;
+        ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
     }
-
-    if (!ar5416SetPowerPerRateTable(ah, pEepData, pEepData4k, chan,
+ 
+    if (!ar5416SetPowerPerRateTable(ah, pEepData,  chan,
                                     &ratesArray[0],cfgCtl,
                                     twiceAntennaReduction,
 				    twiceMaxRegulatoryPower, powerLimit)) {
@@ -869,8 +840,7 @@ ar5416SetTransmitPower(struct ath_hal *ah,
         return AH_FALSE;
     }
 
-    if (!ar5416SetPowerCalTable(ah, pEepData, pEepData4k, chan,
-	&txPowerIndexOffset)) {
+    if (!ar5416SetPowerCalTable(ah,  pEepData, chan, &txPowerIndexOffset)) {
         HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n",
 	    __func__);
         return AH_FALSE;
@@ -898,8 +868,6 @@ ar5416SetTransmitPower(struct ath_hal *ah,
         ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
         if (ratesArray[i] > AR5416_MAX_RATE_POWER)
             ratesArray[i] = AR5416_MAX_RATE_POWER;
-	if (AR_SREV_MERLIN_10_OR_LATER(ah))
-	    ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
     }
 
 #ifdef AH_EEPROM_DUMP
@@ -979,11 +947,10 @@ ar5416SetTransmitPower(struct ath_hal *ah,
     }
 
     /* Write the Power subtraction for dynamic chain changing, for per-packet powertx */
-    if (pModal)
-	    OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
-		POW_SM(pModal->pwrDecreaseFor3Chain, 6)
-		  | POW_SM(pModal->pwrDecreaseFor2Chain, 0)
-	    );
+    OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
+        POW_SM(pModal->pwrDecreaseFor3Chain, 6)
+          | POW_SM(pModal->pwrDecreaseFor2Chain, 0)
+    );
     return AH_TRUE;
 #undef POW_SM
 #undef N
@@ -1221,43 +1188,24 @@ ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan)
 static HAL_BOOL
 ar5416SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
 {
-    const HAL_EEPROM_v14 *ee;
-    const HAL_EEPROM_v4k *ee4k;
-    const struct ar5416eeprom *eep;
-    const struct ar5416eeprom_4k *eep4k;
+    const HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;
+    const struct ar5416eeprom *eep = &ee->ee_base;
     const MODAL_EEP_HEADER *pModal;
-    const MODAL_EEP4K_HEADER *pModal4k;
-    int			i, regChainOffset = 0;
+    int			i, regChainOffset;
     uint8_t		txRxAttenLocal;    /* workaround for eeprom versions <= 14.2 */
 
     HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);
-
-    if (AR_SREV_KITE(ah)) {
-	    ee4k = AH_PRIVATE(ah)->ah_eeprom;
-	    eep4k = &ee4k->ee_base;
-	    pModal4k = &eep4k->modalHeader;
-	    ee = NULL;
-	    eep = NULL;
-	    pModal = NULL;
-    } else {
-	    ee = AH_PRIVATE(ah)->ah_eeprom;
-	    eep = &ee->ee_base;
-	    pModal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)];
-	    ee4k = NULL;
-	    eep4k = NULL;
-	    pModal4k = NULL;
-    }
+    pModal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)];
 
     /* NB: workaround for eeprom versions <= 14.2 */
     txRxAttenLocal = IEEE80211_IS_CHAN_2GHZ(chan) ? 23 : 44;
 
-    OS_REG_WRITE(ah, AR_PHY_SWITCH_COM,
-	(pModal) ? pModal->antCtrlCommon :
-	pModal4k->antCtrlCommon);
+    OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
     for (i = 0; i < AR5416_MAX_CHAINS; i++) { 
-//	if (AR_SREV_KITE(ah) && i >= 2) break;
-	if (AR_SREV_MERLIN(ah) && i >= 2) break;
-       	if (AR_SREV_OWL_20_OR_LATER(ah) &&
+	   if (AR_SREV_MERLIN(ah)) {
+		if (i >= 2) break;
+	   }
+       	   if (AR_SREV_OWL_20_OR_LATER(ah) &&
             (AH5416(ah)->ah_rx_chainmask == 0x5 ||
 	     AH5416(ah)->ah_tx_chainmask == 0x5) && i != 0) {
             /* Regs are swapped from chain 2 to 1 for 5416 2_0 with 
@@ -1268,15 +1216,12 @@ ar5416SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
             regChainOffset = i * 0x1000;
         }
 
-        OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
-	    (pModal) ? pModal->antCtrlChain[i] : pModal4k->antCtrlChain[i]);
+        OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, pModal->antCtrlChain[i]);
         OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4 + regChainOffset, 
         	(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4 + regChainOffset) &
         	~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
-        	SM((pModal) ? pModal->iqCalICh[i] : pModal4k->iqCalICh[i],
-		    AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
-        	SM((pModal) ? pModal->iqCalQCh[i] : pModal4k->iqCalQCh[i],
-		    AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
+        	SM(pModal->iqCalICh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
+        	SM(pModal->iqCalQCh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
 
         /*
          * Large signal upgrade.
@@ -1284,82 +1229,54 @@ ar5416SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
          */
 
         if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) {
-	    int txRxAtten;
-	    if (IS_EEP_MINOR_V3(ah)) {
-		if (pModal) txRxAtten = pModal->txRxAttenCh[i];
-		else txRxAtten = pModal4k->txRxAttenCh[i];
-	    } else
-		txRxAtten = txRxAttenLocal;
-
-	    if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
-		    OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
-			AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAtten);
-		    OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
-			AR9280_PHY_RXGAIN_TXRX_MARGIN,
-			(pModal) ? pModal->rxTxMarginCh[i] : pModal4k->rxTxMarginCh[i]);
-	    } else {
-                OS_REG_WRITE(ah, AR_PHY_RXGAIN + regChainOffset, 
-		    (OS_REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) & ~AR_PHY_RXGAIN_TXRX_ATTEN) |
-		   	    SM(txRxAtten, AR_PHY_RXGAIN_TXRX_ATTEN));
-
-                OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 
-	      	    (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) & ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
-			    SM((pModal) ? pModal->rxTxMarginCh[i]: 
-			                  pModal4k->rxTxMarginCh[i],
-			        AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
-	    }
+            OS_REG_WRITE(ah, AR_PHY_RXGAIN + regChainOffset, 
+		(OS_REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) & ~AR_PHY_RXGAIN_TXRX_ATTEN) |
+			SM(IS_EEP_MINOR_V3(ah)  ? pModal->txRxAttenCh[i] : txRxAttenLocal,
+				AR_PHY_RXGAIN_TXRX_ATTEN));
+
+            OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 
+	    	(OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) & ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
+			SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
         }
     }
 
-    OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
-	(pModal) ? pModal->switchSettling : pModal4k->switchSettling);
-    OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
-	(pModal) ? pModal->adcDesiredSize : pModal4k->adcDesiredSize);
-    OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_PGA,
-	(pModal) ? pModal->pgaDesiredSize : pModal4k->pgaDesiredSize);
+    OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->switchSettling);
+    OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize);
+    OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_PGA, pModal->pgaDesiredSize);
     OS_REG_WRITE(ah, AR_PHY_RF_CTL4,
-                 SM((pModal) ? pModal->txEndToXpaOff : pModal4k->txEndToXpaOff,
-	             AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
-               | SM((pModal) ? pModal->txEndToXpaOff : pModal4k->txEndToXpaOff,
-	             AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
-               | SM((pModal) ? pModal->txFrameToXpaOn : pModal4k->txFrameToXpaOn,
-	             AR_PHY_RF_CTL4_FRAME_XPAA_ON)
-               | SM((pModal) ? pModal->txFrameToXpaOn : pModal4k->txFrameToXpaOn,
-	             AR_PHY_RF_CTL4_FRAME_XPAB_ON));
-
-    OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
-	            (pModal) ? pModal->txEndToRxOn : pModal4k->txEndToRxOn);
+        SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
+        | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
+        | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)
+        | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
+
+    OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, pModal->txEndToRxOn);
 
     if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
 	OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
-	    (pModal) ? pModal->thresh62 : pModal4k->thresh62);
+	    pModal->thresh62);
 	OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
-	    (pModal) ? pModal->thresh62 : pModal4k->thresh62);
+	    pModal->thresh62);
     } else {
 	OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
-	    (pModal) ? pModal->thresh62 : pModal4k->thresh62);
+	    pModal->thresh62);
 	OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA_THRESH62,
-	    (pModal) ? pModal->thresh62 : pModal4k->thresh62);
+	    pModal->thresh62);
     }
     
     /* Minor Version Specific application */
     if (IS_EEP_MINOR_V2(ah)) {
-        OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,  AR_PHY_TX_FRAME_TO_DATA_START, 
-	                 (pModal) ? pModal->txFrameToDataStart : pModal4k->txFrameToDataStart);
-        OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,  AR_PHY_TX_FRAME_TO_PA_ON,
-	                 (pModal) ? pModal->txFrameToPaOn : pModal4k->txFrameToPaOn);
+        OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,  AR_PHY_TX_FRAME_TO_DATA_START, pModal->txFrameToDataStart);
+        OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,  AR_PHY_TX_FRAME_TO_PA_ON, pModal->txFrameToPaOn);    
     }	
     
     if (IS_EEP_MINOR_V3(ah)) {
 	if (IEEE80211_IS_CHAN_HT40(chan)) {
 		/* Overwrite switch settling with HT40 value */
-		OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
-		                 (pModal) ? pModal->swSettleHt40 : pModal4k->swSettleHt40);
+		OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40);
 	}
 	
         if ((AR_SREV_OWL_20_OR_LATER(ah)) &&
             (  AH5416(ah)->ah_rx_chainmask == 0x5 || AH5416(ah)->ah_tx_chainmask == 0x5)){
-            /* NB: no v4k EEPROM */
             /* Reg Offsets are swapped for logical mapping */
 		OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
 			SM(pModal->bswMargin[2], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
@@ -1370,38 +1287,17 @@ ar5416SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
 		OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
 			SM(pModal->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
         } else {
-	    if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
-		OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
-		      AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
-		      (pModal) ? pModal->bswMargin[i] : pModal4k->bswMargin[i]);
-		OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
-		      AR_PHY_GAIN_2GHZ_XATTEN1_DB,
-		      (pModal) ? pModal->bswAtten[i] : pModal4k->bswAtten[i]);
-		OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
-		      AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
-		      (pModal) ? pModal->xatten2Margin[i] : pModal4k->xatten2Margin[i]);
-		OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
-		      AR_PHY_GAIN_2GHZ_XATTEN2_DB,
-		      (pModal) ? pModal->xatten2Db[i] : pModal4k->xatten2Db[i]);
-	    } else {
 		OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
-			SM((pModal) ? pModal->bswMargin[1] : 
-			  pModal4k->bswMargin[1], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
+			SM(pModal->bswMargin[1], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
 		OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
-			SM((pModal) ? pModal->bswAtten[1] :
-			  pModal4k->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
+			SM(pModal->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
 		OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
-			SM((pModal) ? pModal->bswMargin[2] :
-			    pModal4k->bswMargin[2], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
+			SM(pModal->bswMargin[2],AR_PHY_GAIN_2GHZ_BSW_MARGIN));
 		OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
-			SM((pModal) ? pModal->bswAtten[2] : 
-			  pModal4k->bswAtten[2], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
-	    }
+			SM(pModal->bswAtten[2], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
         }
-        OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_MARGIN,
-	    (pModal) ? pModal->bswMargin[0] : pModal4k->bswMargin[0]);
-        OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_ATTEN,
-	    (pModal) ? pModal->bswAtten[0] : pModal4k->bswAtten[0]);
+        OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_MARGIN, pModal->bswMargin[0]);
+        OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_ATTEN, pModal->bswAtten[0]);
     }
     return AH_TRUE;
 }
@@ -1416,9 +1312,8 @@ ar5416SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
  * Sets the transmit power in the baseband for the given
  * operating channel and mode.
  */
-HAL_BOOL
+static HAL_BOOL
 ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
-    			   struct ar5416eeprom_4k *pEepData4k,
                            const struct ieee80211_channel *chan,
                            int16_t *ratesArray, uint16_t cfgCtl,
                            uint16_t AntennaReduction, 
@@ -1436,7 +1331,6 @@ ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
 	int i;
 	int16_t  twiceLargestAntenna;
 	CAL_CTL_DATA *rep;
-	CAL_CTL_DATA_4K *rep4k;
 	CAL_TARGET_POWER_LEG targetPowerOfdm, targetPowerCck = {0, {0, 0, 0, 0}};
 	CAL_TARGET_POWER_LEG targetPowerOfdmExt = {0, {0, 0, 0, 0}}, targetPowerCckExt = {0, {0, 0, 0, 0}};
 	CAL_TARGET_POWER_HT  targetPowerHt20, targetPowerHt40 = {0, {0, 0, 0, 0}};
@@ -1453,19 +1347,15 @@ ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
 	const uint16_t *pCtlMode;
 	uint16_t numCtlModes, ctlMode, freq;
 	CHAN_CENTERS centers;
-	int n2gcck, n2g20, n2g40, numctls;
 
 	ar5416GetChannelCenters(ah,  chan, &centers);
 
 	/* Compute TxPower reduction due to Antenna Gain */
 
-	if (pEepData)
-		twiceLargestAntenna = AH_MAX(AH_MAX(
-		    pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[0],
-		    pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[1]),
-		    pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
-	else
-		twiceLargestAntenna = pEepData4k->modalHeader.antennaGainCh[0];
+	twiceLargestAntenna = AH_MAX(AH_MAX(
+	    pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[0],
+	    pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[1]),
+	    pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
 #if 0
 	/* Turn it back on if we need to calculate per chain antenna gain reduction */
 	/* Use only if the expected gain > 6dbi */
@@ -1500,12 +1390,10 @@ ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
 	case 1:
 		break;
 	case 2:
-		if (pEepData)
-			scaledPower -= pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pwrDecreaseFor2Chain;
+		scaledPower -= pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pwrDecreaseFor2Chain;
 		break;
 	case 3:
-		if (pEepData)
-			scaledPower -= pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pwrDecreaseFor3Chain;
+		scaledPower -= pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pwrDecreaseFor3Chain;
 		break;
 	default:
 		return AH_FALSE; /* Unsupported number of chains */
@@ -1513,56 +1401,36 @@ ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
 
 	scaledPower = AH_MAX(0, scaledPower);
 
-	n2gcck = (pEepData) ? AR5416_NUM_2G_CCK_TARGET_POWERS :
-	    AR5416_4K_NUM_2G_CCK_TARGET_POWERS;
-	n2g20 = (pEepData) ? AR5416_NUM_2G_20_TARGET_POWERS :
-	    AR5416_4K_NUM_2G_20_TARGET_POWERS;
-	n2g40 = (pEepData) ? AR5416_NUM_2G_40_TARGET_POWERS :
-	    AR5416_4K_NUM_2G_40_TARGET_POWERS;
-
 	/* Get target powers from EEPROM - our baseline for TX Power */
 	if (IEEE80211_IS_CHAN_2GHZ(chan)) {
 		/* Setup for CTL modes */
 		numCtlModes = N(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; /* CTL_11B, CTL_11G, CTL_2GHT20 */
 		pCtlMode = ctlModesFor11g;
 
-		ar5416GetTargetPowersLeg(ah,  chan,
-		    (pEepData) ? pEepData->calTargetPowerCck :
-		        pEepData4k->calTargetPowerCck,
-		    n2gcck, &targetPowerCck, 4, AH_FALSE);
-		ar5416GetTargetPowersLeg(ah,  chan,
-		    (pEepData) ? pEepData->calTargetPower2G :
-		        pEepData4k->calTargetPower2G,
-		    n2g20, &targetPowerOfdm, 4, AH_FALSE);
-		ar5416GetTargetPowers(ah,  chan,
-		    (pEepData) ? pEepData->calTargetPower2GHT20 :
-		        pEepData4k->calTargetPower2GHT20,
-		    n2g20, &targetPowerHt20, 8, AH_FALSE);
+		ar5416GetTargetPowersLeg(ah,  chan, pEepData->calTargetPowerCck,
+				AR5416_NUM_2G_CCK_TARGET_POWERS, &targetPowerCck, 4, AH_FALSE);
+		ar5416GetTargetPowersLeg(ah,  chan, pEepData->calTargetPower2G,
+				AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE);
+		ar5416GetTargetPowers(ah,  chan, pEepData->calTargetPower2GHT20,
+				AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE);
 
 		if (IEEE80211_IS_CHAN_HT40(chan)) {
 			numCtlModes = N(ctlModesFor11g);    /* All 2G CTL's */
 
-			ar5416GetTargetPowers(ah, chan,
-			    (pEepData) ? pEepData->calTargetPower2GHT40 :
-			        pEepData4k->calTargetPower2GHT40,
-			    n2g40, &targetPowerHt40, 8, AH_TRUE);
+			ar5416GetTargetPowers(ah,  chan, pEepData->calTargetPower2GHT40,
+				AR5416_NUM_2G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE);
 			/* Get target powers for extension channels */
-			ar5416GetTargetPowersLeg(ah, chan,
-			    (pEepData) ? pEepData->calTargetPowerCck :
-			        pEepData4k->calTargetPowerCck,
-			    n2gcck, &targetPowerCckExt, 4, AH_TRUE);
-			ar5416GetTargetPowersLeg(ah, chan,
-			    (pEepData) ? pEepData->calTargetPower2G :
-			        pEepData4k->calTargetPower2G,
-			    n2g20, &targetPowerOfdmExt, 4, AH_TRUE);
+			ar5416GetTargetPowersLeg(ah,  chan, pEepData->calTargetPowerCck,
+				AR5416_NUM_2G_CCK_TARGET_POWERS, &targetPowerCckExt, 4, AH_TRUE);
+			ar5416GetTargetPowersLeg(ah,  chan, pEepData->calTargetPower2G,
+				AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE);
 		}
 	} else {
 		/* Setup for CTL modes */
 		numCtlModes = N(ctlModesFor11a) - SUB_NUM_CTL_MODES_AT_5G_40; /* CTL_11A, CTL_5GHT20 */
 		pCtlMode = ctlModesFor11a;
 
-		/* NB: v4k EEPROM has no 5Ghz info */
-		ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower5G,
+		ar5416GetTargetPowersLeg(ah,  chan, pEepData->calTargetPower5G,
 				AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE);
 		ar5416GetTargetPowers(ah,  chan, pEepData->calTargetPower5GHT20,
 				AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE);
@@ -1586,9 +1454,7 @@ ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
 	 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
 	 *
 	 */
-	numctls = (pEepData) ? AR5416_NUM_CTLS : AR5416_4K_NUM_CTLS;
 	for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
-		int ctlIndex;
 		HAL_BOOL isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
 		    (pCtlMode[ctlMode] == CTL_2GHT40);
 		if (isHt40CtlMode) {
@@ -1600,33 +1466,17 @@ ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
 		}
 
 		/* walk through each CTL index stored in EEPROM */
-		for (i = 0; i < numctls; i++) {
+		for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
 			uint16_t twiceMinEdgePower;
-			CAL_CTL_EDGES *ctlEdge;
-
-			ctlIndex = (pEepData) ? pEepData->ctlIndex[i] :
-			    pEepData4k->ctlIndex[i];
-			if (!ctlIndex)
-				break;
 
 			/* compare test group from regulatory channel list with test mode from pCtlMode list */
-			if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == ctlIndex) ||
+			if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == pEepData->ctlIndex[i]) ||
 				(((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == 
-				 ((ctlIndex & CTL_MODE_M) | SD_NO_CTL))) {
-				if (pEepData) {
-					rep = &(pEepData->ctlData[i]);
-					ctlEdge = rep->ctlEdges[
-					    owl_get_ntxchains(
-						AH5416(ah)->ah_tx_chainmask) - 1];
-				} else {
-					rep4k = &(pEepData4k->ctlData[i]);
-					ctlEdge = rep4k->ctlEdges[
-					    owl_get_ntxchains(
-						AH5416(ah)->ah_tx_chainmask) - 1];
-				}
-				twiceMinEdgePower = ar5416GetMaxEdgePower(ah,
-				    freq, ctlEdge,
-				    IEEE80211_IS_CHAN_2GHZ(chan));
+				 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
+				rep = &(pEepData->ctlData[i]);
+				twiceMinEdgePower = ar5416GetMaxEdgePower(freq,
+							rep->ctlEdges[owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1],
+							IEEE80211_IS_CHAN_2GHZ(chan));
 				if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
 					/* Find the minimum of all CTL edge powers that apply to this channel */
 					twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower);
@@ -1740,19 +1590,13 @@ fbin2freq(uint8_t fbin, HAL_BOOL is2GHz)
  * Find the maximum conformance test limit for the given channel and CTL info
  */
 static uint16_t
-ar5416GetMaxEdgePower(struct ath_hal *ah,
-    uint16_t freq, CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2GHz)
+ar5416GetMaxEdgePower(uint16_t freq, CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2GHz)
 {
     uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
-    int      i, numBand;
-
-    if (AR_SREV_KITE(ah))
-	    numBand = AR5416_4K_NUM_BAND_EDGES;
-    else
-	    numBand = AR5416_NUM_BAND_EDGES;
+    int      i;
 
     /* Get the edge power */
-    for (i = 0; (i < numBand) && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED) ; i++) {
+    for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED) ; i++) {
         /*
          * If there's an exact channel match or an inband flag set
          * on the lower channel use the given rdEdgePower
@@ -1899,13 +1743,11 @@ ar5416GetTargetPowersLeg(struct ath_hal *ah,
  * points as well as from the nearest pier(s) to get a power detector
  * linear voltage to power level table.
  */
-HAL_BOOL
+static HAL_BOOL
 ar5416SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
-        struct ar5416eeprom_4k *pEepData4k,
 	const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset)
 {
-    CAL_DATA_PER_FREQ *pRawDataset = NULL;
-    CAL_DATA_PER_FREQ_4K *pRawDataset4k = NULL;
+    CAL_DATA_PER_FREQ *pRawDataset;
     uint8_t  *pCalBChans = AH_NULL;
     uint16_t pdGainOverlap_t2;
     static uint8_t  pdadcValues[AR5416_NUM_PDADC_VALUES];
@@ -1918,28 +1760,17 @@ ar5416SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
 
     OS_MEMZERO(xpdGainValues, sizeof(xpdGainValues));
     
-    if (pEepData)
-	    xpdMask = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].xpdGain;
-    else
-	    xpdMask = pEepData4k->modalHeader.xpdGain;
+    xpdMask = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].xpdGain;
 
     if (IS_EEP_MINOR_V2(ah)) {
-	if (pEepData)
-		pdGainOverlap_t2 = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pdGainOverlap;
-	else
-		pdGainOverlap_t2 = pEepData4k->modalHeader.pdGainOverlap;
+        pdGainOverlap_t2 = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pdGainOverlap;
     } else { 
     	pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
     }
 
     if (IEEE80211_IS_CHAN_2GHZ(chan)) {
-	if (pEepData) {
-		pCalBChans = pEepData->calFreqPier2G;
-		numPiers = AR5416_NUM_2G_CAL_PIERS;
-	} else {
-		pCalBChans = pEepData4k->calFreqPier2G;
-		numPiers = AR5416_4K_NUM_2G_CAL_PIERS;
-	}
+        pCalBChans = pEepData->calFreqPier2G;
+        numPiers = AR5416_NUM_2G_CAL_PIERS;
     } else {
         pCalBChans = pEepData->calFreqPier5G;
         numPiers = AR5416_NUM_5G_CAL_PIERS;
@@ -1965,7 +1796,7 @@ ar5416SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
 	SM(xpdGainValues[1], AR_PHY_TPCRG1_PD_GAIN_2) | SM(xpdGainValues[2],  AR_PHY_TPCRG1_PD_GAIN_3));
 
     for (i = 0; i < AR5416_MAX_CHAINS; i++) {
-//	    if (AR_SREV_KITE(ah) && i >= AR5416_4K_MAX_CHAINS) break;
+
             if (AR_SREV_OWL_20_OR_LATER(ah) && 
             ( AH5416(ah)->ah_rx_chainmask == 0x5 || AH5416(ah)->ah_tx_chainmask == 0x5) && (i != 0)) {
             /* Regs are swapped from chain 2 to 1 for 5416 2_0 with 
@@ -1976,22 +1807,14 @@ ar5416SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
             regChainOffset = i * 0x1000;
         }
 
-	int txMask;
-	txMask = (pEepData) ? pEepData->baseEepHeader.txMask :
-	    pEepData4k->baseEepHeader.txMask;
-
-        if (txMask & (1 << i)) {
+        if (pEepData->baseEepHeader.txMask & (1 << i)) {
             if (IEEE80211_IS_CHAN_2GHZ(chan)) {
-		if (pEepData)
-		    pRawDataset = pEepData->calPierData2G[i];
-		else
-		    pRawDataset4k = pEepData4k->calPierData2G[i];
+                pRawDataset = pEepData->calPierData2G[i];
             } else {
                 pRawDataset = pEepData->calPierData5G[i];
             }
 
-            ar5416GetGainBoundariesAndPdadcs(ah, chan, pRawDataset,
-					     pRawDataset4k,
+            ar5416GetGainBoundariesAndPdadcs(ah,  chan, pRawDataset,
                                              pCalBChans, numPiers,
                                              pdGainOverlap_t2,
                                              &tMinCalPower, gainBoundaries,
@@ -2003,6 +1826,7 @@ ar5416SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
                  * negative or greater than 0.  Need to offset the power
                  * values by the amount of minPower for griffin
                  */
+
                 OS_REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
                      SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
                      SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)  |
@@ -2048,10 +1872,8 @@ static void
 ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah, 
                                  const struct ieee80211_channel *chan,
 				 CAL_DATA_PER_FREQ *pRawDataSet,
-				 CAL_DATA_PER_FREQ_4K *pRawDataSet4k,
                                  uint8_t * bChans,  uint16_t availPiers,
-                                 uint16_t tPdGainOverlap, int16_t *pMinCalPower,
-				 uint16_t * pPdGainBoundaries,
+                                 uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t * pPdGainBoundaries,
                                  uint8_t * pPDADCValues, uint16_t numXpdGains)
 {
 
@@ -2094,35 +1916,17 @@ ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah,
     if (match) {
         /* Directly fill both vpd tables from the matching index */
         for (i = 0; i < numXpdGains; i++) {
-	    if (pRawDataSet) {
-		    minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
-		    maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
-		    ar5416FillVpdTable(minPwrT4[i], maxPwrT4[i],
-				       pRawDataSet[idxL].pwrPdg[i],
-				       pRawDataSet[idxL].vpdPdg[i],
-				       AR5416_PD_GAIN_ICEPTS, vpdTableI[i]);
-	    } else {
-		    minPwrT4[i] = pRawDataSet4k[idxL].pwrPdg[i][0];
-		    maxPwrT4[i] = pRawDataSet4k[idxL].pwrPdg[i][4];
-		    ar5416FillVpdTable(minPwrT4[i], maxPwrT4[i],
-				       pRawDataSet4k[idxL].pwrPdg[i],
-				       pRawDataSet4k[idxL].vpdPdg[i],
-				       AR5416_PD_GAIN_ICEPTS, vpdTableI[i]);
-	    }
+            minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
+            maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
+            ar5416FillVpdTable(minPwrT4[i], maxPwrT4[i], pRawDataSet[idxL].pwrPdg[i],
+                               pRawDataSet[idxL].vpdPdg[i], AR5416_PD_GAIN_ICEPTS, vpdTableI[i]);
         }
     } else {
         for (i = 0; i < numXpdGains; i++) {
-	    if (pRawDataSet) {
-		    pVpdL = pRawDataSet[idxL].vpdPdg[i];
-		    pPwrL = pRawDataSet[idxL].pwrPdg[i];
-		    pVpdR = pRawDataSet[idxR].vpdPdg[i];
-		    pPwrR = pRawDataSet[idxR].pwrPdg[i];
-	    } else {
-		    pVpdL = pRawDataSet4k[idxL].vpdPdg[i];
-		    pPwrL = pRawDataSet4k[idxL].pwrPdg[i];
-		    pVpdR = pRawDataSet4k[idxR].vpdPdg[i];
-		    pPwrR = pRawDataSet4k[idxR].pwrPdg[i];
-	    }
+            pVpdL = pRawDataSet[idxL].vpdPdg[i];
+            pPwrL = pRawDataSet[idxL].pwrPdg[i];
+            pVpdR = pRawDataSet[idxR].vpdPdg[i];
+            pPwrR = pRawDataSet[idxR].pwrPdg[i];
 
             /* Start Vpd interpolation from the max of the minimum powers */
             minPwrT4[i] = AH_MAX(pPwrL[0], pPwrR[0]);
@@ -2170,10 +1974,7 @@ ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah,
 
         /* Find starting index for this pdGain */
         if (i == 0) {
-            if (AR_SREV_MERLIN_10_OR_LATER(ah))
-		ss = (int16_t)(0 - (minPwrT4[i] / 2));
-	    else
-                ss = 0; /* for the first pdGain, start from index 0 */
+            ss = 0; /* for the first pdGain, start from index 0 */
         } else {
 	    /* need overlap entries extrapolated below. */
             ss = (int16_t)((pPdGainBoundaries[i-1] - (minPwrT4[i] / 2)) - tPdGainOverlap + 1 + minDelta);
@@ -2189,7 +1990,7 @@ ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah,
             ss++;
         }
 
-        sizeCurrVpdTable = (uint8_t)((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
+        sizeCurrVpdTable = (uint8_t)((maxPwrT4[i] - minPwrT4[i]) / 2 +1);
         tgtIndex = (uint8_t)(pPdGainBoundaries[i] + tPdGainOverlap - (minPwrT4[i] / 2));
         maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable;
 
@@ -2338,20 +2139,13 @@ ar5416Set11nRegs(struct ath_hal *ah, const struct ieee80211_channel *chan)
 {
 	uint32_t phymode;
 	HAL_HT_MACMODE macmode;		/* MAC - 20/40 mode */
-	uint32_t dacFifo;
 
 	if (!IEEE80211_IS_CHAN_HT(chan))
 		return;
 
-	if (AR_SREV_KITE_10_OR_LATER(ah))
-		dacFifo = OS_REG_READ(ah, AR_PHY_TURBO) 
-		        & AR_PHY_FC_ENABLE_DAC_FIFO;
-	else
-		dacFifo = 0;
-
 	/* Enable 11n HT, 20 MHz */
 	phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
-		| AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | dacFifo;
+		| AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH;
 
 	/* Configure baseband for dynamic 20/40 operation */
 	if (IEEE80211_IS_CHAN_HT40(chan)) {
diff --git a/sys/dev/ath/ath_hal/ar5416/ar9160_attach.c b/sys/dev/ath/ath_hal/ar5416/ar9160_attach.c
index fd3945c..96dca80 100644
--- a/sys/dev/ath/ath_hal/ar5416/ar9160_attach.c
+++ b/sys/dev/ath/ath_hal/ar5416/ar9160_attach.c
@@ -249,7 +249,7 @@ ar9160Attach(uint16_t devid, HAL_SOFTC sc,
 		OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
 
 	ar9160AniSetup(ah);			/* Anti Noise Immunity */
-	ar5416InitNfHistBuff(ah, AH5416(ah)->ah_cal.nfCalHist);
+	ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
 
 	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
 
diff --git a/sys/dev/ath/ath_hal/ar5416/ar9280.c b/sys/dev/ath/ath_hal/ar5416/ar9280.c
index dd69311..72720f7 100644
--- a/sys/dev/ath/ath_hal/ar5416/ar9280.c
+++ b/sys/dev/ath/ath_hal/ar5416/ar9280.c
@@ -277,15 +277,12 @@ ar9280GetNoiseFloor(struct ath_hal *ah, int16_t nfarray[])
 	    "NF calibrated [ctl] [chain 0] is %d\n", nf);
 	nfarray[0] = nf;
 
-	if (!AR_SREV_KITE(ah)) {
-		nf = MS(OS_REG_READ(ah, AR_PHY_CH1_CCA),
-		    AR9280_PHY_CH1_MINCCA_PWR);
-		if (nf & 0x100)
-			nf = 0 - ((nf ^ 0x1ff) + 1);
-		HALDEBUG(ah, HAL_DEBUG_NFCAL,
-		    "NF calibrated [ctl] [chain 1] is %d\n", nf);
-		nfarray[1] = nf;
-	}
+	nf = MS(OS_REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR);
+	if (nf & 0x100)
+		nf = 0 - ((nf ^ 0x1ff) + 1);
+	HALDEBUG(ah, HAL_DEBUG_NFCAL,
+	    "NF calibrated [ctl] [chain 1] is %d\n", nf);
+	nfarray[1] = nf;
 
 	nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
 	if (nf & 0x100)
@@ -294,15 +291,12 @@ ar9280GetNoiseFloor(struct ath_hal *ah, int16_t nfarray[])
 	    "NF calibrated [ext] [chain 0] is %d\n", nf);
 	nfarray[3] = nf;
 
-	if (AR_SREV_KITE(ah)) {
-		nf = MS(OS_REG_READ(ah, AR_PHY_CH1_EXT_CCA),
-		    AR9280_PHY_CH1_EXT_MINCCA_PWR);
-		if (nf & 0x100)
+	nf = MS(OS_REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR);
+	if (nf & 0x100)
 		nf = 0 - ((nf ^ 0x1ff) + 1);
-		HALDEBUG(ah, HAL_DEBUG_NFCAL,
-		    "NF calibrated [ext] [chain 1] is %d\n", nf);
-		nfarray[4] = nf;
-	}
+	HALDEBUG(ah, HAL_DEBUG_NFCAL,
+	    "NF calibrated [ext] [chain 1] is %d\n", nf);
+	nfarray[4] = nf;
 }
 
 /*
diff --git a/sys/dev/ath/ath_hal/ar5416/ar9280_attach.c b/sys/dev/ath/ath_hal/ar5416/ar9280_attach.c
index bac8a55..d998af0 100644
--- a/sys/dev/ath/ath_hal/ar5416/ar9280_attach.c
+++ b/sys/dev/ath/ath_hal/ar5416/ar9280_attach.c
@@ -23,7 +23,6 @@
 #include "ah_devid.h"
 
 #include "ah_eeprom_v14.h"		/* XXX for tx/rx gain */
-#include "ah_eeprom_v4k.h"
 
 #include "ar5416/ar9280.h"
 #include "ar5416/ar5416reg.h"
@@ -31,9 +30,6 @@
 
 #include "ar5416/ar9280v1.ini"
 #include "ar5416/ar9280v2.ini"
-#include "ar5416/ar9285.ini"
-#include "ar5416/ar9285v2.ini"
-
 
 static const HAL_PERCAL_DATA ar9280_iq_cal = {		/* single sample */
 	.calName = "IQ", .calType = IQ_MISMATCH_CAL,
@@ -123,10 +119,6 @@ ar9280Attach(uint16_t devid, HAL_SOFTC sc,
 	AH5416(ah)->ah_writeIni		= ar9280WriteIni;
 	AH5416(ah)->ah_rx_chainmask	= AR9280_DEFAULT_RXCHAINMASK;
 	AH5416(ah)->ah_tx_chainmask	= AR9280_DEFAULT_TXCHAINMASK;
-	if (AR_SREV_KITE(ah)) {
-		AH5416(ah)->ah_rx_chainmask = AR9285_DEFAULT_RXCHAINMASK;
-		AH5416(ah)->ah_tx_chainmask = AR9285_DEFAULT_TXCHAINMASK;
-	}
 
 	if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
 		/* reset chip */
@@ -155,18 +147,7 @@ ar9280Attach(uint16_t devid, HAL_SOFTC sc,
 	AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;
 
 	/* setup common ini data; rf backends handle remainder */
-	/* XXX power consumption higer if clkreq is on */
-	if (AR_SREV_KITE_12_OR_LATER(ah)) {
-		HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes_v2, 6);
-		HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common_v2, 2);
-		HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
-		    ar9285PciePhy_clkreq_always_on_L1_v2, 2);
-	} else if (AR_SREV_KITE_10_OR_LATER(ah)) {
-		HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes, 6);
-		HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common, 2);
-		HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
-		    ar9285PciePhy_clkreq_always_on_L1, 2);
-	} else if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
+	if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
 		HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v2, 6);
 		HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v2, 2);
 		HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
@@ -181,10 +162,7 @@ ar9280Attach(uint16_t devid, HAL_SOFTC sc,
 	}
 	ar5416AttachPCIE(ah);
 
-	if (devid == AR9285_DEVID_PCIE)
-		ecode = ath_hal_v4kEepromAttach(ah);
-	else
-		ecode = ath_hal_v14EepromAttach(ah);
+	ecode = ath_hal_v14EepromAttach(ah);
 	if (ecode != HAL_OK)
 		goto bad;
 
@@ -257,19 +235,7 @@ ar9280Attach(uint16_t devid, HAL_SOFTC sc,
 			goto bad;		/* XXX ? try to continue */
 		}
 	}
-
-	if (AR_SREV_KITE_12_OR_LATER(ah)) {
-		switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) {
-		case AR5416_EEP_TXGAIN_HIGH_POWER:
-			HAL_INI_INIT(&ahp9280->ah_ini_txgain,
-			    ar9285Modes_high_power_tx_gain_v2, 6);
-			break;
-		default:
-			HAL_INI_INIT(&ahp9280->ah_ini_txgain,
-			    ar9285Modes_original_tx_gain_v2, 6);
-			break;
-		}
-	} else if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
+	if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
 		/* setp txgain table */
 		switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) {
 		case AR5416_EEP_TXGAIN_HIGH_POWER:
@@ -315,7 +281,7 @@ ar9280Attach(uint16_t devid, HAL_SOFTC sc,
 		OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
 
 	ar9280AniSetup(ah);			/* Anti Noise Immunity */
-	ar5416InitNfHistBuff(ah, AH5416(ah)->ah_cal.nfCalHist);
+	ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
 
 	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
 
@@ -335,10 +301,7 @@ ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
 		ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
 		OS_DELAY(1000);
 		OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
-		if (AR_SREV_KITE(ah))
-			OS_REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
-		else
-			OS_REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
+		OS_REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
 	}
 }
 
@@ -381,10 +344,6 @@ ar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
 		regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain,
 		    modesIndex, regWrites);
 	}
-	if (AR_SREV_KITE_12_OR_LATER(ah))
-		regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain,
-		    modesIndex, regWrites);
-
 	/* XXX Merlin 100us delay for shift registers */
 	regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
 	    1, regWrites);
@@ -711,10 +670,7 @@ ar9280FillCapabilityInfo(struct ath_hal *ah)
 
 	if (!ar5416FillCapabilityInfo(ah))
 		return AH_FALSE;
-	if (AR_SREV_KITE_10_OR_LATER(ah))
-		pCap->halNumGpioPins = 12;
-	else
-		pCap->halNumGpioPins = 10;
+	pCap->halNumGpioPins = 10;
 	pCap->halWowSupport = AH_TRUE;
 	pCap->halWowMatchPatternExact = AH_TRUE;
 #if 0
@@ -774,12 +730,9 @@ ar9280SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)
 static const char*
 ar9280Probe(uint16_t vendorid, uint16_t devid)
 {
-	if (vendorid == ATHEROS_VENDOR_ID) {
-		if (devid == AR9280_DEVID_PCI || devid == AR9280_DEVID_PCIE)
-			return "Atheros 9280";
-		else if (devid == AR9285_DEVID_PCIE)
-			return "Atheros 9285";
-	}
+	if (vendorid == ATHEROS_VENDOR_ID &&
+	    (devid == AR9280_DEVID_PCI || devid == AR9280_DEVID_PCIE))
+		return "Atheros 9280";
 	return AH_NULL;
 }
 AH_CHIP(AR9280, ar9280Probe, ar9280Attach);