Set SCSIGO generically before we determine the phase instead of doing it

in each phase routine.  Saves a few instructions.

Be more careful in how we deal with SXFRCTL0.  Or in the control bits of
interest instead of using mvi.  The kernel driver will set the ULTRAEN
bit of SXFRCTL0 if we are using Ultra (20MHz) mode and we don't want to
clobber it.

In sdtr_to_rate divide by two if we are in ultra mode to get the correct
setting since its a 20MHz instead of 10MHz scale.

1 files changed, 11 insertions, 12 deletions

diff --git a/sys/dev/aic7xxx/aic7xxx.seq b/sys/dev/aic7xxx/aic7xxx.seq
index 8fb7f21..c1c333e 100644
--- a/sys/dev/aic7xxx/aic7xxx.seq
+++ b/sys/dev/aic7xxx/aic7xxx.seq
@@ -41,13 +41,14 @@
 #
 ##-M#########################################################################
 
-VERSION AIC7XXX_SEQ_VER "$Id: aic7xxx.seq,v 1.18 1995/07/31 08:21:59 gibbs Exp $"
+VERSION AIC7XXX_SEQ_VER "$Id: aic7xxx.seq,v 1.21 1995/08/06 05:15:45 gibbs Exp $"
 
 SCBMASK		= 0xff
 
 SCSISEQ		= 0x00
 ENRSELI		= 0x10
 SXFRCTL0	= 0x01
+ULTRAEN		= 0x20
 SXFRCTL1	= 0x02
 SCSISIGI	= 0x03
 SCSISIGO	= 0x03
@@ -459,6 +460,7 @@ ITloop:
 
 	and	A,0xe0,SCSISIGI			# CDI|IOI|MSGI
 
+	mov	A		call scsisig
 	cmp	ALLZEROS,A	je p_dataout
 	cmp	A,0x40		je p_datain
 	cmp	A,0x80		je p_command
@@ -469,7 +471,6 @@ ITloop:
 	mvi	INTSTAT,BAD_PHASE		# unknown - signal driver
 
 p_dataout:
-	mvi	0		call scsisig	# !CDO|!IOO|!MSGO
 	mvi	DMAPARAMS,0x7d			# WIDEODD|SCSIEN|SDMAEN|HDMAEN|
 						#   DIRECTION|FIFORESET
 	jmp	data_phase_init
@@ -484,7 +485,6 @@ data_phase_reinit:
 # Reads should not use WIDEODD since it may make the last byte for a SG segment
 # go to the next segment.
 p_datain:
-	mvi	0x40		call scsisig	# !CDO|IOO|!MSGO
 	mvi	DMAPARAMS,0x39			# SCSIEN|SDMAEN|HDMAEN|
 						#   !DIRECTION|FIFORESET
 data_phase_init:
@@ -589,7 +589,6 @@ data_phase_finish:
 #  so we can copy those three bytes directly into HCNT.
 #
 p_command:
-	mvi	0x80		call scsisig	# CDO|!IOO|!MSGO
 	call	assert
 
 # Load HADDR and HCNT.  We can do this in one bcopy since they are neighbors
@@ -607,7 +606,6 @@ p_command:
 #  and store it into the SCB.
 #
 p_status:
-	mvi	0xc0		call scsisig	# CDO|IOO|!MSGO
 
 	mvi	SCBARRAY+14	call inb_first
 	jmp	mesgin_done
@@ -616,7 +614,6 @@ p_status:
 #  took us into this phase anyway, build a no-op message and send it.
 #
 p_mesgout:
-	mvi	0xa0		call scsisig	# CDO|!IOO|MSGO
 	mvi	0x8		call mk_mesg	# build NOP message
 
 	clr     STCNT+2
@@ -676,7 +673,8 @@ p_mesgout5:
 
 	and	A,0xe0,SCSISIGI			# CDI|IOI|MSGI
 	cmp	A,0xa0		jne p_mesgout6
-	mvi	0x10		call scsisig	# ATNO - re-assert ATN
+	or	SINDEX,0x10,SIGSTATE		# turn on ATNO
+	call	scsisig				# ATNO - re-assert ATN
 
 	jmp	ITloop
 
@@ -694,7 +692,6 @@ p_mesgout6:
 #  to a data I/O phase.
 #
 p_mesgin:
-	mvi	0xe0		call scsisig	# CDO|IOO|MSGO
 	mvi	A		call inb_first	# read the 1st message byte
 	mvi	REJBYTE,A			# save it for the driver
 
@@ -757,11 +754,12 @@ status_ok:
 	mov	A,FUNCTION1
 	test	SCBARRAY+1,0x88 jz clear_a
 	xor	ACTIVE_B,A
-	jmp	complete
+	jmp	immediate
 
 clear_a:
 	xor	ACTIVE_A,A
 
+immediate:
 	test    SCBARRAY+11,0xff jnz complete  # Immediate message complete
 # Pause the sequencer until the driver gets around to handling the command
 # complete.  This is so that any action that might require carefull timing
@@ -1059,7 +1057,7 @@ initialize_for_target:
 #
 	clr	SIGSTATE 
 
-	mvi	SXFRCTL0,0x8a			# DFON|SPIOEN|CLRCHN
+	or	SXFRCTL0,0x8a			# DFON|SPIOEN|CLRCHN
 
 #  Make sure that the system knows we have not been through a DATA
 #  phase.
@@ -1220,7 +1218,8 @@ sdtr_to_rate_loop:
 	jmp	sdtr_to_rate_loop
 sdtr_to_rate_done:
 	shr	RETURN_1,0x2
-	add	RETURN_1,0x18	ret
-
+	add	RETURN_1,0x18
+	test	SXFRCTL0,ULTRAEN jz return
+	shr	RETURN_1,0x1
 return:
 	ret