diff options
| author | gibbs <gibbs@FreeBSD.org> | 1998-12-15 08:22:42 +0000 |
|---|---|---|
| committer | gibbs <gibbs@FreeBSD.org> | 1998-12-15 08:22:42 +0000 |
| commit | 4bb599f96ca8518733c65bfc1ae889e53f69d282 (patch) | |
| tree | 5727a212c14d64ba0911fe96bfd4eb9dfde75eb7 /sys/dev/aic7xxx/aic7xxx.reg | |
| parent | 41e7e01c3b4d0b2cfd3e5887f58ed3dc5ad4166a (diff) | |
| download | FreeBSD-src-4bb599f96ca8518733c65bfc1ae889e53f69d282.zip FreeBSD-src-4bb599f96ca8518733c65bfc1ae889e53f69d282.tar.gz | |
Perform a save data pointers operation if a data transfer was performed
in target mode, but we are not completing the command.
Use a template of allowed bus arbitration phases to selectively and
dynamically enable/disable initiator or target (re)selection.
Properly handle timeouts for target role transactions - just go to the
bus free state and report the error to the peripheral driver.
Checkpoint support for the XPT_ABORT_CCB function code. This currently
handles the accept tio and immediate notify ccb types, but does not
handle the continue target I/O or SCSI I/O ccb types. This is enough
to handle dynamic target enable/disable events.
Clean up the SCSI reset code so that we perform at most 1 SCSI bus
reset at initialization, the reset requested by the XPT layer.
Diffstat (limited to 'sys/dev/aic7xxx/aic7xxx.reg')
| -rw-r--r-- | sys/dev/aic7xxx/aic7xxx.reg | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/sys/dev/aic7xxx/aic7xxx.reg b/sys/dev/aic7xxx/aic7xxx.reg index bcb96c2..f6138f6 100644 --- a/sys/dev/aic7xxx/aic7xxx.reg +++ b/sys/dev/aic7xxx/aic7xxx.reg @@ -32,7 +32,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id: aic7xxx.reg,v 1.8 1998/11/23 01:33:47 gibbs Exp $ + * $Id: aic7xxx.reg,v 1.9 1998/12/10 04:14:50 gibbs Exp $ */ /* @@ -1316,6 +1316,21 @@ scratch_ram { } /* + * Sequences the kernel driver has okayed for us. This allows + * the driver to do things like prevent initiator or target + * operations. + */ + SCSISEQ_TEMPLATE { + size 1 + bit ENSELO 0x40 + bit ENSELI 0x20 + bit ENRSELI 0x10 + bit ENAUTOATNO 0x08 + bit ENAUTOATNI 0x04 + bit ENAUTOATNP 0x02 + } + + /* * These are reserved registers in the card's scratch ram. Some of * the values are specified in the AHA2742 technical reference manual * and are initialized by the BIOS at boot time. |
