aic7xxx.c:

aic7xxx.h:
	Split out core chip initialization into ahc_chip_init().
	This will allow us to reset the chip correctly at times
	other than initial chip setup.

aic7770.c
aic7xxx_pci.c:
	Flesh out bus chip init methods for our two
	bus attachments and use these, in addition to
	bus suspend/resume hooks to get the core in
	better shape for handling these events.

	When disabling PCI parity error checking, use FAILDIS.
	Although the chip docs indicate that clearing PERRESPEN
	should also work, it does not.

	Auto-disable pci parity error checking after informing
	the user of AHC_PCI_TARGET_PERR_THRESH number of parity
	errors observed as a target.

aic7xxx.h:
aic7xxx_pci.c
aic7770.c
aic7xxx.c
	Add the instruction_ram_size softc field.

	Remove the now unused stack_size softc field.

	Modify ahc_loadseq to return a failure code
	and to actually check the downloaded instruction
	count against the limit set in our softc.

	Modify callers of ahc_loadseq to handle load
	failures as appropriate.

	Set instruction RAM sizes for each chip type.

aic7xxx_pci.c:
	Add some delay in the aic785X termination
	control code.  This may fix problems with
	the 2930.

	Be consistent in how we access config space
	registers.  16bit registers are accessed using
	16bit ops.

aic7xxx.c:
	Correct spelling errors.

	Have ahc_force_renegotiation() take a devinfo as is done
	in the U320 driver.  Use this argument to correct a bug
	in the selection timeout handler where we forced a renegotiation
	with the last device that had set SAVED_SCSIID.  SAVED_SCSIID
	is only updated once a selection is *sucessfull* and so is
	stale for any selection timeout.

	Cleanup the setup of the devinfo for busfree events.  We
	now use this devinfo for a call to ahc_force_renegotiation()
	at the bottom of the routine, so it must be initialized in
	all cases.

	In ahc_pause_and_flushwork(), adjust the loop so that it
	will exit in the hot-eject case even if the INT_PEND mask
	is something other than 0xFF (as it is in this driver).

	Correct a wrapping string constant.

	Call ahc_fini_scbdata() after shutdown so that
	any ahc_chip_init() routine that might access
	SCB data will not access free'd memory.

	Correctly setup our buffer tag to indicate that 39bit
	addressing is available if in 39bit addressing mode.

	Rearrange some variable declarations based on
	type size.

aic7xxx.c
aic7xxx.h:
aic7xxx.reg:
	Consistently use MAX_OFFSET for the user max syncrate
	set from non-volatile storage.  This ensures that the
	offset does not conflict with AHC_OFFSET_UNKNOWN.

	Change AHC_OFFSET_UNKNOWN to 0xFF.  This is
	a value that the curr->offset can never be,
	unlike '0' which we previously used.  This
	fixes code that only checks for a non-zero
	offset to determine if a sync negotiation
	is required since it will fire in the unknown
	case even if the goal is async.

	Change MAX_OFFSET to 0x7f which is the max
	offset U160 aic7xxx controllers can negotiate.
	This ensures that curr->offset will not
	match AHC_OFFSET_UNKNOWN.

aic7xxx_inline.h:
	Have our inline interrupt handler return with a value
	indicating whether we serviced a real interrupt.  This
	is required for Linux support.

	Return earlier if the interrupt is not for us.

1 files changed, 65 insertions, 29 deletions

diff --git a/sys/dev/aic7xxx/aic7xxx.h b/sys/dev/aic7xxx/aic7xxx.h
index a30deb3..de1a221 100644
--- a/sys/dev/aic7xxx/aic7xxx.h
+++ b/sys/dev/aic7xxx/aic7xxx.h
@@ -37,7 +37,7 @@
  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGES.
  *
- * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.h#70 $
+ * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.h#75 $
  *
  * $FreeBSD$
  */
@@ -365,14 +365,15 @@ typedef enum {
 	AHC_LSCBS_ENABLED     = 0x2000000, /* 64Byte SCBs enabled */
 	AHC_SCB_CONFIG_USED   = 0x4000000, /* No SEEPROM but SCB2 had info. */
 	AHC_NO_BIOS_INIT      = 0x8000000, /* No BIOS left over settings. */
-	AHC_DISABLE_PCI_PERR  = 0x10000000
+	AHC_DISABLE_PCI_PERR  = 0x10000000,
+	AHC_HAS_TERM_LOGIC    = 0x20000000
 } ahc_flag;
 
 /************************* Hardware  SCB Definition ***************************/
 
 /*
  * The driver keeps up to MAX_SCB scb structures per card in memory.  The SCB
- * consists of a "hardware SCB" mirroring the fields availible on the card
+ * consists of a "hardware SCB" mirroring the fields available on the card
  * and additional information the kernel stores for each transaction.
  *
  * To minimize space utilization, a portion of the hardware scb stores
@@ -691,7 +692,7 @@ struct ahc_tmode_lstate;
 
 #define AHC_WIDTH_UNKNOWN	0xFF
 #define AHC_PERIOD_UNKNOWN	0xFF
-#define AHC_OFFSET_UNKNOWN	0x0
+#define AHC_OFFSET_UNKNOWN	0xFF
 #define AHC_PPR_OPTS_UNKNOWN	0xFF
 
 /*
@@ -877,31 +878,39 @@ typedef enum {
 /*********************** Software Configuration Structure *********************/
 TAILQ_HEAD(scb_tailq, scb);
 
-struct ahc_suspend_channel_state {
-	uint8_t	scsiseq;
-	uint8_t	sxfrctl0;
-	uint8_t	sxfrctl1;
-	uint8_t	simode0;
-	uint8_t	simode1;
-	uint8_t	seltimer;
-	uint8_t	seqctl;
+struct ahc_aic7770_softc {
+	/*
+	 * Saved register state used for chip_init().
+	 */
+	uint8_t busspd;
+	uint8_t bustime;
+};
+
+struct ahc_pci_softc {
+	/*
+	 * Saved register state used for chip_init().
+	 */
+	uint32_t  devconfig;
+	uint16_t  targcrccnt;
+	uint8_t   command;
+	uint8_t   csize_lattime;
+	uint8_t   optionmode;
+	uint8_t   crccontrol1;
+	uint8_t   dscommand0;
+	uint8_t   dspcistatus;
+	uint8_t   scbbaddr;
+	uint8_t   dff_thrsh;
 };
 
-struct ahc_suspend_state {
-	struct	ahc_suspend_channel_state channel[2];
-	uint8_t	optionmode;
-	uint8_t	dscommand0;
-	uint8_t	dspcistatus;
-	/* hsmailbox */
-	uint8_t	crccontrol1;
-	uint8_t	scbbaddr;
-	/* Host and sequencer SCB counts */
-	uint8_t	dff_thrsh;
-	uint8_t	*scratch_ram;
-	uint8_t	*btt;
+union ahc_bus_softc {
+	struct ahc_aic7770_softc aic7770_softc;
+	struct ahc_pci_softc pci_softc;
 };
 
 typedef void (*ahc_bus_intr_t)(struct ahc_softc *);
+typedef int (*ahc_bus_chip_init_t)(struct ahc_softc *);
+typedef int (*ahc_bus_suspend_t)(struct ahc_softc *);
+typedef int (*ahc_bus_resume_t)(struct ahc_softc *);
 typedef void ahc_callback_t (void *);
 
 struct ahc_softc {
@@ -937,6 +946,11 @@ struct ahc_softc {
 	struct scb_tailq	  untagged_queues[AHC_NUM_TARGETS];
 
 	/*
+	 * Bus attachment specific data.
+	 */
+	union ahc_bus_softc	  bus_softc;
+
+	/*
 	 * Platform specific data.
 	 */
 	struct ahc_platform_data *platform_data;
@@ -952,6 +966,22 @@ struct ahc_softc {
 	ahc_bus_intr_t		  bus_intr;
 
 	/*
+	 * Bus specific initialization required
+	 * after a chip reset.
+	 */
+	ahc_bus_chip_init_t	  bus_chip_init;
+
+	/*
+	 * Bus specific suspend routine.
+	 */
+	ahc_bus_suspend_t	  bus_suspend;
+
+	/*
+	 * Bus specific resume routine.
+	 */
+	ahc_bus_resume_t	  bus_resume;
+
+	/*
 	 * Target mode related state kept on a per enabled lun basis.
 	 * Targets that are not enabled will have null entries.
 	 * As an initiator, we keep one target entry for our initiator
@@ -1043,9 +1073,6 @@ struct ahc_softc {
 	 */
 	bus_addr_t		  dma_bug_buf;
 
-	/* Information saved through suspend/resume cycles */
-	struct ahc_suspend_state  suspend_state;
-
 	/* Number of enabled target mode device on this card */
 	u_int			  enabled_luns;
 
@@ -1055,7 +1082,16 @@ struct ahc_softc {
 	/* PCI cacheline size. */
 	u_int			  pci_cachesize;
 
-	u_int			  stack_size;
+	/*
+	 * Count of parity errors we have seen as a target.
+	 * We auto-disable parity error checking after seeing
+	 * AHC_PCI_TARGET_PERR_THRESH number of errors.
+	 */
+	u_int			  pci_target_perr_count;
+#define		AHC_PCI_TARGET_PERR_THRESH	10
+
+	/* Maximum number of sequencer instructions supported. */
+	u_int			  instruction_ram_size;
 
 	/* Per-Unit descriptive information */
 	const char		 *description;
@@ -1152,6 +1188,7 @@ int		ahc_match_scb(struct ahc_softc *ahc, struct scb *scb,
 struct ahc_softc	*ahc_alloc(void *platform_arg, char *name);
 int			 ahc_softc_init(struct ahc_softc *);
 void			 ahc_controller_info(struct ahc_softc *ahc, char *buf);
+int			 ahc_chip_init(struct ahc_softc *ahc);
 int			 ahc_init(struct ahc_softc *ahc);
 void			 ahc_intr_enable(struct ahc_softc *ahc, int enable);
 void			 ahc_pause_and_flushwork(struct ahc_softc *ahc);
@@ -1167,7 +1204,6 @@ int			 ahc_reset(struct ahc_softc *ahc);
 void			 ahc_shutdown(void *arg);
 
 /*************************** Interrupt Services *******************************/
-void			ahc_pci_intr(struct ahc_softc *ahc);
 void			ahc_clear_intstat(struct ahc_softc *ahc);
 void			ahc_run_qoutfifo(struct ahc_softc *ahc);
 #ifdef AHC_TARGET_MODE