Different VIA host bridges use different offsets to their AGP config

registers, so add a register offset array to the softc.  We key off the
device ID to determine which set of register offsets.  Currently the 8385
host bridge used on amd64 is the only bridge to use the AGP3_VIA_*
register offsets and all other bridges use the AGP_VIA_* offsets.  It is
currently unclear if the AGP3_VIA_* offsets are for VIA bridges that
implement AGP 3.0 bridges or just for amd64 bridges.

Submitted by:	Kenneth Culver culverk at sweetdreamsracing dot biz

2 files changed, 41 insertions, 9 deletions

diff --git a/sys/dev/agp/agp_via.c b/sys/dev/agp/agp_via.c
index e6cd94a..8d94200 100644
--- a/sys/dev/agp/agp_via.c
+++ b/sys/dev/agp/agp_via.c
@@ -48,12 +48,22 @@ __FBSDID("$FreeBSD$");
 #include <vm/vm_object.h>
 #include <vm/pmap.h>
 
+#define	REG_GARTCTRL	0
+#define	REG_APSIZE	1
+#define	REG_ATTBASE	2
+
 struct agp_via_softc {
 	struct agp_softc agp;
 	u_int32_t	initial_aperture; /* aperture size at startup */
 	struct agp_gatt *gatt;
+	int		*regs;
 };
 
+static int via_v2_regs[] = { AGP_VIA_GARTCTRL, AGP_VIA_APSIZE,
+    AGP_VIA_ATTBASE };
+static int via_v3_regs[] = { AGP3_VIA_GARTCTRL, AGP3_VIA_APSIZE,
+    AGP3_VIA_ATTBASE };
+
 static const char*
 agp_via_match(device_t dev)
 {
@@ -77,6 +87,8 @@ agp_via_match(device_t dev)
 		return ("VIA 82C694X (Apollo Pro 133A) host to PCI bridge");
 	case 0x06911106:
 		return ("VIA 82C691 (Apollo Pro) host to PCI bridge");
+	case 0x31881106:
+		return ("VIA 8385 host to PCI bridge");
 	};
 
 	if (pci_get_vendor(dev) == 0x1106)
@@ -109,6 +121,15 @@ agp_via_attach(device_t dev)
 	struct agp_gatt *gatt;
 	int error;
 
+	switch (pci_get_devid(dev)) {
+	case 0x31881106:
+		sc->regs = via_v3_regs;
+		break;
+	default:
+		sc->regs = via_v2_regs;
+		break;
+	}
+	
 	error = agp_generic_attach(dev);
 	if (error)
 		return error;
@@ -132,10 +153,10 @@ agp_via_attach(device_t dev)
 	sc->gatt = gatt;
 
 	/* Install the gatt. */
-	pci_write_config(dev, AGP_VIA_ATTBASE, gatt->ag_physical | 3, 4);
+	pci_write_config(dev, sc->regs[REG_ATTBASE], gatt->ag_physical | 3, 4);
 	
 	/* Enable the aperture. */
-	pci_write_config(dev, AGP_VIA_GARTCTRL, 0x0f, 4);
+	pci_write_config(dev, sc->regs[REG_GARTCTRL], 0x0f, 4);
 
 	return 0;
 }
@@ -150,8 +171,8 @@ agp_via_detach(device_t dev)
 	if (error)
 		return error;
 
-	pci_write_config(dev, AGP_VIA_GARTCTRL, 0, 4);
-	pci_write_config(dev, AGP_VIA_ATTBASE, 0, 4);
+	pci_write_config(dev, sc->regs[REG_GARTCTRL], 0, 4);
+	pci_write_config(dev, sc->regs[REG_ATTBASE], 0, 4);
 	AGP_SET_APERTURE(dev, sc->initial_aperture);
 	agp_free_gatt(sc->gatt);
 
@@ -161,9 +182,10 @@ agp_via_detach(device_t dev)
 static u_int32_t
 agp_via_get_aperture(device_t dev)
 {
+	struct agp_via_softc *sc = device_get_softc(dev);
 	u_int32_t apsize;
 
-	apsize = pci_read_config(dev, AGP_VIA_APSIZE, 1) & 0x1f;
+	apsize = pci_read_config(dev, sc->regs[REG_APSIZE], 1) & 0x1f;
 
 	/*
 	 * The size is determined by the number of low bits of
@@ -178,6 +200,7 @@ agp_via_get_aperture(device_t dev)
 static int
 agp_via_set_aperture(device_t dev, u_int32_t aperture)
 {
+	struct agp_via_softc *sc = device_get_softc(dev);
 	u_int32_t apsize;
 
 	/*
@@ -191,7 +214,7 @@ agp_via_set_aperture(device_t dev, u_int32_t aperture)
 	if ((((apsize ^ 0xff) << 20) | ((1 << 20) - 1)) + 1 != aperture)
 		return EINVAL;
 
-	pci_write_config(dev, AGP_VIA_APSIZE, apsize, 1);
+	pci_write_config(dev, sc->regs[REG_APSIZE], apsize, 1);
 
 	return 0;
 }
@@ -223,8 +246,10 @@ agp_via_unbind_page(device_t dev, int offset)
 static void
 agp_via_flush_tlb(device_t dev)
 {
-	pci_write_config(dev, AGP_VIA_GARTCTRL, 0x8f, 4);
-	pci_write_config(dev, AGP_VIA_GARTCTRL, 0x0f, 4);
+	struct agp_via_softc *sc = device_get_softc(dev);
+
+	pci_write_config(dev, sc->regs[REG_GARTCTRL], 0x8f, 4);
+	pci_write_config(dev, sc->regs[REG_GARTCTRL], 0x0f, 4);
 }
 
 static device_method_t agp_via_methods[] = {
diff --git a/sys/dev/agp/agpreg.h b/sys/dev/agp/agpreg.h
index 13df29e..a5373e4 100644
--- a/sys/dev/agp/agpreg.h
+++ b/sys/dev/agp/agpreg.h
@@ -87,13 +87,20 @@
 #define AGP_INTEL_I8XX_ERRSTS	0xc8
 
 /*
- * Config offsets for VIA AGP chipsets.
+ * Config offsets for VIA AGP 2.x chipsets.
  */
 #define AGP_VIA_GARTCTRL	0x80
 #define AGP_VIA_APSIZE		0x84
 #define AGP_VIA_ATTBASE		0x88
 
 /*
+ * Config offsets for VIA AGP 3.0 chipsets.
+ */
+#define AGP3_VIA_GARTCTRL        0x90
+#define AGP3_VIA_APSIZE          0x94
+#define AGP3_VIA_ATTBASE         0x98
+
+/*
  * Config offsets for SiS AGP chipsets.
  */
 #define AGP_SIS_ATTBASE		0x90