Add support for the AdvanSys ASC38C0800 Ultra2 chipset. Preliminary

support is also included for the ASC38C1600 Ultra160 chipset, but
as firmware is not yet available for this chip, it is disabled.

Approved by: jkh@FreeBSD.org

1 files changed, 364 insertions, 97 deletions

diff --git a/sys/dev/advansys/adwlib.h b/sys/dev/advansys/adwlib.h
index 3773cf1..d32bfb9 100644
--- a/sys/dev/advansys/adwlib.h
+++ b/sys/dev/advansys/adwlib.h
@@ -2,7 +2,7 @@
  * Definitions for low level routines and data structures
  * for the Advanced Systems Inc. SCSI controllers chips.
  *
- * Copyright (c) 1998 Justin T. Gibbs.
+ * Copyright (c) 1998, 1999, 2000 Justin T. Gibbs.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -10,7 +10,7 @@
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions, and the following disclaimer,
- *    without modification, immediately at the beginning of the file.
+ *    without modification.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
@@ -61,6 +61,12 @@
 #define ADW_MAX_TID		15
 #define ADW_MAX_LUN		7
 
+#define	ADW_ALL_TARGETS		0xFFFF
+
+#define ADW_TARGET_GROUP(tid)		((tid) & ~0x3)
+#define ADW_TARGET_GROUP_SHIFT(tid)	(((tid) & 0x3) * 4)
+#define ADW_TARGET_GROUP_MASK(tid)	(0xF << ADW_TARGET_GROUP_SHIFT(tid))
+
 /*
  * Board Register offsets.
  */
@@ -68,6 +74,7 @@
 #define		ADW_INTR_STATUS_INTRA		0x01
 #define		ADW_INTR_STATUS_INTRB		0x02
 #define		ADW_INTR_STATUS_INTRC		0x04
+#define		ADW_INTR_STATUS_INTRALL		0x07
 
 
 #define ADW_SIGNATURE_WORD			0x0000
@@ -164,6 +171,27 @@
 #define		ADW_SCSI_CFG1_ILLEGAL_CABLE_CONF_B_MASK	\
 (ADW_SCSI_CFG1_EXT8_MASK|ADW_SCSI_CFG1_INT8_MASK|ADW_SCSI_CFG1_INT16_MASK)
 
+/*
+ * Addendum for ASC-38C0800 Chip
+ */
+#define		ADW2_SCSI_CFG1_DIS_TERM_DRV	0x4000	/*
+							 * The Terminators
+							 * must be disabled
+							 * in order to detect
+							 * cable presence
+							 */
+
+#define		ADW2_SCSI_CFG1_DEV_DETECT	0x1C00
+#define		ADW2_SCSI_CFG1_DEV_DETECT_HVD	0x1000
+#define		ADW2_SCSI_CFG1_DEV_DETECT_LVD	0x0800
+#define		ADW2_SCSI_CFG1_DEV_DETECT_SE	0x0400
+
+#define		ADW2_SCSI_CFG1_TERM_CTL_LVD	0x00C0	/* Ultra2 Only */
+#define		ADW2_SCSI_CFG1_TERM_LVD_HI	0x0080 
+#define		ADW2_SCSI_CFG1_TERM_LVD_LO	0x0040
+#define		ADW2_SCSI_CFG1_EXTLVD_MASK	0x0008	/* ExtLVD cable pres */
+#define		ADW2_SCSI_CFG1_INTLVD_MASK	0x0004	/* IntLVD cable pres */
+
 #define ADW_MEM_CFG				0x0010
 #define 	ADW_MEM_CFG_BIOS_EN		0x40
 #define		ADW_MEM_CFG_FAST_EE_CLK		0x20	/* Diagnostic Bit */
@@ -175,6 +203,12 @@
 #define		ADW_MEM_CFG_RAM_SZ_32KB		0x10
 #define		ADW_MEM_CFG_RAM_SZ_64KB		0x14
 
+#define	ADW_GPIO_CNTL				0x0011
+#define	ADW_GPIO_DATA				0x0012
+
+#define	ADW_COMMA				0x0014
+#define ADW_COMMB				0x0018  
+
 #define ADW_EEP_CMD				0x001A
 #define		ADW_EEP_CMD_READ		0x0080	/* or in address */
 #define		ADW_EEP_CMD_WRITE		0x0040	/* or in address */
@@ -191,11 +225,11 @@
 #define		ADW_DMA_CFG0_FIFO_THRESH	0x70
 #define		ADW_DMA_CFG0_FIFO_THRESH_16B	0x00
 #define		ADW_DMA_CFG0_FIFO_THRESH_32B	0x20
-#define		ADW_DMA_CFG0_IFO_THRESH_48B	0x30
-#define		ADW_DMA_CFG0_IFO_THRESH_64B	0x40
-#define		ADW_DMA_CFG0_IFO_THRESH_80B	0x50
-#define		ADW_DMA_CFG0_IFO_THRESH_96B	0x60
-#define		ADW_DMA_CFG0_IFO_THRESH_112B	0x70
+#define		ADW_DMA_CFG0_FIFO_THRESH_48B	0x30
+#define		ADW_DMA_CFG0_FIFO_THRESH_64B	0x40
+#define		ADW_DMA_CFG0_FIFO_THRESH_80B	0x50
+#define		ADW_DMA_CFG0_FIFO_THRESH_96B	0x60
+#define		ADW_DMA_CFG0_FIFO_THRESH_112B	0x70
 #define		ADW_DMA_CFG0_START_CTL_MASK	0x0C
 #define		ADW_DMA_CFG0_START_CTL_TH	0x00 /* Start on thresh */
 #define		ADW_DMA_CFG0_START_CTL_IDLE	0x04 /* Start when idle */
@@ -206,18 +240,57 @@
 #define		ADW_DMA_CFG0_READ_CMD_MRL	0x02
 #define		ADW_DMA_CFG0_READ_CMD_MRM	0x03
 
+#define ADW_TICKLE				0x0022
+#define		ADW_TICKLE_NOP			0x00
+#define		ADW_TICKLE_A			0x01
+#define		ADW_TICKLE_B			0x02
+#define		ADW_TICKLE_C			0x03
+
 /* Program Counter */
 #define ADW_PC					0x2A
 
 #define ADW_SCSI_CTRL				0x0034
 #define		ADW_SCSI_CTRL_RSTOUT		0x2000
 
+/*
+ * ASC-38C0800 RAM BIST Register bit definitions
+ */
+#define ADW_RAM_BIST				0x0038
+#define		ADW_RAM_BIST_RAM_TEST_MODE	0x80
+#define		ADW_RAM_BIST_PRE_TEST_MODE	0x40
+#define		ADW_RAM_BIST_NORMAL_MODE	0x00
+#define		ADW_RAM_BIST_RAM_TEST_DONE	0x10
+#define		ADW_RAM_BIST_RAM_TEST_STATUS	0x0F
+#define		ADW_RAM_BIST_RAM_TEST_HOST_ERR	0x08
+#define		ADW_RAM_BIST_RAM_TEST_RAM_ERR	0x04
+#define		ADW_RAM_BIST_RAM_TEST_RISC_ERR	0x02
+#define		ADW_RAM_BIST_RAM_TEST_SCSI_ERR	0x01
+#define		ADW_RAM_BIST_RAM_TEST_SUCCESS	0x00
+#define		ADW_RAM_BIST_PRE_TEST_VALUE	0x05
+#define		ADW_RAM_BIST_NORMAL_VALUE	0x00 
+#define ADW_PLL_TEST				0x0039
+
 #define	ADW_SCSI_RESET_HOLD_TIME_US		60
 
 /* LRAM Constants */
-#define ADW_CONDOR_MEMSIZE	0x2000 /* 8 KB Internal Memory */
-#define ADW_MC_BIOSMEM		0x0040 /* BIOS RISC Memory Start */
-#define ADW_MC_BIOSLEN		0x0050 /* BIOS RISC Memory Length */
+#define ADW_3550_MEMSIZE	0x2000	/* 8 KB Internal Memory */
+#define ADW_3550_IOLEN		0x40	/* I/O Port Range in bytes */
+
+#define ADW_38C0800_MEMSIZE	0x4000	/* 16 KB Internal Memory */
+#define ADW_38C0800_IOLEN	0x100	/* I/O Port Range in bytes */
+
+#define ADW_38C1600_MEMSIZE	0x4000	/* 16 KB Internal Memory */
+#define ADW_38C1600_IOLEN	0x100	/* I/O Port Range in bytes */
+#define ADW_38C1600_MEMLEN	0x1000	/* Memory Range 4KB */
+
+#define ADW_MC_BIOSMEM		0x0040	/* BIOS RISC Memory Start */
+#define ADW_MC_BIOSLEN		0x0050	/* BIOS RISC Memory Length */
+
+#define	PCI_ID_ADVANSYS_3550		0x230010CD00000000ull
+#define	PCI_ID_ADVANSYS_38C0800_REV1	0x250010CD00000000ull
+#define	PCI_ID_ADVANSYS_38C1600_REV1	0x270010CD00000000ull
+#define PCI_ID_ALL_MASK             	0xFFFFFFFFFFFFFFFFull
+#define PCI_ID_DEV_VENDOR_MASK      	0xFFFFFFFF00000000ull
 
 /* ====================== SCSI Request Structures =========================== */
 
@@ -240,8 +313,8 @@ struct adw_sg_elm {
 struct adw_sg_block {   
 	u_int8_t  reserved1;
 	u_int8_t  reserved2;
-	u_int8_t  first_entry_no;  /* starting entry number */
-	u_int8_t  last_entry_no;   /* last entry number */
+	u_int8_t  reserved3;
+	u_int8_t  sg_cnt;	/* Valid entries in this block */
 	u_int32_t sg_busaddr_next; /* link to the next sg block */
 	struct	  adw_sg_elm sg_list[ADW_NO_OF_SG_PER_BLOCK];
 };
@@ -291,28 +364,42 @@ typedef enum {
  */
 struct adw_scsi_req_q {
 	u_int8_t  cntl;		  /* Ucode flags and state. */
-	u_int8_t  sg_entry_cnt;	  /* SG element count. Zero for no SG. */
+	u_int8_t  target_cmd;
 	u_int8_t  target_id;	  /* Device target identifier. */
 	u_int8_t  target_lun;	  /* Device target logical unit number. */
 	u_int32_t data_addr;	  /* Data buffer physical address. */
 	u_int32_t data_cnt;	  /* Data count. Ucode sets to residual. */
-	u_int32_t sense_addr;	  /* Sense buffer physical address. */
-	u_int32_t srb_ptr;	  /* Driver request pointer. */
-	u_int8_t  a_flag;	  /* Adv Library flag field. */
+	u_int32_t sense_baddr;	  /* Sense buffer bus address. */
+	u_int32_t carrier_baddr;  /* Carrier bus address. */
+	u_int8_t  mflag;	  /* microcode flag field. */
 	u_int8_t  sense_len;	  /* Auto-sense length. Residual on complete. */
 	u_int8_t  cdb_len;	  /* SCSI CDB length. */
-	u_int8_t  tag_code;	  /* SCSI-2 Tag Queue Code: 00, 20-22. */
+	u_int8_t  scsi_cntl;	  /* SCSI command control flags (tags, nego) */
+#define		ADW_QSC_NO_DISC		0x01
+#define		ADW_QSC_NO_TAGMSG	0x02
+#define		ADW_QSC_NO_SYNC		0x04
+#define		ADW_QSC_NO_WIDE		0x08
+#define		ADW_QSC_REDO_DTR	0x10 /* Renegotiate WDTR/SDTR */
+#define		ADW_QSC_HEAD_OF_Q_TAG	0x40
+#define		ADW_QSC_ORDERED_Q_TAG	0x80
 	u_int8_t  done_status;	  /* Completion status. */
 	u_int8_t  scsi_status;	  /* SCSI status byte. */
 	u_int8_t  host_status;	  /* Ucode host status. */
-
-	u_int8_t  ux_sg_ix;       /* Ucode working SG variable. */
+	u_int8_t  sg_wk_ix;	  /* Microcode working SG index. */
 	u_int8_t  cdb[12];        /* SCSI command block. */
 	u_int32_t sg_real_addr;   /* SG list physical address. */ 
-	u_int32_t free_scsiq_link;/* Unused */
-	u_int32_t ux_wk_data_cnt; /* Saved data count at disconnection. */
-	u_int32_t scsi_req_baddr; /* Bus address of this request. */
-	u_int32_t sg_block_index; /* sg_block tag (Unused) */
+	u_int32_t scsi_req_baddr; /* Bus address of this structure. */
+	u_int32_t sg_wk_data_cnt; /* Saved data count at disconnection. */
+	/*
+	 * The 'tokens' placed in these two fields are
+	 * used to identify the scsi request and the next
+	 * carrier in the response queue, *not* physical
+	 * addresses.  This driver uses byte offsets for
+	 * portability and speed of mapping back to either
+	 * a virtual or physical address.
+	 */
+	u_int32_t scsi_req_bo;	  /* byte offset of this structure */
+	u_int32_t carrier_bo;	  /* byte offst of our carrier. */
 };
 
 typedef enum {
@@ -332,23 +419,6 @@ struct acb {
 	SLIST_ENTRY(acb) links;
 };
 
-typedef struct {
-	u_int16_t bios_init_dis    :1,/* don't act as initiator. */
-	  	  bios_ext_trans   :1,/* > 1 GB support */
-		  bios_more_2disk  :1,/* > 2 Disk Support */
-		  bios_no_removable:1,/* don't support removables */
-		  bios_cd_boot     :1,/* support bootable CD */
-				   :1,
-		  bios_multi_lun   :1,/* support multiple LUNs */
-		  bios_message     :1,/* display BIOS message */
-				   :1,
-		  bios_reset_sb    :1,/* Reset SCSI bus during init. */
-				   :1,
-		  bios_quiet	   :1,/* No verbose initialization. */
-		  bios_scsi_par_en :1,/* SCSI parity enabled */
-				   :3;
-} adw_bios_ctrl;
-
 /*
  * EEPROM configuration format
  *
@@ -371,6 +441,7 @@ struct adw_eeprom
 #define		ADW_EEPROM_BIG_ENDIAN	0x8000
 #define		ADW_EEPROM_BIOS_ENABLE	0x4000
 #define		ADW_EEPROM_TERM_POL	0x2000
+#define		ADW_EEPROM_CIS_LD	0x1000
 
 				/* bit 13 set - Term Polarity Control */
 				/* bit 14 set - BIOS Enable */
@@ -378,7 +449,15 @@ struct adw_eeprom
 	u_int16_t cfg_msw;	/* unused */
 	u_int16_t disc_enable;
 	u_int16_t wdtr_able;
-	u_int16_t sdtr_able;
+	union {
+		/*
+		 * sync enable bits for UW cards,
+		 * actual sync rate for TID 0-3
+		 * on U2W and U160 cards.
+		 */
+		u_int16_t sync_enable;
+		u_int16_t sdtr1;
+	} sync1;
 	u_int16_t start_motor;
 	u_int16_t tagqng_able;
 	u_int16_t bios_scan;
@@ -391,31 +470,70 @@ struct adw_eeprom
 	u_int8_t  bios_id_lun;	/*    high nibble is lun */  
 				/*    low nibble is scsi id */
 
-	u_int8_t  termination;	/* 0 - automatic */
+	u_int8_t  termination_se;	/* 0 - automatic */
 #define		ADW_EEPROM_TERM_AUTO 		0
 #define		ADW_EEPROM_TERM_OFF		1
 #define		ADW_EEPROM_TERM_HIGH_ON		2
 #define		ADW_EEPROM_TERM_BOTH_ON		3
 
-	u_int8_t  reserved1;	/*    reserved byte (not used) */                                  
-	adw_bios_ctrl bios_ctrl;
-
-	u_int16_t ultra_able;	/* 13 ULTRA speed able */ 
-	u_int16_t reserved2;	/* 14 reserved */
+	u_int8_t  termination_lvd;
+	u_int16_t bios_ctrl;
+#define		ADW_BIOS_INIT_DIS     0x0001 /* Don't act as initiator */
+#define		ADW_BIOS_EXT_TRANS    0x0002 /* > 1 GB support */
+#define		ADW_BIOS_MORE_2DISK   0x0004 /* > 1 GB support */
+#define		ADW_BIOS_NO_REMOVABLE 0x0008 /* don't support removable media */
+#define		ADW_BIOS_CD_BOOT      0x0010 /* support bootable CD */
+#define		ADW_BIOS_SCAN_EN      0x0020 /* BIOS SCAN enabled */
+#define		ADW_BIOS_MULTI_LUN    0x0040 /* probe luns */
+#define		ADW_BIOS_MESSAGE      0x0080 /* display BIOS message */
+#define		ADW_BIOS_RESET_BUS    0x0200 /* reset SCSI bus durint init */
+#define		ADW_BIOS_QUIET        0x0800 /* No verbose initialization */
+#define		ADW_BIOS_SCSI_PAR_EN  0x1000 /* SCSI parity enabled */
+
+	union {
+		/* 13
+		 * ultra enable bits for UW cards,
+		 * actual sync rate for TID 4-7
+		 * on U2W and U160 cards.
+		 */
+		u_int16_t ultra_enable;
+		u_int16_t sdtr2;
+	} sync2;
+	union {
+		/* 14
+		 * reserved for UW cards,
+		 * actual sync rate for TID 8-11
+		 * on U2W and U160 cards.
+		 */
+		u_int16_t reserved;
+		u_int16_t sdtr3;
+	} sync3;
 	u_int8_t  max_host_qng;	/* 15 maximum host queuing */
 	u_int8_t  max_dvc_qng;	/*    maximum per device queuing */
 	u_int16_t dvc_cntl;	/* 16 control bit for driver */
-	u_int16_t bug_fix;	/* 17 control bit for bug fix */
-	u_int16_t serial_number[3];
-	u_int16_t checksum;
-	u_int8_t  oem_name[16];
-	u_int16_t dvc_err_code;
-	u_int16_t adv_err_code;
-	u_int16_t adv_err_addr;
-	u_int16_t saved_dvc_err_code;
-	u_int16_t saved_adv_err_code;
-	u_int16_t saved_adv_err_addr;
-	u_int16_t num_of_err;
+	union {
+		/* 17
+		 * reserved for UW cards,
+		 * actual sync rate for TID 12-15
+		 * on U2W and U160 cards.
+		 */
+		u_int16_t reserved;
+		u_int16_t sdtr4;
+	} sync4;
+	u_int16_t serial_number[3]; /* 18-20 */
+	u_int16_t checksum;	/* 21 */
+	u_int8_t  oem_name[16];	/* 22 - 29 */
+	u_int16_t dvc_err_code;	/* 30 */
+	u_int16_t adv_err_code;	/* 31 */
+	u_int16_t adv_err_addr;	/* 32 */
+	u_int16_t saved_dvc_err_code; /* 33 */
+	u_int16_t saved_adv_err_code; /* 34 */
+	u_int16_t saved_adv_err_addr; /* 35 */
+	u_int16_t reserved[20];	      /* 36 - 55 */
+	u_int16_t cisptr_lsw;	/* 56 CIS data */
+	u_int16_t cisptr_msw;	/* 57 CIS data */
+	u_int32_t subid;	/* 58-59 SubSystem Vendor/Dev ID */
+	u_int16_t reserved2[4];
 };
 
 /* EEProm Addresses */
@@ -425,10 +543,53 @@ struct adw_eeprom
 #define	ADW_EEP_MAX_WORD_ADDR	(sizeof(struct adw_eeprom)/2)
 
 typedef enum {
+	ADW_CHIP_NONE,
+	ADW_CHIP_ASC3550,	/* Ultra-Wide IC */
+	ADW_CHIP_ASC38C0800,	/* Ultra2-Wide/LVD IC */
+	ADW_CHIP_ASC38C1600	/* Ultra3-Wide/LVD2 IC */
+} adw_chip;
+
+typedef enum {
+	ADW_FENONE	  = 0x0000,
+	ADW_ULTRA	  = 0x0001,	/* Supports 20MHz Transfers */
+	ADW_ULTRA2	  = 0x0002,	/* Supports 40MHz Transfers */
+	ADW_DT		  = 0x0004,	/* Supports Double Transistion REQ/ACK*/
+	ADW_WIDE  	  = 0x0008,	/* Wide Channel */
+	ADW_ASC3550_FE	  = ADW_ULTRA,	
+	ADW_ASC38C0800_FE = ADW_ULTRA2,
+	ADW_ASC38C1600_FE = ADW_ULTRA2|ADW_DT
+} adw_feature;
+
+typedef enum {
+	ADW_FNONE	  = 0x0000,
+	ADW_EEPROM_FAILED = 0x0001
+} adw_flag;
+
+typedef enum {
 	ADW_STATE_NORMAL	= 0x00,
 	ADW_RESOURCE_SHORTAGE	= 0x01
 } adw_state;
 
+typedef enum {
+	ADW_MC_SDTR_ASYNC,
+	ADW_MC_SDTR_5,
+	ADW_MC_SDTR_10,
+	ADW_MC_SDTR_20,
+	ADW_MC_SDTR_40,
+	ADW_MC_SDTR_80
+} adw_mc_sdtr;
+
+struct adw_syncrate
+{
+	adw_mc_sdtr mc_sdtr;
+	u_int8_t    period;
+	char       *rate;
+};
+
+/* We have an input and output queue for our carrier structures */
+#define ADW_OUTPUT_QUEUE 0	/* Offset into carriers member */
+#define ADW_INPUT_QUEUE 1	/* Offset into carriers member */
+#define ADW_NUM_CARRIER_QUEUES 2
 struct adw_softc
 {
 	bus_space_tag_t		  tag;
@@ -436,16 +597,37 @@ struct adw_softc
 	adw_state		  state;
 	bus_dma_tag_t		  buffer_dmat;
 	struct acb	         *acbs;
+	struct adw_carrier	 *carriers;
+	struct adw_carrier	 *free_carriers;
+	struct adw_carrier	 *commandq;
+	struct adw_carrier	 *responseq;
 	LIST_HEAD(, ccb_hdr)	  pending_ccbs;
 	SLIST_HEAD(, acb)	  free_acb_list;
 	bus_dma_tag_t		  parent_dmat;
+	bus_dma_tag_t		  carrier_dmat;	/* dmat for our acb carriers*/
+	bus_dmamap_t		  carrier_dmamap;
 	bus_dma_tag_t		  acb_dmat;	/* dmat for our ccb array */
 	bus_dmamap_t		  acb_dmamap;
 	bus_dma_tag_t		  sg_dmat;	/* dmat for our sg maps */
 	SLIST_HEAD(, sg_map_node) sg_maps;
 	bus_addr_t		  acb_busbase;
+	bus_addr_t		  carrier_busbase;
+	adw_chip		  chip;
+	adw_feature		  features;
+	adw_flag		  flags;
+	u_int			  memsize;
+	char			  channel;
 	struct cam_path		 *path;
 	struct cam_sim		 *sim;
+	struct resource		 *regs;
+	struct resource		 *irq;
+	void			 *ih;
+	const struct adw_mcode	 *mcode_data;
+	const struct adw_eeprom	 *default_eeprom;
+	device_t		  device;
+	int			  regs_res_type;
+	int			  regs_res_id;
+	int			  irq_res_type;
 	u_int			  max_acbs;
 	u_int			  num_acbs;
 	u_int			  initiator_id;
@@ -453,20 +635,22 @@ struct adw_softc
 	u_int			  unit;
 	char*			  name;
 	cam_status		  last_reset;	/* Last reset type */
-	adw_bios_ctrl		  bios_ctrl;
+	u_int16_t		  bios_ctrl;
 	adw_idle_cmd_t		  idle_cmd;
 	u_int			  idle_cmd_param;
 	volatile int		  idle_command_cmp;
 	u_int16_t		  user_wdtr;
-	u_int16_t		  user_sdtr;
-	u_int16_t		  user_ultra;
+	u_int16_t		  user_sdtr[4];	/* A nibble per-device */
 	u_int16_t		  user_tagenb;
 	u_int16_t		  tagenb;
 	u_int16_t		  user_discenb;
 	u_int16_t		  serial_number[3];
 };
 
-extern struct adw_eeprom adw_default_eeprom;
+extern const struct adw_eeprom adw_asc3550_default_eeprom;
+extern const struct adw_eeprom adw_asc38C0800_default_eeprom;
+extern const struct adw_syncrate adw_syncrates[];
+extern const int adw_num_syncrates;
 
 #define adw_inb(adw, port)				\
 	bus_space_read_1((adw)->tag, (adw)->bsh, port)
@@ -482,6 +666,9 @@ extern struct adw_eeprom adw_default_eeprom;
 #define adw_outl(adw, port, value)			\
 	bus_space_write_4((adw)->tag, (adw)->bsh, port, value)
 
+#define adw_set_multi_2(adw, port, value, count)	\
+	bus_space_set_multi_2((adw)->tag, (adw)->bsh, port, value, count)
+
 static __inline const char*	adw_name(struct adw_softc *adw);
 static __inline u_int	adw_lram_read_8(struct adw_softc *adw, u_int addr);
 static __inline u_int	adw_lram_read_16(struct adw_softc *adw, u_int addr);
@@ -493,6 +680,25 @@ static __inline void	adw_lram_write_16(struct adw_softc *adw, u_int addr,
 static __inline void	adw_lram_write_32(struct adw_softc *adw, u_int addr,
 					  u_int value);
 
+static __inline u_int32_t	acbvtobo(struct adw_softc *adw,
+					   struct acb *acb);
+static __inline u_int32_t	acbvtob(struct adw_softc *adw,
+					   struct acb *acb);
+static __inline struct acb *	acbbotov(struct adw_softc *adw,
+					u_int32_t busaddr);
+static __inline struct acb *	acbbtov(struct adw_softc *adw,
+					u_int32_t busaddr);
+static __inline u_int32_t	carriervtobo(struct adw_softc *adw,
+					     struct adw_carrier *carrier);
+static __inline u_int32_t	carriervtob(struct adw_softc *adw,
+					    struct adw_carrier *carrier);
+static __inline struct adw_carrier *
+				carrierbotov(struct adw_softc *adw,
+					     u_int32_t byte_offset);
+static __inline struct adw_carrier *
+				carrierbtov(struct adw_softc *adw,
+					    u_int32_t baddr);
+
 static __inline const char*
 adw_name(struct adw_softc *adw)
 {
@@ -546,12 +752,71 @@ adw_lram_write_32(struct adw_softc *adw, u_int addr, u_int value)
 	adw_outw(adw, ADW_RAM_DATA, value >> 16);
 }
 
+static __inline u_int32_t
+acbvtobo(struct adw_softc *adw, struct acb *acb)
+{
+	return ((u_int32_t)((caddr_t)acb - (caddr_t)adw->acbs));
+}
+
+static __inline u_int32_t
+acbvtob(struct adw_softc *adw, struct acb *acb)
+{
+	return (adw->acb_busbase + acbvtobo(adw, acb));
+}
+
+static __inline struct acb *
+acbbotov(struct adw_softc *adw, u_int32_t byteoffset)
+{
+	return ((struct acb *)((caddr_t)adw->acbs + byteoffset));
+}
+
+static __inline struct acb *
+acbbtov(struct adw_softc *adw, u_int32_t busaddr)
+{
+	return (acbbotov(adw, busaddr - adw->acb_busbase));
+}
+
+/*
+ * Return the byte offset for a carrier relative to our array of carriers.
+ */
+static __inline u_int32_t
+carriervtobo(struct adw_softc *adw, struct adw_carrier *carrier)
+{
+	return ((u_int32_t)((caddr_t)carrier - (caddr_t)adw->carriers));
+}
+
+static __inline u_int32_t
+carriervtob(struct adw_softc *adw, struct adw_carrier *carrier)
+{
+	return (adw->carrier_busbase + carriervtobo(adw, carrier));
+}
+
+static __inline struct adw_carrier *
+carrierbotov(struct adw_softc *adw, u_int32_t byte_offset)
+{
+	return ((struct adw_carrier *)((caddr_t)adw->carriers + byte_offset));
+}
+
+static __inline struct adw_carrier *
+carrierbtov(struct adw_softc *adw, u_int32_t baddr)
+{
+	return (carrierbotov(adw, baddr - adw->carrier_busbase));
+}
+
 /* Intialization */
-int		adw_find_signature(bus_space_tag_t tag, bus_space_handle_t bsh);
+int		adw_find_signature(struct adw_softc *adw);
 void		adw_reset_chip(struct adw_softc *adw);
 u_int16_t	adw_eeprom_read(struct adw_softc *adw, struct adw_eeprom *buf);
 void		adw_eeprom_write(struct adw_softc *adw, struct adw_eeprom *buf);
 int		adw_init_chip(struct adw_softc *adw, u_int term_scsicfg1);
+void		adw_set_user_sdtr(struct adw_softc *adw,
+				  u_int tid, u_int mc_sdtr);
+u_int		adw_get_user_sdtr(struct adw_softc *adw, u_int tid);
+void		adw_set_chip_sdtr(struct adw_softc *adw, u_int tid, u_int sdtr);
+u_int		adw_get_chip_sdtr(struct adw_softc *adw, u_int tid);
+u_int		adw_find_sdtr(struct adw_softc *adw, u_int period);
+u_int		adw_find_period(struct adw_softc *adw, u_int mc_sdtr);
+u_int		adw_hshk_cfg_period_factor(u_int tinfo);
 
 /* Idle Commands */
 void			adw_idle_cmd_send(struct adw_softc *adw, u_int cmd,
@@ -562,44 +827,46 @@ adw_idle_cmd_status_t	adw_idle_cmd_wait(struct adw_softc *adw);
 static __inline void	adw_send_acb(struct adw_softc *adw, struct acb *acb,
 				     u_int32_t acb_baddr);
 
-static __inline void
-adw_send_acb(struct adw_softc *adw, struct acb *acb, u_int32_t acb_baddr)
+static __inline void	adw_tickle_risc(struct adw_softc *adw, u_int value)
 {
-	u_int next_queue;
-
-	/* Determine the next free queue. */
-	next_queue = adw_lram_read_8(adw, ADW_MC_HOST_NEXT_READY);
-	next_queue = ADW_MC_RISC_Q_LIST_BASE
-		   + (next_queue * ADW_MC_RISC_Q_LIST_SIZE);
-
-	/*
-	 * Write the physical address of the host Q to the free Q.
-	 */
-    	adw_lram_write_32(adw, next_queue + RQL_PHYADDR, acb_baddr);
-
-	adw_lram_write_8(adw, next_queue + RQL_TID, acb->queue.target_id);
-
 	/*
-	 * Set the ADW_MC_HOST_NEXT_READY (0x128) microcode variable to
-	 * the 'next_queue' request forward pointer.
-	 *
-	 * Do this *before* changing the 'next_queue' queue to QS_READY.
-	 * After the state is changed to QS_READY 'RQL_FWD' will be changed
-	 * by the microcode.
-	 *
+	 * Tickle the RISC to tell it to read its Command Queue Head pointer.
 	 */
-	adw_lram_write_8(adw, ADW_MC_HOST_NEXT_READY,
-			 adw_lram_read_8(adw, next_queue + RQL_FWD));
+	adw_outb(adw, ADW_TICKLE, value);
+	if (adw->chip == ADW_CHIP_ASC3550) {
+		/*
+		 * Clear the tickle value. In the ASC-3550 the RISC flag
+		 * command 'clr_tickle_a' does not work unless the host
+		 * value is cleared.
+		 */
+		adw_outb(adw, ADW_TICKLE, ADW_TICKLE_NOP);
+	}
+}
 
-	/*
-	 * Change the state of 'next_queue' request from QS_FREE to
-	 * QS_READY which will cause the microcode to pick it up and
-	 * execute it.
-	 *  
-	 * Can't reference 'next_queue' after changing the request
-	 * state to QS_READY. The microcode now owns the request.
-	 */
-	adw_lram_write_8(adw, next_queue + RQL_STATE, ADW_MC_QS_READY);
+static __inline void
+adw_send_acb(struct adw_softc *adw, struct acb *acb, u_int32_t acb_baddr)
+{
+	struct adw_carrier *new_cq;
+
+	new_cq = adw->free_carriers;
+	adw->free_carriers = carrierbotov(adw, new_cq->next_ba);
+	new_cq->next_ba = ADW_CQ_STOPPER;
+
+	acb->queue.carrier_baddr = adw->commandq->carr_ba;
+	acb->queue.carrier_bo = adw->commandq->carr_offset;
+	adw->commandq->areq_ba = acbvtob(adw, acb);
+	adw->commandq->next_ba = new_cq->carr_ba;
+#if 0
+	printf("EnQ 0x%x 0x%x 0x%x 0x%x\n",
+	       adw->commandq->carr_offset,
+	       adw->commandq->carr_ba,
+	       adw->commandq->areq_ba,
+	       adw->commandq->next_ba);
+#endif
+	adw->commandq = new_cq;
+
+	
+	adw_tickle_risc(adw, ADW_TICKLE_A);
 }
      
 #endif /* _ADWLIB_H_ */