Add preliminary support for the Lanner MR-955. It boots multi-user but there

seem to be problems both with the on-board Ethernet interfaces and the em(4)
interfaces on PCI under FreeBSD.

Thanks to Lanner for providing access to hardware.

5 files changed, 45 insertions, 0 deletions

diff --git a/sys/contrib/octeon-sdk/cvmx-app-init.h b/sys/contrib/octeon-sdk/cvmx-app-init.h
index 6becb91..8f768ed 100644
--- a/sys/contrib/octeon-sdk/cvmx-app-init.h
+++ b/sys/contrib/octeon-sdk/cvmx-app-init.h
@@ -182,7 +182,11 @@ enum cvmx_board_types_enum {
     CVMX_BOARD_TYPE_CUST_ITB101      = 10005,
     CVMX_BOARD_TYPE_CUST_NTE102      = 10006,
     CVMX_BOARD_TYPE_CUST_AGS103      = 10007,
+#if !defined(OCTEON_VENDOR_LANNER)
     CVMX_BOARD_TYPE_CUST_GST104      = 10008,
+#else
+    CVMX_BOARD_TYPE_CUST_LANNER_MR955= 10008,
+#endif
     CVMX_BOARD_TYPE_CUST_GCT105      = 10009,
     CVMX_BOARD_TYPE_CUST_AGS106      = 10010,
     CVMX_BOARD_TYPE_CUST_SGM107      = 10011,
@@ -257,7 +261,11 @@ static inline const char *cvmx_board_type_to_string(enum cvmx_board_types_enum t
         ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_ITB101)
         ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NTE102)
         ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS103)
+#if !defined(OCTEON_VENDOR_LANNER)
         ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GST104)
+#else
+	ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_LANNER_MR955)
+#endif
         ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT105)
         ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS106)
         ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_SGM107)
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-board.c b/sys/contrib/octeon-sdk/cvmx-helper-board.c
index b890185..5bf2990 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-board.c
+++ b/sys/contrib/octeon-sdk/cvmx-helper-board.c
@@ -114,6 +114,9 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
         case CVMX_BOARD_TYPE_EBT5800:
         case CVMX_BOARD_TYPE_THUNDER:
         case CVMX_BOARD_TYPE_NICPRO2:
+#if defined(OCTEON_VENDOR_LANNER)
+	case CVMX_BOARD_TYPE_CUST_LANNER_MR955:
+#endif
             /* Interface 0 is SPI4, interface 1 is RGMII */
             if ((ipd_port >= 16) && (ipd_port < 20))
                 return ipd_port - 16;
@@ -616,6 +619,12 @@ int __cvmx_helper_board_interface_probe(int interface, int supported_ports)
             if (interface == 1)
                 return 0;
 	    break;
+#if defined(OCTEON_VENDOR_LANNER)
+	case CVMX_BOARD_TYPE_CUST_LANNER_MR955:
+	    if (interface == 1)
+	        return 12;
+	    break;
+#endif
     }
 #ifdef CVMX_BUILD_FOR_UBOOT
     if (CVMX_HELPER_INTERFACE_MODE_SPI == cvmx_helper_interface_get_mode(interface) && getenv("disable_spi"))
diff --git a/sys/contrib/octeon-sdk/cvmx-helper-spi.c b/sys/contrib/octeon-sdk/cvmx-helper-spi.c
index 9ee1aab..bc05662 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper-spi.c
+++ b/sys/contrib/octeon-sdk/cvmx-helper-spi.c
@@ -82,6 +82,21 @@ int __cvmx_helper_spi_probe(int interface)
     {
         num_ports = 10;
     }
+#if defined(OCTEON_VENDOR_LANNER)
+    else if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CUST_LANNER_MR955)
+    {
+        cvmx_pko_reg_crc_enable_t enable;
+	if (interface == 1) {
+	    num_ports = 12;
+	} else {
+	    /* XXX This is not entirely true.  */
+	    num_ports = 0;
+	}
+        enable.u64 = cvmx_read_csr(CVMX_PKO_REG_CRC_ENABLE);
+        enable.s.enable &= 0xffff << (16 - (interface*16));
+        cvmx_write_csr(CVMX_PKO_REG_CRC_ENABLE, enable.u64);
+    }
+#endif
     else
     {
         cvmx_pko_reg_crc_enable_t enable;
diff --git a/sys/contrib/octeon-sdk/cvmx-helper.c b/sys/contrib/octeon-sdk/cvmx-helper.c
index cc52749..cd155bb 100644
--- a/sys/contrib/octeon-sdk/cvmx-helper.c
+++ b/sys/contrib/octeon-sdk/cvmx-helper.c
@@ -101,6 +101,15 @@ static CVMX_SHARED cvmx_helper_link_info_t port_link_info[CVMX_PIP_NUM_INPUT_POR
  */
 int cvmx_helper_get_number_of_interfaces(void)
 {
+    switch (cvmx_sysinfo_get()->board_type) {
+#if defined(OCTEON_VENDOR_LANNER)
+	case CVMX_BOARD_TYPE_CUST_LANNER_MR955:
+	    return 2;
+#endif
+	default:
+	    break;
+    }
+
     if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
         return 4;
     else
diff --git a/sys/contrib/octeon-sdk/cvmx-spi.c b/sys/contrib/octeon-sdk/cvmx-spi.c
index 012d03b..cbb48a5 100644
--- a/sys/contrib/octeon-sdk/cvmx-spi.c
+++ b/sys/contrib/octeon-sdk/cvmx-spi.c
@@ -515,7 +515,11 @@ int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, int timeout)
     // Wait for the training sequence to complete
     cvmx_dprintf ("SPI%d: Waiting for training\n", interface);
     cvmx_wait (1000 * MS);
+#if !defined(OCTEON_VENDOR_LANNER)
     timeout_time = cvmx_get_cycle() + 1000ull * MS * 600;  /* Wait a really long time here */
+#else
+    timeout_time = cvmx_get_cycle() + 1000ull * MS * 10;
+#endif
     /* The HRM says we must wait for 34 + 16 * MAXDIST training sequences.
         We'll be pessimistic and wait for a lot more */
     rx_training_needed = 500;