MFC r264601,264646,265766,267918,267919,267920:

 Merge if_nf10bmac(4), a driver to support an NetFPGA-10G Embedded
 CPU Ethernet Core.

 The current version operates on a simple PIO based interface connected
 to a NetFPGA-10G port.

 To avoid confusion: this driver operates on a CPU running on the FPGA,
 e.g. BERI/mips, and is not suited for the PCI host interface.

 Adjust the register layout to allow for 64bit registers in the
 future for nf10bmac(4).  Also, add support for and enable RX interrupts.

 Allow switching between 32bit and 64bit bus width data access at compile
 time by setting NF10BMAC_64BIT and using a REGWTYPE #define to set correct
 variable and return value widths.

 Adjust comments to indicate the 32 or 64bit register widths.

Relnotes:	yes
Sponsored by:	DARPA/AFRL

1 files changed, 13 insertions, 1 deletions

diff --git a/sys/boot/fdt/dts/mips/beri-netfpga.dts b/sys/boot/fdt/dts/mips/beri-netfpga.dts
index 509d387..9064257 100644
--- a/sys/boot/fdt/dts/mips/beri-netfpga.dts
+++ b/sys/boot/fdt/dts/mips/beri-netfpga.dts
@@ -1,7 +1,7 @@
 /*-
  * Copyright (c) 2012-2013 Robert N. M. Watson
  * Copyright (c) 2013 SRI International
- * Copyright (c) 2013 Bjoern A. Zeeb
+ * Copyright (c) 2013-2014 Bjoern A. Zeeb
  * All rights reserved.
  *
  * This software was developed by SRI International and the University of
@@ -130,6 +130,18 @@
 			interrupt-parent = <&beripic>;
 		};
 */
+
+		ethernet@7f005000 {
+			compatible = "netfpag10g,nf10bmac";
+			// LOOP, TX, RX, INTR
+			reg = <0x7f005000 0x20
+			       0x7f005020 0x30
+			       0x7f005050 0x30
+			       0x7f005100 0x10>;
+			// RX
+			interrupts = <1>;
+			interrupt-parent = <&beripic>;
+		};
 	};
 
 	aliases {