MFC r256912, r256931, r256977

Sync BERI kernel configs with P4:

Switch the majority of device configuration to FDT from hints.

Add BERI_*_BASE configs to reduce duplication in the MDROOT and SDROOT
kernels.

Add NFS and GSSAPI support by default.

Enable ATSE_CFI_HACK in BERI configs, stable MAC addresses are useful.

BERI_SIM.hint is no longer used, remove it.

Sponsored by:	DARPA/AFRL
Approved by:	re (delphij)

2 files changed, 410 insertions, 0 deletions

diff --git a/sys/boot/fdt/dts/beri-sim.dts b/sys/boot/fdt/dts/beri-sim.dts
new file mode 100644
index 0000000..4148bb9
--- /dev/null
+++ b/sys/boot/fdt/dts/beri-sim.dts
@@ -0,0 +1,144 @@
+/*-
+ * Copyright (c) 2012-2013 Robert N. M. Watson
+ * Copyright (c) 2013 SRI International
+ * All rights reserved.
+ *
+ * This software was developed by SRI International and the University of
+ * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
+ * ("CTSRD"), as part of the DARPA CRASH research programme.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/dts-v1/;
+
+/*
+ * Device names here have been largely made up on the spot, especially for the
+ * "compatible" strings, and might want to be revised.
+ *
+ * For now, use 32-bit addressing as our Avalon bus is 32-bit.  However, in
+ * the future, we should likely change to 64-bit.
+ */
+
+/ {
+	model = "SRI/Cambridge BERI simulation";
+	compatible = "sri-cambridge,beri-sim";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/*
+		 * Secondary CPUs all start disabled and use the
+		 * spin-table enable method.  cpu-release-addr must be
+		 * specified for each cpu other than cpu@0.  Values of
+		 * cpu-release-addr grow down from 0x100000 (kernel).
+		 */
+		status = "disabled";
+		enable-method = "spin-table";
+
+		cpu@0 {
+			device-type = "cpu";
+			compatible = "sri-cambridge,beri";
+
+			reg = <0>;
+			status = "okay";
+		};
+
+/*
+		cpu@1 {
+			device-type = "cpu";
+			compatible = "sri-cambridge,beri";
+
+			reg = <1>;
+			// XXX: should we need cached prefix?
+			cpu-release-addr = <0xffffffff 0x800fffe0>;
+		};
+*/
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		#interrupt-cells = <1>;
+
+		/*
+		 * Declare mips,mips4k since BERI doesn't (yet) have a PIC, so
+		 * we use mips4k coprocessor 0 interrupt management directly.
+		 */
+		compatible = "simple-bus", "mips,mips4k";
+		ranges = <>;
+
+		memory {
+			device_type = "memory";
+			reg = <0x0 0x4000000>;		// 64M at 0x0
+		};
+
+		beripic: beripic@7f804000 {
+			compatible = "sri-cambridge,beri-pic";
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			reg = <0x7f804000 0x400
+			       0x7f806000 0x10
+			       0x7f806080 0x10
+			       0x7f806100 0x10>;
+			interrupts = <0 1 2 3 4>;
+			hard-interrupt-sources = <64>;
+			soft-interrupt-sources = <64>;
+		};
+
+		serial@7f000000 {
+			compatible = "altera,jtag_uart-11_0";
+			reg = <0x7f000000 0x40>;
+			interrupts = <0>;
+			interrupt-parent = <&beripic>;
+		};
+
+		serial@7f001000 {
+			compatible = "altera,jtag_uart-11_0";
+			reg = <0x7f001000 0x40>;
+		};
+
+		serial@7f002000 {
+			compatible = "altera,jtag_uart-11_0";
+			reg = <0x7f002000 0x40>;
+		};
+
+		sdcard@7f008000 {
+			compatible = "altera,sdcard_11_2011";
+			reg = <0x7f008000 0x400>;
+		};
+
+		avgen@0x7f00a000 {
+			compatible = "sri-cambridge,avgen";
+			reg = <0x7f00a000 0x14>;
+			sri-cambridge,width = <4>;
+			sri-cambridge,fileio = "rw";
+			sri-cambridge,devname = "berirom";
+		};
+	};
+};
diff --git a/sys/boot/fdt/dts/beripad-de4.dts b/sys/boot/fdt/dts/beripad-de4.dts
new file mode 100644
index 0000000..4d4126c
--- /dev/null
+++ b/sys/boot/fdt/dts/beripad-de4.dts
@@ -0,0 +1,266 @@
+/*-
+ * Copyright (c) 2012-2013 Robert N. M. Watson
+ * Copyright (c) 2013 SRI International
+ * All rights reserved.
+ *
+ * This software was developed by SRI International and the University of
+ * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
+ * ("CTSRD"), as part of the DARPA CRASH research programme.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/dts-v1/;
+
+/*
+ * Device names here have been largely made up on the spot, especially for the
+ * "compatible" strings, and might want to be revised.
+ *
+ * For now, use 32-bit addressing as our Avalon bus is 32-bit.  However, in
+ * the future, we should likely change to 64-bit.
+ */
+
+/ {
+	model = "SRI/Cambridge BeriPad (DE4)";
+	compatible = "sri-cambridge,beripad-de4";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/*
+		 * Secondary CPUs all start disabled and use the
+		 * spin-table enable method.  cpu-release-addr must be
+		 * specified for each cpu other than cpu@0.  Values of
+		 * cpu-release-addr grow down from 0x100000 (kernel).
+		 */
+		status = "disabled";
+		enable-method = "spin-table";
+
+		cpu@0 {
+			device-type = "cpu";
+			compatible = "sri-cambridge,beri";
+
+			reg = <0>;
+			status = "okay";
+		};
+
+/*
+		cpu@1 {
+			device-type = "cpu";
+			compatible = "sri-cambridge,beri";
+
+			reg = <1>;
+			// XXX: should we need cached prefix?
+			cpu-release-addr = <0xffffffff 0x800fffe0>;
+		};
+*/
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		#interrupt-cells = <1>;
+
+		/*
+		 * Declare mips,mips4k since BERI doesn't (yet) have a PIC, so
+		 * we use mips4k coprocessor 0 interrupt management directly.
+		 */
+		compatible = "simple-bus", "mips,mips4k";
+		ranges = <>;
+
+		memory {
+			device_type = "memory";
+			reg = <0x0 0x40000000>;		// 1G at 0x0
+		};
+
+		beripic: beripic@7f804000 {
+			compatible = "sri-cambridge,beri-pic";
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			reg = <0x7f804000 0x400
+			       0x7f806000 0x10
+			       0x7f806080 0x10
+			       0x7f806100 0x10>;
+			interrupts = <0 1 2 3 4>;
+			hard-interrupt-sources = <64>;
+			soft-interrupt-sources = <64>;
+		};
+
+		serial@7f002100 {
+			compatible = "ns16550";
+			reg = <0x7f002100 0x20>;
+			reg-shift = <2>;
+			clock-frequency = <50000000>;
+			interrupts = <6>;
+			interrupt-parent = <&beripic>;
+		};
+
+		serial@7f000000 {
+			compatible = "altera,jtag_uart-11_0";
+			reg = <0x7f000000 0x40>;
+			interrupts = <0>;
+			interrupt-parent = <&beripic>;
+		};
+
+		serial@7f001000 {
+			compatible = "altera,jtag_uart-11_0";
+			reg = <0x7f001000 0x40>;
+		};
+
+		serial@7f002000 {
+			compatible = "altera,jtag_uart-11_0";
+			reg = <0x7f002000 0x40>;
+		};
+
+		sdcard@7f008000 {
+			compatible = "altera,sdcard_11_2011";
+			reg = <0x7f008000 0x400>;
+		};
+
+		led@7f006000 {
+			compatible = "sri-cambridge,de4led";
+			reg = <0x7f006000 0x1>;
+		};
+
+		/*
+		 * XXX-BZ keep flash before ethernet so that atse can read the
+		 * Ethernet addresses for now.
+		 */
+		flash@74000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "cfi-flash";
+			reg = <0x74000000 0x4000000>;
+
+			/* Board configuration */
+			partition@0 {
+				reg = <0x0 0x20000>;
+				label = "config";
+			};
+
+			/* Power up FPGA image */
+			partition@20000 {
+				reg = <0x20000 0xc00000>;
+				label = "fpga0";
+			};
+
+			/* Secondary FPGA image (on RE_CONFIGn button) */
+			partition@C20000 {
+				reg = <0xc20000 0xc00000>;
+				label = "fpga1";
+			};
+
+			/* Space for operating system use */
+			partition@1820000 {
+				reg = <0x1820000 0x027c0000>;
+				label = "os";
+			};
+
+			/* Second stage bootloader */
+			parition@3fe0000 {
+				reg = <0x3fe0000 0x20000>;
+				label = "boot";
+			};
+		};
+
+		ethernet@7f007000 {
+			compatible = "altera,atse";
+			// MAC, RX+RXC, TX+TXC.
+			reg = <0x7f007000 0x400
+			       0x7f007500 0x8
+			       0x7f007520 0x20
+			       0x7f007400 0x8
+			       0x7f007420 0x20>;
+			// RX, TX
+			interrupts = <1 2>;
+			interrupt-parent = <&beripic>;
+		};
+
+		ethernet@7f005000 {
+			compatible = "altera,atse";
+			// MAC, RX+RXC, TX+TXC.
+			reg = <0x7f005000 0x400
+			       0x7f005500 0x8
+			       0x7f005520 0x20
+			       0x7f005400 0x8
+			       0x7f005420 0x20>;
+			// RX, TX
+			interrupts = <11 12>;
+			interrupt-parent = <&beripic>;
+		};
+
+		touchscreen@70400000 {
+			compatible = "sri-cambridge,mtl";
+			reg = <0x70400000 0x1000
+			       0x70000000 0x177000
+			       0x70177000 0x2000>;
+		};
+
+		usb@0x7f100000 {
+			compatible = "philips,isp1761";
+			reg = <0x7f100000 0x40000
+			       0x7f140000 0x4>;
+			// IRQ 4 is DC, IRQ 5 is HC.
+			interrupts = <4 5>;
+			interrupt-parent = <&beripic>;
+		};
+
+		avgen@0x7f009000 {
+			compatible = "sri-cambridge,avgen";
+			reg = <0x7f009000 0x2>;	
+			sri-cambridge,width = <1>;
+			sri-cambridge,fileio = "r";
+			sri-cambridge,devname = "de4bsw";
+		};
+
+		avgen@0x7f00a000 {
+			compatible = "sri-cambridge,avgen";
+			reg = <0x7f00a000 0x14>;
+			sri-cambridge,width = <4>;
+			sri-cambridge,fileio = "rw";
+			sri-cambridge,devname = "berirom";
+		};
+
+		avgen@0x7f00c000 {
+			compatible = "sri-cambridge,avgen";
+			reg = <0x7f00c000 0x8>;
+			sri-cambridge,width = <4>;
+			sri-cambridge,fileio = "rw";
+			sri-cambridge,devname = "de4tempfan";
+		};
+
+		avgen@0x7f100000 {
+			compatible = "sri-cambridge,avgen";
+			reg = <0x7f100000 0x40000>;
+			sri-cambridge,width = <4>;
+			sri-cambridge,fileio = "r";
+			sri-cambridge,devname = "usbmem";
+		};
+
+	};
+};