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| author | ian <ian@FreeBSD.org> | 2015-05-04 14:55:21 +0000 |
|---|---|---|
| committer | ian <ian@FreeBSD.org> | 2015-05-04 14:55:21 +0000 |
| commit | 010365f81b173d359451721e5573b5d34555adef (patch) | |
| tree | cde1842e40315adf01bd9eabef41b44fc0ac060a /sys/arm | |
| parent | c8296a2c9540040222df62d9490fdbba987474b2 (diff) | |
| download | FreeBSD-src-010365f81b173d359451721e5573b5d34555adef.zip FreeBSD-src-010365f81b173d359451721e5573b5d34555adef.tar.gz | |
On an icache sync by address/len, round the length up if the operation spans
a cacheline boundary.
PR: 199740
Submitted by: Juergen Weiss <weiss@uni-mainz.de>
Diffstat (limited to 'sys/arm')
| -rw-r--r-- | sys/arm/arm/cpufunc_asm_armv7.S | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/sys/arm/arm/cpufunc_asm_armv7.S b/sys/arm/arm/cpufunc_asm_armv7.S index 25f052f..7016d7e 100644 --- a/sys/arm/arm/cpufunc_asm_armv7.S +++ b/sys/arm/arm/cpufunc_asm_armv7.S @@ -266,6 +266,9 @@ END(armv7_icache_sync_all) ENTRY_NP(armv7_icache_sync_range) ldr ip, .Larmv7_icache_line_size ldr ip, [ip] + sub r3, ip, #1 /* Address need not be aligned, but */ + and r2, r0, r3 /* round length up if op spans line */ + add r1, r1, r2 /* boundary: len += addr & linemask; */ .Larmv7_sync_next: mcr CP15_DCCMVAC(r0) mcr CP15_ICIMVAU(r0) |
