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author | ian <ian@FreeBSD.org> | 2014-05-14 17:40:18 +0000 |
---|---|---|
committer | ian <ian@FreeBSD.org> | 2014-05-14 17:40:18 +0000 |
commit | 3c9602820517b21689d8a6153fd6f7ea38c7a749 (patch) | |
tree | 5a1c9e79488178b15f78d541f8a651be6ee21573 /sys/arm | |
parent | 4ee6f0bd3bade07595ecc84f07aa45d765a3eae1 (diff) | |
download | FreeBSD-src-3c9602820517b21689d8a6153fd6f7ea38c7a749.zip FreeBSD-src-3c9602820517b21689d8a6153fd6f7ea38c7a749.tar.gz |
MFC r258359, r258742, r258845, r259936, r259640
Apply access flags for managed and unmanaged pages properly on ARMv6/v7
Set the PGA_WRITEABLE flag when the protections indicate write access, not
just when the current access is a write.
Enable missing Access Flag for secondary cores on ARMv6/v7
Add identification and necessary type checks for Krait CPU cores.
Diffstat (limited to 'sys/arm')
-rw-r--r-- | sys/arm/arm/cpufunc.c | 11 | ||||
-rw-r--r-- | sys/arm/arm/elf_trampoline.c | 2 | ||||
-rw-r--r-- | sys/arm/arm/identcpu.c | 3 | ||||
-rw-r--r-- | sys/arm/arm/locore.S | 7 | ||||
-rw-r--r-- | sys/arm/arm/pmap-v6.c | 36 | ||||
-rw-r--r-- | sys/arm/arm/swtch.S | 4 | ||||
-rw-r--r-- | sys/arm/include/armreg.h | 1 | ||||
-rw-r--r-- | sys/arm/include/cpuconf.h | 5 | ||||
-rw-r--r-- | sys/arm/include/cpufunc.h | 4 | ||||
-rw-r--r-- | sys/arm/include/intr.h | 2 | ||||
-rw-r--r-- | sys/arm/include/md_var.h | 1 |
11 files changed, 44 insertions, 32 deletions
diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c index d69f2f1..923745f 100644 --- a/sys/arm/arm/cpufunc.c +++ b/sys/arm/arm/cpufunc.c @@ -1038,7 +1038,7 @@ struct cpu_functions arm1176_cpufuncs = { }; #endif /*CPU_ARM1176 */ -#if defined(CPU_CORTEXA) +#if defined(CPU_CORTEXA) || defined(CPU_KRAIT) struct cpu_functions cortexa_cpufuncs = { /* CPU functions */ @@ -1118,7 +1118,7 @@ u_int cpu_reset_needs_v4_MMU_disable; /* flag used in locore.s */ defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ defined(CPU_FA526) || defined(CPU_FA626TE) || defined(CPU_MV_PJ4B) || \ defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \ - defined(CPU_CORTEXA) + defined(CPU_CORTEXA) || defined(CPU_KRAIT) static void get_cachetype_cp15(void); @@ -1416,7 +1416,7 @@ set_cpufuncs() goto out; } #endif /* CPU_ARM1136 || CPU_ARM1176 */ -#ifdef CPU_CORTEXA +#if defined(CPU_CORTEXA) || defined(CPU_KRAIT) if (cputype == CPU_ID_CORTEXA7 || cputype == CPU_ID_CORTEXA8R1 || cputype == CPU_ID_CORTEXA8R2 || @@ -1424,7 +1424,8 @@ set_cpufuncs() cputype == CPU_ID_CORTEXA9R1 || cputype == CPU_ID_CORTEXA9R2 || cputype == CPU_ID_CORTEXA9R3 || - cputype == CPU_ID_CORTEXA15 ) { + cputype == CPU_ID_CORTEXA15 || + cputype == CPU_ID_KRAIT ) { cpufuncs = cortexa_cpufuncs; cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */ get_cachetype_cp15(); @@ -2406,7 +2407,7 @@ pj4bv7_setup(args) } #endif /* CPU_MV_PJ4B */ -#ifdef CPU_CORTEXA +#if defined(CPU_CORTEXA) || defined(CPU_KRAIT) void cortexa_setup(char *args) diff --git a/sys/arm/arm/elf_trampoline.c b/sys/arm/arm/elf_trampoline.c index 87be924..c27880e 100644 --- a/sys/arm/arm/elf_trampoline.c +++ b/sys/arm/arm/elf_trampoline.c @@ -102,7 +102,7 @@ extern void xscalec3_l2cache_purge(void); #elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) #define cpu_l2cache_wbinv_all sheeva_l2cache_wbinv_all extern void sheeva_l2cache_wbinv_all(void); -#elif defined(CPU_CORTEXA) +#elif defined(CPU_CORTEXA) || defined(CPU_KRAIT) #define cpu_idcache_wbinv_all armv7_idcache_wbinv_all #define cpu_l2cache_wbinv_all() #else diff --git a/sys/arm/arm/identcpu.c b/sys/arm/arm/identcpu.c index f3870dd..f7ecff9 100644 --- a/sys/arm/arm/identcpu.c +++ b/sys/arm/arm/identcpu.c @@ -252,6 +252,8 @@ const struct cpuidtab cpuids[] = { generic_steppings }, { CPU_ID_CORTEXA15, CPU_CLASS_CORTEXA, "Cortex A15", generic_steppings }, + { CPU_ID_KRAIT, CPU_CLASS_KRAIT, "Krait", + generic_steppings }, { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", sa110_steppings }, @@ -351,6 +353,7 @@ const struct cpu_classtab cpu_classes[] = { { "ARM10E", "CPU_ARM10" }, /* CPU_CLASS_ARM10E */ { "ARM10EJ", "CPU_ARM10" }, /* CPU_CLASS_ARM10EJ */ { "Cortex-A", "CPU_CORTEXA" }, /* CPU_CLASS_CORTEXA */ + { "Krait", "CPU_KRAIT" }, /* CPU_CLASS_KRAIT */ { "SA-1", "CPU_SA110" }, /* CPU_CLASS_SA1 */ { "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */ { "ARM11J", "CPU_ARM11" }, /* CPU_CLASS_ARM11J */ diff --git a/sys/arm/arm/locore.S b/sys/arm/arm/locore.S index 678f3bf..d52cacd 100644 --- a/sys/arm/arm/locore.S +++ b/sys/arm/arm/locore.S @@ -170,7 +170,7 @@ Lunmapped: mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ -#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) +#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT) mov r0, #0 mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */ #endif @@ -377,7 +377,7 @@ Ltag: mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ -#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) +#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT) mov r0, #0 mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */ #endif @@ -389,8 +389,9 @@ Ltag: mcr p15, 0, r0, c3, c0, 0 /* Enable MMU */ mrc p15, 0, r0, c1, c0, 0 -#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) +#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT) orr r0, r0, #CPU_CONTROL_V6_EXTPAGE + orr r0, r0, #CPU_CONTROL_AF_ENABLE #endif orr r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE) mcr p15, 0, r0, c1, c0, 0 diff --git a/sys/arm/arm/pmap-v6.c b/sys/arm/arm/pmap-v6.c index 26fbfaf..2b43e15 100644 --- a/sys/arm/arm/pmap-v6.c +++ b/sys/arm/arm/pmap-v6.c @@ -3079,31 +3079,33 @@ validate: * then continue setting mapping parameters */ if (m != NULL) { - if (prot & (VM_PROT_ALL)) { - if ((m->oflags & VPO_UNMANAGED) == 0) + if ((m->oflags & VPO_UNMANAGED) == 0) { + if (prot & (VM_PROT_ALL)) { vm_page_aflag_set(m, PGA_REFERENCED); - } else { - /* - * Need to do page referenced emulation. - */ - npte &= ~L2_S_REF; + } else { + /* + * Need to do page referenced emulation. + */ + npte &= ~L2_S_REF; + } } if (prot & VM_PROT_WRITE) { - /* Write enable */ - npte &= ~(L2_APX); - if ((m->oflags & VPO_UNMANAGED) == 0) { vm_page_aflag_set(m, PGA_WRITEABLE); /* - * The access type and permissions indicate - * that the page will be written as soon as - * returned from fault service. - * Mark it dirty from the outset. + * XXX: Skip modified bit emulation for now. + * The emulation reveals problems + * that result in random failures + * during memory allocation on some + * platforms. + * Therefore, the page is marked RW + * immediately. */ - if ((access & VM_PROT_WRITE) != 0) - vm_page_dirty(m); - } + npte &= ~(L2_APX); + vm_page_dirty(m); + } else + npte &= ~(L2_APX); } if (!(prot & VM_PROT_EXECUTE)) npte |= L2_XN; diff --git a/sys/arm/arm/swtch.S b/sys/arm/arm/swtch.S index 95a37cf..bff20fb 100644 --- a/sys/arm/arm/swtch.S +++ b/sys/arm/arm/swtch.S @@ -131,7 +131,7 @@ ENTRY(cpu_throw) /* Switch to lwp0 context */ ldr r9, .Lcpufuncs -#if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B) +#if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B) && !defined(CPU_KRAIT) mov lr, pc ldr pc, [r9, #CF_IDCACHE_WBINV_ALL] #endif @@ -361,7 +361,7 @@ ENTRY(cpu_switch) cmpeq r0, r5 /* Same DACR? */ beq .Lcs_context_switched /* yes! */ -#if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B) +#if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B) && !defined(CPU_KRAIT) /* * Definately need to flush the cache. */ diff --git a/sys/arm/include/armreg.h b/sys/arm/include/armreg.h index 35d2e9f..9397678 100644 --- a/sys/arm/include/armreg.h +++ b/sys/arm/include/armreg.h @@ -157,6 +157,7 @@ #define CPU_ID_CORTEXA15 0x410fc0f0 #define CPU_ID_SA110 0x4401a100 #define CPU_ID_SA1100 0x4401a110 +#define CPU_ID_KRAIT 0x510f06f0 /* Snapdragon S4 Pro/APQ8064 */ #define CPU_ID_TI925T 0x54029250 #define CPU_ID_MV88FR131 0x56251310 /* Marvell Feroceon 88FR131 Core */ #define CPU_ID_MV88FR331 0x56153310 /* Marvell Feroceon 88FR331 Core */ diff --git a/sys/arm/include/cpuconf.h b/sys/arm/include/cpuconf.h index 986633b..0c2faa3 100644 --- a/sys/arm/include/cpuconf.h +++ b/sys/arm/include/cpuconf.h @@ -66,6 +66,7 @@ defined(CPU_FA626TE) + \ defined(CPU_XSCALE_IXP425)) + \ defined(CPU_CORTEXA) + \ + defined(CPU_KRAIT) + \ defined(CPU_MV_PJ4B) /* @@ -97,7 +98,7 @@ #endif #endif -#if defined(CPU_CORTEXA) +#if defined(CPU_CORTEXA) || defined(CPU_KRAIT) #define ARM_ARCH_7A 1 #else #define ARM_ARCH_7A 0 @@ -156,7 +157,7 @@ #define ARM_MMU_V6 0 #endif -#if defined(CPU_CORTEXA) +#if defined(CPU_CORTEXA) || defined(CPU_KRAIT) #define ARM_MMU_V7 1 #else #define ARM_MMU_V7 0 diff --git a/sys/arm/include/cpufunc.h b/sys/arm/include/cpufunc.h index d3e9ebe..0b53906 100644 --- a/sys/arm/include/cpufunc.h +++ b/sys/arm/include/cpufunc.h @@ -188,7 +188,7 @@ extern u_int cputype; #else void tlb_broadcast(int); -#if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) +#if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT) #define TLB_BROADCAST /* No need to explicitely send an IPI */ #else #define TLB_BROADCAST tlb_broadcast(7) @@ -463,7 +463,7 @@ void sheeva_l2cache_wbinv_all (void); #endif #if defined(CPU_ARM1136) || defined(CPU_ARM1176) || \ - defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) + defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT) void arm11_setttb (u_int); void arm11_sleep (int); diff --git a/sys/arm/include/intr.h b/sys/arm/include/intr.h index 93a204c..a3bc837 100644 --- a/sys/arm/include/intr.h +++ b/sys/arm/include/intr.h @@ -52,6 +52,8 @@ #define NIRQ 64 #elif defined(CPU_CORTEXA) #define NIRQ 160 +#elif defined(CPU_KRAIT) +#define NIRQ 288 #elif defined(CPU_ARM1136) || defined(CPU_ARM1176) #define NIRQ 128 #elif defined(SOC_MV_ARMADAXP) diff --git a/sys/arm/include/md_var.h b/sys/arm/include/md_var.h index efb973d..ef202f5 100644 --- a/sys/arm/include/md_var.h +++ b/sys/arm/include/md_var.h @@ -63,6 +63,7 @@ enum cpu_class { CPU_CLASS_ARM10E, CPU_CLASS_ARM10EJ, CPU_CLASS_CORTEXA, + CPU_CLASS_KRAIT, CPU_CLASS_SA1, CPU_CLASS_XSCALE, CPU_CLASS_ARM11J, |