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| author | ian <ian@FreeBSD.org> | 2015-05-24 18:23:57 +0000 |
|---|---|---|
| committer | ian <ian@FreeBSD.org> | 2015-05-24 18:23:57 +0000 |
| commit | 83a17cbb7769e0ba41c229f622376f58e37187f4 (patch) | |
| tree | 1fdd8b2236049e8ee2a146a21bdfcee98ee04749 /sys/arm | |
| parent | 6bbf63ab358eb20bca48b212cd16b935c1571d74 (diff) | |
| download | FreeBSD-src-83a17cbb7769e0ba41c229f622376f58e37187f4.zip FreeBSD-src-83a17cbb7769e0ba41c229f622376f58e37187f4.tar.gz | |
MFC r282418:
On an icache sync by address/len, round the length up if the operation
spans a cacheline boundary.
Diffstat (limited to 'sys/arm')
| -rw-r--r-- | sys/arm/arm/cpufunc_asm_armv7.S | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/sys/arm/arm/cpufunc_asm_armv7.S b/sys/arm/arm/cpufunc_asm_armv7.S index 25f052f..7016d7e 100644 --- a/sys/arm/arm/cpufunc_asm_armv7.S +++ b/sys/arm/arm/cpufunc_asm_armv7.S @@ -266,6 +266,9 @@ END(armv7_icache_sync_all) ENTRY_NP(armv7_icache_sync_range) ldr ip, .Larmv7_icache_line_size ldr ip, [ip] + sub r3, ip, #1 /* Address need not be aligned, but */ + and r2, r0, r3 /* round length up if op spans line */ + add r1, r1, r2 /* boundary: len += addr & linemask; */ .Larmv7_sync_next: mcr CP15_DCCMVAC(r0) mcr CP15_ICIMVAU(r0) |
