MFC r268838, r277644:

  Add support for Toradex Apalis i.MX6 development board.

  Add support for imx6 audio transmitting, include drivers for:
  o Digital Audio Multiplexer (AUDMUX)
  o Smart Direct Memory Access Controller (SDMA)
  o Synchronous Serial Interface (SSI)

12 files changed, 1927 insertions, 1 deletions

diff --git a/sys/arm/conf/APALIS-IMX6 b/sys/arm/conf/APALIS-IMX6
new file mode 100644
index 0000000..ce8a0d5
--- /dev/null
+++ b/sys/arm/conf/APALIS-IMX6
@@ -0,0 +1,31 @@
+# Kernel configuration for Toradex Apalis i.MX6
+#
+# For more information on this file, please read the config(5) manual page,
+# and/or the handbook section on Kernel Configuration Files:
+#
+#    http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
+#
+# The handbook is also available locally in /usr/share/doc/handbook
+# if you've installed the doc distribution, otherwise always see the
+# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
+# latest information.
+#
+# An exhaustive list of options and more detailed explanations of the
+# device lines is also present in the ../../conf/NOTES and NOTES files.
+# If you are in doubt as to the purpose or necessity of a line, check first
+# in NOTES.
+#
+# $FreeBSD$
+
+#NO_UNIVERSE
+
+include 	"IMX6"
+ident		APALIS-IMX6
+
+makeoptions	MODULES_OVERRIDE=""
+makeoptions	WITHOUT_MODULES="ahc"
+
+# Flattened Device Tree
+options 	FDT
+options 	FDT_DTB_STATIC
+makeoptions	FDT_DTS_FILE=apalis-imx6.dts
diff --git a/sys/arm/freescale/imx/files.imx6 b/sys/arm/freescale/imx/files.imx6
index df86ef9..de1fc41 100644
--- a/sys/arm/freescale/imx/files.imx6
+++ b/sys/arm/freescale/imx/files.imx6
@@ -28,6 +28,9 @@ arm/freescale/imx/imx_machdep.c		standard
 arm/freescale/imx/imx_gpt.c		standard
 arm/freescale/imx/imx_gpio.c		optional gpio
 arm/freescale/imx/imx_i2c.c		optional fsliic
+arm/freescale/imx/imx6_sdma.c		optional sdma
+arm/freescale/imx/imx6_audmux.c		optional sound
+arm/freescale/imx/imx6_ssi.c		optional sound
 
 #
 # Optional devices.
@@ -52,3 +55,19 @@ arm/freescale/imx/imx6_usbphy.c		optional ehci
 # Not ready yet...
 #
 #arm/freescale/imx/imx51_ipuv3.c  	optional sc
+
+# SDMA firmware
+sdma_fw.c				optional sdma_fw		\
+	compile-with	"${AWK} -f $S/tools/fw_stub.awk sdma-imx6q-to1.bin:sdma_fw -msdma -c${.TARGET}" \
+	no-implicit-rule before-depend local				\
+	clean		"sdma_fw.c"
+sdma-imx6q-to1.fwo			optional sdma_fw		\
+	dependency	"sdma-imx6q-to1.bin"				\
+	compile-with	"${LD} -b binary -d -warn-common -r -d -o ${.TARGET} sdma-imx6q-to1.bin" \
+	no-implicit-rule						\
+	clean		"sdma-imx6q-to1.fwo"
+sdma-imx6q-to1.bin			optional sdma_fw		\
+	dependency	"$S/contrib/dev/imx/sdma-imx6q-to1.bin.uu"	\
+	compile-with	"uudecode < $S/contrib/dev/imx/sdma-imx6q-to1.bin.uu" \
+	no-obj no-implicit-rule						\
+	clean		"sdma-imx6q-to1.bin"
diff --git a/sys/arm/freescale/imx/imx6_anatop.c b/sys/arm/freescale/imx/imx6_anatop.c
index a66e924..fcc6729 100644
--- a/sys/arm/freescale/imx/imx6_anatop.c
+++ b/sys/arm/freescale/imx/imx6_anatop.c
@@ -713,6 +713,27 @@ out:
 	return (err);
 }
 
+uint32_t
+pll4_configure_output(uint32_t mfi, uint32_t mfn, uint32_t mfd)
+{
+	int reg;
+
+	/*
+	 * Audio PLL (PLL4).
+	 * PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM)
+	 */
+
+	reg = (IMX6_ANALOG_CCM_PLL_AUDIO_ENABLE);
+	reg &= ~(IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_MASK << \
+		IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT);
+	reg |= (mfi << IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT);
+	imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO, reg);
+	imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO_NUM, mfn);
+	imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO_DENOM, mfd);
+
+	return (0);
+}
+
 static int
 imx6_anatop_probe(device_t dev)
 {
diff --git a/sys/arm/freescale/imx/imx6_anatopreg.h b/sys/arm/freescale/imx/imx6_anatopreg.h
index bb75735..a155249 100644
--- a/sys/arm/freescale/imx/imx6_anatopreg.h
+++ b/sys/arm/freescale/imx/imx6_anatopreg.h
@@ -58,6 +58,9 @@
 #define	IMX6_ANALOG_CCM_PLL_SYS_NUM			0x050
 #define	IMX6_ANALOG_CCM_PLL_SYS_DENOM			0x060
 #define	IMX6_ANALOG_CCM_PLL_AUDIO			0x070
+#define	   IMX6_ANALOG_CCM_PLL_AUDIO_ENABLE		  (1 << 13)
+#define	   IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT	  0
+#define	   IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_MASK	  0x7f
 #define	IMX6_ANALOG_CCM_PLL_AUDIO_SET			0x074
 #define	IMX6_ANALOG_CCM_PLL_AUDIO_CLR			0x078
 #define	IMX6_ANALOG_CCM_PLL_AUDIO_TOG			0x07C
diff --git a/sys/arm/freescale/imx/imx6_anatopvar.h b/sys/arm/freescale/imx/imx6_anatopvar.h
index 5ede711..4ebe672 100644
--- a/sys/arm/freescale/imx/imx6_anatopvar.h
+++ b/sys/arm/freescale/imx/imx6_anatopvar.h
@@ -42,4 +42,6 @@ void imx6_anatop_write_4(bus_size_t _offset, uint32_t _value);
 
 uint32_t imx6_get_cpu_clock(void);
 
+uint32_t pll4_configure_output(uint32_t mfi, uint32_t mfn, uint32_t mfd);
+
 #endif
diff --git a/sys/arm/freescale/imx/imx6_audmux.c b/sys/arm/freescale/imx/imx6_audmux.c
new file mode 100644
index 0000000..4ea2109
--- /dev/null
+++ b/sys/arm/freescale/imx/imx6_audmux.c
@@ -0,0 +1,159 @@
+/*-
+ * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * i.MX6 Digital Audio Multiplexer (AUDMUX)
+ * Chapter 16, i.MX 6Dual/6Quad Applications Processor Reference Manual,
+ * Rev. 1, 04/2013
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/malloc.h>
+#include <sys/endian.h>
+#include <sys/rman.h>
+#include <sys/timeet.h>
+#include <sys/timetc.h>
+
+#include <dev/fdt/fdt_common.h>
+#include <dev/ofw/openfirm.h>
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <machine/bus.h>
+#include <machine/fdt.h>
+#include <machine/cpu.h>
+#include <machine/intr.h>
+
+#define	READ4(_sc, _reg)	\
+	bus_space_read_4(_sc->bst, _sc->bsh, _reg)
+#define	WRITE4(_sc, _reg, _val)	\
+	bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
+
+#define	AUDMUX_PTCR(n)	(0x8 * (n - 1))	/* Port Timing Control Register */
+#define	 PTCR_TFS_DIR	(1 << 31)	/* Transmit Frame Sync Direction Control */
+#define	 PTCR_TFSEL_S	27		/* Transmit Frame Sync Select */
+#define	 PTCR_TFSEL_M	0xf
+#define	 PTCR_TCLKDIR	(1 << 26)	/* Transmit Clock Direction Control */
+#define	 PTCR_TCSEL_S	22		/* Transmit Clock Select. */
+#define	 PTCR_TCSEL_M	0xf
+#define	 PTCR_RFS_DIR	(1 << 21)	/* Receive Frame Sync Direction Control */
+#define	 PTCR_SYN	(1 << 11)
+#define	AUDMUX_PDCR(n)	(0x8 * (n - 1) + 0x4)	/* Port Data Control Reg */
+#define	 PDCR_RXDSEL_S		13	/* Receive Data Select */
+#define	 PDCR_RXDSEL_M		0x3
+#define	 PDCR_RXDSEL_PORT(n)	(n - 1)
+
+struct audmux_softc {
+	struct resource		*res[1];
+	bus_space_tag_t		bst;
+	bus_space_handle_t	bsh;
+	void			*ih;
+};
+
+static struct resource_spec audmux_spec[] = {
+	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
+	{ -1, 0 }
+};
+
+static int
+audmux_probe(device_t dev)
+{
+
+	if (!ofw_bus_status_okay(dev))
+		return (ENXIO);
+
+	if (!ofw_bus_is_compatible(dev, "fsl,imx6q-audmux"))
+		return (ENXIO);
+
+	device_set_desc(dev, "i.MX6 Digital Audio Multiplexer");
+	return (BUS_PROBE_DEFAULT);
+}
+
+static int
+audmux_configure(struct audmux_softc *sc,
+	int ssi_port, int audmux_port)
+{
+	uint32_t reg;
+
+	/* Direction: output */
+	reg = (PTCR_TFS_DIR | PTCR_TCLKDIR | PTCR_SYN);
+	WRITE4(sc, AUDMUX_PTCR(audmux_port), reg);
+
+	/* Select source */
+	reg = (PDCR_RXDSEL_PORT(ssi_port) << PDCR_RXDSEL_S);
+	WRITE4(sc, AUDMUX_PDCR(audmux_port), reg);
+
+	return (0);
+}
+
+static int
+audmux_attach(device_t dev)
+{
+	struct audmux_softc *sc;
+
+	sc = device_get_softc(dev);
+
+	if (bus_alloc_resources(dev, audmux_spec, sc->res)) {
+		device_printf(dev, "could not allocate resources\n");
+		return (ENXIO);
+	}
+
+	/* Memory interface */
+	sc->bst = rman_get_bustag(sc->res[0]);
+	sc->bsh = rman_get_bushandle(sc->res[0]);
+
+	/*
+	 * Direct SSI1 output to AUDMUX5 pins.
+	 * TODO: dehardcore this.
+	 */
+	audmux_configure(sc, 1, 5);
+
+	return (0);
+};
+
+static device_method_t audmux_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		audmux_probe),
+	DEVMETHOD(device_attach,	audmux_attach),
+	{ 0, 0 }
+};
+
+static driver_t audmux_driver = {
+	"audmux",
+	audmux_methods,
+	sizeof(struct audmux_softc),
+};
+
+static devclass_t audmux_devclass;
+
+DRIVER_MODULE(audmux, simplebus, audmux_driver, audmux_devclass, 0, 0);
diff --git a/sys/arm/freescale/imx/imx6_ccm.c b/sys/arm/freescale/imx/imx6_ccm.c
index 2c80bd9..8d7f14f 100644
--- a/sys/arm/freescale/imx/imx6_ccm.c
+++ b/sys/arm/freescale/imx/imx6_ccm.c
@@ -94,7 +94,7 @@ ccm_init_gates(struct ccm_softc *sc)
 	WR4(sc, CCM_CCGR2, 0x0fffffc0); /* ipmux & ipsync (bridges), iomux, i2c */
 	WR4(sc, CCM_CCGR3, 0x3ff00000); /* DDR memory controller */
 	WR4(sc, CCM_CCGR4, 0x0000f300); /* pl301 bus crossbar */
-	WR4(sc, CCM_CCGR5, 0x0f000000); /* uarts */
+	WR4(sc, CCM_CCGR5, 0x0ffc00c0); /* uarts, ssi, sdma */
 	WR4(sc, CCM_CCGR6, 0x000000ff); /* usdhc 1-4 */
 }
 
@@ -180,6 +180,58 @@ ccm_probe(device_t dev)
 }
 
 void
+imx_ccm_ssi_configure(device_t _ssidev)
+{
+	struct ccm_softc *sc;
+	uint32_t reg;
+
+	sc = ccm_sc;
+
+	/*
+	 * Select PLL4 (Audio PLL) clock multiplexer as source.
+	 * PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM).
+	 */
+
+	reg = RD4(sc, CCM_CSCMR1);
+	reg &= ~(SSI_CLK_SEL_M << SSI1_CLK_SEL_S);
+	reg |= (SSI_CLK_SEL_PLL4 << SSI1_CLK_SEL_S);
+	reg &= ~(SSI_CLK_SEL_M << SSI2_CLK_SEL_S);
+	reg |= (SSI_CLK_SEL_PLL4 << SSI2_CLK_SEL_S);
+	reg &= ~(SSI_CLK_SEL_M << SSI3_CLK_SEL_S);
+	reg |= (SSI_CLK_SEL_PLL4 << SSI3_CLK_SEL_S);
+	WR4(sc, CCM_CSCMR1, reg);
+
+	/*
+	 * Ensure we have set hardware-default values
+	 * for pre and post dividers.
+	 */
+
+	/* SSI1 and SSI3 */
+	reg = RD4(sc, CCM_CS1CDR);
+	/* Divide by 2 */
+	reg &= ~(SSI_CLK_PODF_MASK << SSI1_CLK_PODF_SHIFT);
+	reg &= ~(SSI_CLK_PODF_MASK << SSI3_CLK_PODF_SHIFT);
+	reg |= (0x1 << SSI1_CLK_PODF_SHIFT);
+	reg |= (0x1 << SSI3_CLK_PODF_SHIFT);
+	/* Divide by 4 */
+	reg &= ~(SSI_CLK_PRED_MASK << SSI1_CLK_PRED_SHIFT);
+	reg &= ~(SSI_CLK_PRED_MASK << SSI3_CLK_PRED_SHIFT);
+	reg |= (0x3 << SSI1_CLK_PRED_SHIFT);
+	reg |= (0x3 << SSI3_CLK_PRED_SHIFT);
+	WR4(sc, CCM_CS1CDR, reg);
+
+	/* SSI2 */
+	reg = RD4(sc, CCM_CS2CDR);
+	/* Divide by 2 */
+	reg &= ~(SSI_CLK_PODF_MASK << SSI2_CLK_PODF_SHIFT);
+	reg |= (0x1 << SSI2_CLK_PODF_SHIFT);
+	/* Divide by 4 */
+	reg &= ~(SSI_CLK_PRED_MASK << SSI2_CLK_PRED_SHIFT);
+	reg |= (0x3 << SSI2_CLK_PRED_SHIFT);
+	WR4(sc, CCM_CS2CDR, reg);
+}
+
+void
 imx_ccm_usb_enable(device_t _usbdev)
 {
 
diff --git a/sys/arm/freescale/imx/imx6_ccmreg.h b/sys/arm/freescale/imx/imx6_ccmreg.h
index d50c190..31d92ca 100644
--- a/sys/arm/freescale/imx/imx6_ccmreg.h
+++ b/sys/arm/freescale/imx/imx6_ccmreg.h
@@ -29,6 +29,26 @@
 #ifndef	IMX6_CCMREG_H
 #define	IMX6_CCMREG_H
 
+#define	CCM_CSCMR1			0x01C
+#define	  SSI1_CLK_SEL_S		  10
+#define	  SSI2_CLK_SEL_S		  12
+#define	  SSI3_CLK_SEL_S		  14
+#define	  SSI_CLK_SEL_M			  0x3
+#define	  SSI_CLK_SEL_508_PFD		  0
+#define	  SSI_CLK_SEL_454_PFD		  1
+#define	  SSI_CLK_SEL_PLL4		  2
+#define	CCM_CSCMR2			0x020
+#define	CCM_CS1CDR			0x028
+#define	  SSI1_CLK_PODF_SHIFT		  0
+#define	  SSI1_CLK_PRED_SHIFT		  6
+#define	  SSI3_CLK_PODF_SHIFT		  16
+#define	  SSI3_CLK_PRED_SHIFT		  22
+#define	  SSI_CLK_PODF_MASK		  0x3f
+#define	  SSI_CLK_PRED_MASK		  0x7
+#define	CCM_CS2CDR			0x02C
+#define	  SSI2_CLK_PODF_SHIFT		  0
+#define	  SSI2_CLK_PRED_SHIFT		  6
+#define	CCM_CSCDR2			0x038
 #define	CCM_CLPCR			0x054
 #define	  CCM_CLPCR_LPM_MASK		  0x03
 #define	  CCM_CLPCR_LPM_RUN		  0x00
diff --git a/sys/arm/freescale/imx/imx6_sdma.c b/sys/arm/freescale/imx/imx6_sdma.c
new file mode 100644
index 0000000..4a4c287
--- /dev/null
+++ b/sys/arm/freescale/imx/imx6_sdma.c
@@ -0,0 +1,518 @@
+/*-
+ * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * i.MX6 Smart Direct Memory Access Controller (sDMA)
+ * Chapter 41, i.MX 6Dual/6Quad Applications Processor Reference Manual,
+ * Rev. 1, 04/2013
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/malloc.h>
+#include <sys/endian.h>
+#include <sys/rman.h>
+#include <sys/timeet.h>
+#include <sys/timetc.h>
+#include <sys/firmware.h>
+
+#include <vm/vm.h>
+#include <vm/vm_extern.h>
+#include <vm/vm_kern.h>
+
+#include <dev/fdt/fdt_common.h>
+#include <dev/ofw/openfirm.h>
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <machine/bus.h>
+#include <machine/fdt.h>
+#include <machine/cpu.h>
+#include <machine/intr.h>
+
+#include <arm/freescale/imx/imx6_sdma.h>
+
+#define	MAX_BD	(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
+
+#define	READ4(_sc, _reg)	\
+	bus_space_read_4(_sc->bst, _sc->bsh, _reg)
+#define	WRITE4(_sc, _reg, _val)	\
+	bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
+
+struct sdma_softc *sdma_sc;
+
+static struct resource_spec sdma_spec[] = {
+	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
+	{ SYS_RES_IRQ,		0,	RF_ACTIVE },
+	{ -1, 0 }
+};
+
+static void
+sdma_intr(void *arg)
+{
+	struct sdma_buffer_descriptor *bd;
+	struct sdma_channel *channel;
+	struct sdma_conf *conf;
+	struct sdma_softc *sc;
+	int pending;
+	int i;
+	int j;
+
+	sc = arg;
+
+	pending = READ4(sc, SDMAARM_INTR);
+
+	/* Ack intr */
+	WRITE4(sc, SDMAARM_INTR, pending);
+
+	for (i = 0; i < SDMA_N_CHANNELS; i++) {
+		if ((pending & (1 << i)) == 0)
+			continue;
+		channel = &sc->channel[i];
+		conf = channel->conf;
+		if (!conf)
+			continue;
+		for (j = 0; j < conf->num_bd; j++) {
+			bd = &channel->bd[j];
+			bd->mode.status |= BD_DONE;
+			if (bd->mode.status & BD_RROR)
+				printf("sDMA error\n");
+		}
+
+		conf->ih(conf->ih_user, 1);
+
+		WRITE4(sc, SDMAARM_HSTART, (1 << i));
+	}
+}
+
+static int
+sdma_probe(device_t dev)
+{
+
+	if (!ofw_bus_status_okay(dev))
+		return (ENXIO);
+
+	if (!ofw_bus_is_compatible(dev, "fsl,imx6q-sdma"))
+		return (ENXIO);
+
+	device_set_desc(dev, "i.MX6 Smart Direct Memory Access Controller");
+	return (BUS_PROBE_DEFAULT);
+}
+
+int
+sdma_start(int chn)
+{
+	struct sdma_softc *sc;
+
+	sc = sdma_sc;
+
+	WRITE4(sc, SDMAARM_HSTART, (1 << chn));
+
+	return (0);
+}
+
+int
+sdma_stop(int chn)
+{
+	struct sdma_softc *sc;
+
+	sc = sdma_sc;
+
+	WRITE4(sc, SDMAARM_STOP_STAT, (1 << chn));
+
+	return (0);
+}
+
+int
+sdma_alloc(void)
+{
+	struct sdma_channel *channel;
+	struct sdma_softc *sc;
+	int found;
+	int chn;
+	int i;
+
+	sc = sdma_sc;
+	found = 0;
+
+	/* Channel 0 can't be used */
+	for (i = 1; i < SDMA_N_CHANNELS; i++) {
+		channel = &sc->channel[i];
+		if (channel->in_use == 0) {
+			channel->in_use = 1;
+			found = 1;
+			break;
+		}
+	}
+
+	if (!found)
+		return (-1);
+
+	chn = i;
+
+	/* Allocate area for buffer descriptors */
+	channel->bd = (void *)kmem_alloc_contig(kernel_arena,
+	    PAGE_SIZE, M_ZERO, 0, ~0, PAGE_SIZE, 0,
+	    VM_MEMATTR_UNCACHEABLE);
+
+	return (chn);
+}
+
+int
+sdma_free(int chn)
+{
+	struct sdma_channel *channel;
+	struct sdma_softc *sc;
+
+	sc = sdma_sc;
+
+	channel = &sc->channel[chn];
+	channel->in_use = 0;
+
+	kmem_free(kernel_arena, (vm_offset_t)channel->bd,
+			PAGE_SIZE);
+
+	return (0);
+}
+
+static int
+sdma_overrides(struct sdma_softc *sc, int chn,
+		int evt, int host, int dsp)
+{
+	int reg;
+
+	/* Ignore sDMA requests */
+	reg = READ4(sc, SDMAARM_EVTOVR);
+	if (evt)
+		reg |= (1 << chn);
+	else
+		reg &= ~(1 << chn);
+	WRITE4(sc, SDMAARM_EVTOVR, reg);
+
+	/* Ignore enable bit (HE) */
+	reg = READ4(sc, SDMAARM_HOSTOVR);
+	if (host)
+		reg |= (1 << chn);
+	else
+		reg &= ~(1 << chn);
+	WRITE4(sc, SDMAARM_HOSTOVR, reg);
+
+	/* Prevent sDMA channel from starting */
+	reg = READ4(sc, SDMAARM_DSPOVR);
+	if (!dsp)
+		reg |= (1 << chn);
+	else
+		reg &= ~(1 << chn);
+	WRITE4(sc, SDMAARM_DSPOVR, reg);
+
+	return (0);
+}
+
+int
+sdma_configure(int chn, struct sdma_conf *conf)
+{
+	struct sdma_buffer_descriptor *bd0;
+	struct sdma_buffer_descriptor *bd;
+	struct sdma_context_data *context;
+	struct sdma_channel *channel;
+	struct sdma_softc *sc;
+#if 0
+	int timeout;
+	int ret;
+#endif
+	int i;
+
+	sc = sdma_sc;
+
+	channel = &sc->channel[chn];
+	channel->conf = conf;
+
+	/* Ensure operation has stopped */
+	sdma_stop(chn);
+
+	/* Set priority and enable the channel */
+	WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1);
+	WRITE4(sc, SDMAARM_CHNENBL(conf->event), (1 << chn));
+
+	sdma_overrides(sc, chn, 0, 0, 0);
+
+	if (conf->num_bd > MAX_BD) {
+		device_printf(sc->dev, "Error: too much buffer"
+				" descriptors requested\n");
+		return (-1);
+	}
+
+	for (i = 0; i < conf->num_bd; i++) {
+		bd = &channel->bd[i];
+		bd->mode.command = conf->command;
+		bd->mode.status = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
+		if (i == (conf->num_bd - 1))
+			bd->mode.status |= BD_WRAP;
+		bd->mode.count = conf->period;
+		bd->buffer_addr = conf->saddr + (conf->period * i);
+		bd->ext_buffer_addr = 0;
+	}
+
+	sc->ccb[chn].base_bd_ptr = vtophys(channel->bd);
+	sc->ccb[chn].current_bd_ptr = vtophys(channel->bd);
+
+	/*
+	 * Load context.
+	 *
+	 * i.MX6 Reference Manual: Appendix A SDMA Scripts
+	 * A.3.1.7.1 (mcu_2_app)
+	 */
+
+	/*
+	 * TODO: allow using other scripts
+	 */
+	context = sc->context;
+	memset(context, 0, sizeof(*context));
+	context->channel_state.pc = sc->fw_scripts->mcu_2_app_addr;
+
+	/*
+	 * Tx FIFO 0 address (r6)
+	 * Event_mask (r1)
+	 * Event2_mask (r0)
+	 * Watermark level (r7)
+	 */
+
+	if (conf->event > 32) {
+		context->gReg[0] = (1 << (conf->event % 32));
+		context->gReg[1] = 0;
+	} else {
+		context->gReg[0] = 0;
+		context->gReg[1] = (1 << conf->event);
+	}
+
+	context->gReg[6] = conf->daddr;
+	context->gReg[7] = conf->word_length;
+
+	bd0 = sc->bd0;
+	bd0->mode.command = C0_SETDM;
+	bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
+	bd0->mode.count = sizeof(*context) / 4;
+	bd0->buffer_addr = sc->context_phys;
+	bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * chn;
+
+	WRITE4(sc, SDMAARM_HSTART, 1);
+
+#if 0
+	/* Debug purposes */
+
+	timeout = 1000;
+	while (!(ret = READ4(sc, SDMAARM_INTR) & 1)) {
+		if (timeout-- <= 0)
+			break;
+		DELAY(10);
+	};
+
+	if (!ret) {
+		device_printf(sc->dev, "Failed to load context.\n");
+		return (-1);
+	}
+
+	WRITE4(sc, SDMAARM_INTR, ret);
+
+	device_printf(sc->dev, "Context loaded successfully.\n");
+#endif
+
+	return (0);
+}
+
+static int
+load_firmware(struct sdma_softc *sc)
+{
+	struct sdma_firmware_header *header;
+	const struct firmware *fp;
+
+	fp = firmware_get("sdma_fw");
+	if (fp == NULL) {
+		device_printf(sc->dev, "Can't get firmware.\n");
+		return (-1);
+	}
+
+	header = (struct sdma_firmware_header *)fp->data;
+	if (header->magic != FW_HEADER_MAGIC) {
+		device_printf(sc->dev, "Can't use firmware.\n");
+		return (-1);
+	}
+
+	sc->fw_header = header;
+	sc->fw_scripts = (void *)((char *)header +
+				header->script_addrs_start);
+
+	return (0);
+}
+
+static int
+boot_firmware(struct sdma_softc *sc)
+{
+	struct sdma_buffer_descriptor *bd0;
+	uint32_t *ram_code;
+	int timeout;
+	int ret;
+	int chn;
+	int sz;
+	int i;
+
+	ram_code = (void *)((char *)sc->fw_header +
+			sc->fw_header->ram_code_start);
+
+	/* Make sure SDMA has not started yet */
+	WRITE4(sc, SDMAARM_MC0PTR, 0);
+
+	sz = SDMA_N_CHANNELS * sizeof(struct sdma_channel_control) + \
+	    sizeof(struct sdma_context_data);
+	sc->ccb = (void *)kmem_alloc_contig(kernel_arena,
+	    sz, M_ZERO, 0, ~0, PAGE_SIZE, 0, VM_MEMATTR_UNCACHEABLE);
+	sc->ccb_phys = vtophys(sc->ccb);
+
+	sc->context = (void *)((char *)sc->ccb + \
+	    SDMA_N_CHANNELS * sizeof(struct sdma_channel_control));
+	sc->context_phys = vtophys(sc->context);
+
+	/* Disable all the channels */
+	for (i = 0; i < SDMA_N_EVENTS; i++)
+		WRITE4(sc, SDMAARM_CHNENBL(i), 0);
+
+	/* All channels have priority 0 */
+	for (i = 0; i < SDMA_N_CHANNELS; i++)
+		WRITE4(sc, SDMAARM_SDMA_CHNPRI(i), 0);
+
+	/* Channel 0 is used for booting firmware */
+	chn = 0;
+
+	sc->bd0 = (void *)kmem_alloc_contig(kernel_arena,
+	    PAGE_SIZE, M_ZERO, 0, ~0, PAGE_SIZE, 0,
+	    VM_MEMATTR_UNCACHEABLE);
+	bd0 = sc->bd0;
+	sc->ccb[chn].base_bd_ptr = vtophys(bd0);
+	sc->ccb[chn].current_bd_ptr = vtophys(bd0);
+
+	WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1);
+
+	sdma_overrides(sc, chn, 1, 0, 0);
+
+	/* XXX: not sure what is that */
+	WRITE4(sc, SDMAARM_CHN0ADDR, 0x4050);
+
+	WRITE4(sc, SDMAARM_CONFIG, 0);
+	WRITE4(sc, SDMAARM_MC0PTR, sc->ccb_phys);
+	WRITE4(sc, SDMAARM_CONFIG, CONFIG_CSM);
+	WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1);
+
+	bd0->mode.command = C0_SETPM;
+	bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
+	bd0->mode.count = sc->fw_header->ram_code_size / 2;
+	bd0->buffer_addr = vtophys(ram_code);
+	bd0->ext_buffer_addr = sc->fw_scripts->ram_code_start_addr;
+
+	WRITE4(sc, SDMAARM_HSTART, 1);
+
+	timeout = 100;
+	while (!(ret = READ4(sc, SDMAARM_INTR) & 1)) {
+		if (timeout-- <= 0)
+			break;
+		DELAY(10);
+	};
+
+	if (ret == 0) {
+		device_printf(sc->dev, "SDMA failed to boot\n");
+		return (-1);
+	}
+
+	WRITE4(sc, SDMAARM_INTR, ret);
+
+#if 0
+	device_printf(sc->dev, "SDMA booted successfully.\n");
+#endif
+
+	/* Debug is disabled */
+	WRITE4(sc, SDMAARM_ONCE_ENB, 0);
+
+	return (0);
+}
+
+static int
+sdma_attach(device_t dev)
+{
+	struct sdma_softc *sc;
+	int err;
+
+	sc = device_get_softc(dev);
+	sc->dev = dev;
+
+	if (bus_alloc_resources(dev, sdma_spec, sc->res)) {
+		device_printf(dev, "could not allocate resources\n");
+		return (ENXIO);
+	}
+
+	/* Memory interface */
+	sc->bst = rman_get_bustag(sc->res[0]);
+	sc->bsh = rman_get_bushandle(sc->res[0]);
+
+	sdma_sc = sc;
+
+	/* Setup interrupt handler */
+	err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE,
+	    NULL, sdma_intr, sc, &sc->ih);
+	if (err) {
+		device_printf(dev, "Unable to alloc interrupt resource.\n");
+		return (ENXIO);
+	}
+
+	if (load_firmware(sc) == -1)
+		return (ENXIO);
+
+	if (boot_firmware(sc) == -1)
+		return (ENXIO);
+
+	return (0);
+};
+
+static device_method_t sdma_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		sdma_probe),
+	DEVMETHOD(device_attach,	sdma_attach),
+	{ 0, 0 }
+};
+
+static driver_t sdma_driver = {
+	"sdma",
+	sdma_methods,
+	sizeof(struct sdma_softc),
+};
+
+static devclass_t sdma_devclass;
+
+DRIVER_MODULE(sdma, simplebus, sdma_driver, sdma_devclass, 0, 0);
diff --git a/sys/arm/freescale/imx/imx6_sdma.h b/sys/arm/freescale/imx/imx6_sdma.h
new file mode 100644
index 0000000..0f970de
--- /dev/null
+++ b/sys/arm/freescale/imx/imx6_sdma.h
@@ -0,0 +1,245 @@
+/*-
+ * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#define	SDMAARM_MC0PTR		0x00	/* ARM platform Channel 0 Pointer */
+#define	SDMAARM_INTR		0x04	/* Channel Interrupts */
+#define	SDMAARM_STOP_STAT	0x08	/* Channel Stop/Channel Status */
+#define	SDMAARM_HSTART		0x0C	/* Channel Start */
+#define	SDMAARM_EVTOVR		0x10	/* Channel Event Override */
+#define	SDMAARM_DSPOVR		0x14	/* Channel BP Override */
+#define	SDMAARM_HOSTOVR		0x18	/* Channel ARM platform Override */
+#define	SDMAARM_EVTPEND		0x1C	/* Channel Event Pending */
+#define	SDMAARM_RESET		0x24	/* Reset Register */
+#define	SDMAARM_EVTERR		0x28	/* DMA Request Error Register */
+#define	SDMAARM_INTRMASK	0x2C	/* Channel ARM platform Interrupt Mask */
+#define	SDMAARM_PSW		0x30	/* Schedule Status */
+#define	SDMAARM_EVTERRDBG	0x34	/* DMA Request Error Register */
+#define	SDMAARM_CONFIG		0x38	/* Configuration Register */
+#define	 CONFIG_CSM		0x3
+#define	SDMAARM_SDMA_LOCK	0x3C	/* SDMA LOCK */
+#define	SDMAARM_ONCE_ENB	0x40	/* OnCE Enable */
+#define	SDMAARM_ONCE_DATA	0x44	/* OnCE Data Register */
+#define	SDMAARM_ONCE_INSTR	0x48	/* OnCE Instruction Register */
+#define	SDMAARM_ONCE_STAT	0x4C	/* OnCE Status Register */
+#define	SDMAARM_ONCE_CMD	0x50	/* OnCE Command Register */
+#define	SDMAARM_ILLINSTADDR	0x58	/* Illegal Instruction Trap Address */
+#define	SDMAARM_CHN0ADDR	0x5C	/* Channel 0 Boot Address */
+#define	SDMAARM_EVT_MIRROR	0x60	/* DMA Requests */
+#define	SDMAARM_EVT_MIRROR2	0x64	/* DMA Requests 2 */
+#define	SDMAARM_XTRIG_CONF1	0x70	/* Cross-Trigger Events Configuration Register 1 */
+#define	SDMAARM_XTRIG_CONF2	0x74	/* Cross-Trigger Events Configuration Register 2 */
+#define	SDMAARM_SDMA_CHNPRI(n)	(0x100 + 0x4 * n)	/* Channel Priority Registers */
+#define	SDMAARM_CHNENBL(n)	(0x200 + 0x4 * n)	/* Channel Enable RAM */
+
+/* SDMA Event Mappings */
+#define	SSI1_RX_1	35
+#define	SSI1_TX_1	36
+#define	SSI1_RX_0	37
+#define	SSI1_TX_0	38
+#define	SSI2_RX_1	39
+#define	SSI2_TX_1	40
+#define	SSI2_RX_0	41
+#define	SSI2_TX_0	42
+#define	SSI3_RX_1	43
+#define	SSI3_TX_1	44
+#define	SSI3_RX_0	45
+#define	SSI3_TX_0	46
+
+#define	C0_ADDR		0x01
+#define	C0_LOAD		0x02
+#define	C0_DUMP		0x03
+#define	C0_SETCTX	0x07
+#define	C0_GETCTX	0x03
+#define	C0_SETDM	0x01
+#define	C0_SETPM	0x04
+#define	C0_GETDM	0x02
+#define	C0_GETPM	0x08
+
+#define	BD_DONE		0x01
+#define	BD_WRAP		0x02
+#define	BD_CONT		0x04
+#define	BD_INTR		0x08
+#define	BD_RROR		0x10
+#define	BD_LAST		0x20
+#define	BD_EXTD		0x80
+
+/* sDMA data transfer length */
+#define	CMD_4BYTES	0
+#define	CMD_3BYTES	3
+#define	CMD_2BYTES	2
+#define	CMD_1BYTES	1
+
+struct sdma_firmware_header {
+	uint32_t	magic;
+	uint32_t	version_major;
+	uint32_t	version_minor;
+	uint32_t	script_addrs_start;
+	uint32_t	num_script_addrs;
+	uint32_t	ram_code_start;
+	uint32_t	ram_code_size;
+};
+
+struct sdma_mode_count {
+	uint16_t count;
+	uint8_t status;
+	uint8_t command;
+};
+
+struct sdma_buffer_descriptor {
+	struct sdma_mode_count	mode;
+	uint32_t		buffer_addr;
+	uint32_t		ext_buffer_addr;
+} __packed;
+
+struct sdma_channel_control {
+	uint32_t	current_bd_ptr;
+	uint32_t	base_bd_ptr;
+	uint32_t	unused[2];
+} __packed;
+
+struct sdma_state_registers {
+	uint32_t	pc     :14;
+	uint32_t	unused1: 1;
+	uint32_t	t      : 1;
+	uint32_t	rpc    :14;
+	uint32_t	unused0: 1;
+	uint32_t	sf     : 1;
+	uint32_t	spc    :14;
+	uint32_t	unused2: 1;
+	uint32_t	df     : 1;
+	uint32_t	epc    :14;
+	uint32_t	lm     : 2;
+} __packed;
+
+struct sdma_context_data {
+	struct sdma_state_registers	channel_state;
+	uint32_t	gReg[8];
+	uint32_t	mda;
+	uint32_t	msa;
+	uint32_t	ms;
+	uint32_t	md;
+	uint32_t	pda;
+	uint32_t	psa;
+	uint32_t	ps;
+	uint32_t	pd;
+	uint32_t	ca;
+	uint32_t	cs;
+	uint32_t	dda;
+	uint32_t	dsa;
+	uint32_t	ds;
+	uint32_t	dd;
+	uint32_t	unused[8];
+} __packed;
+
+/* SDMA firmware script pointers */
+struct sdma_script_start_addrs {
+	int32_t	ap_2_ap_addr;
+	int32_t	ap_2_bp_addr;
+	int32_t	ap_2_ap_fixed_addr;
+	int32_t	bp_2_ap_addr;
+	int32_t	loopback_on_dsp_side_addr;
+	int32_t	mcu_interrupt_only_addr;
+	int32_t	firi_2_per_addr;
+	int32_t	firi_2_mcu_addr;
+	int32_t	per_2_firi_addr;
+	int32_t	mcu_2_firi_addr;
+	int32_t	uart_2_per_addr;
+	int32_t	uart_2_mcu_addr;
+	int32_t	per_2_app_addr;
+	int32_t	mcu_2_app_addr;
+	int32_t	per_2_per_addr;
+	int32_t	uartsh_2_per_addr;
+	int32_t	uartsh_2_mcu_addr;
+	int32_t	per_2_shp_addr;
+	int32_t	mcu_2_shp_addr;
+	int32_t	ata_2_mcu_addr;
+	int32_t	mcu_2_ata_addr;
+	int32_t	app_2_per_addr;
+	int32_t	app_2_mcu_addr;
+	int32_t	shp_2_per_addr;
+	int32_t	shp_2_mcu_addr;
+	int32_t	mshc_2_mcu_addr;
+	int32_t	mcu_2_mshc_addr;
+	int32_t	spdif_2_mcu_addr;
+	int32_t	mcu_2_spdif_addr;
+	int32_t	asrc_2_mcu_addr;
+	int32_t	ext_mem_2_ipu_addr;
+	int32_t	descrambler_addr;
+	int32_t	dptc_dvfs_addr;
+	int32_t	utra_addr;
+	int32_t	ram_code_start_addr;
+	int32_t	mcu_2_ssish_addr;
+	int32_t	ssish_2_mcu_addr;
+	int32_t	hdmi_dma_addr;
+};
+
+#define	SDMA_N_CHANNELS 32
+#define	SDMA_N_EVENTS	48
+#define	FW_HEADER_MAGIC	0x414d4453
+
+struct sdma_channel {
+	struct sdma_conf		*conf;
+	struct sdma_buffer_descriptor	*bd;
+	uint8_t 			in_use;
+};
+
+struct sdma_softc {
+	struct resource			*res[2];
+	bus_space_tag_t			bst;
+	bus_space_handle_t		bsh;
+	device_t			dev;
+	void				*ih;
+	struct sdma_channel_control	*ccb;
+	struct sdma_buffer_descriptor	*bd0;
+	struct sdma_context_data	*context;
+	struct sdma_channel		channel[SDMA_N_CHANNELS];
+	uint32_t			num_bd;
+	uint32_t			ccb_phys;
+	uint32_t			context_phys;
+	struct sdma_firmware_header	*fw_header;
+	struct sdma_script_start_addrs	*fw_scripts;
+};
+
+struct sdma_conf {
+	bus_addr_t	saddr;
+	bus_addr_t	daddr;
+	uint32_t	word_length;
+	uint32_t	nbits;
+	uint32_t	command;
+	uint32_t	num_bd;
+	uint32_t	event;
+	uint32_t	period;
+	uint32_t	(*ih)(void *, int);
+	void		*ih_user;
+};
+
+int sdma_configure(int, struct sdma_conf *);
+int sdma_start(int);
+int sdma_stop(int);
+int sdma_alloc(void);
+int sdma_free(int);
diff --git a/sys/arm/freescale/imx/imx6_ssi.c b/sys/arm/freescale/imx/imx6_ssi.c
new file mode 100644
index 0000000..af8a9e8
--- /dev/null
+++ b/sys/arm/freescale/imx/imx6_ssi.c
@@ -0,0 +1,855 @@
+/*-
+ * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * i.MX6 Synchronous Serial Interface (SSI)
+ *
+ * Chapter 61, i.MX 6Dual/6Quad Applications Processor Reference Manual,
+ * Rev. 1, 04/2013
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/malloc.h>
+#include <sys/rman.h>
+#include <sys/timeet.h>
+#include <sys/timetc.h>
+
+#include <dev/sound/pcm/sound.h>
+#include <dev/sound/chip.h>
+#include <mixer_if.h>
+
+#include <dev/fdt/fdt_common.h>
+#include <dev/ofw/openfirm.h>
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <machine/bus.h>
+#include <machine/fdt.h>
+#include <machine/cpu.h>
+#include <machine/intr.h>
+
+#include <arm/freescale/imx/imx6_sdma.h>
+#include <arm/freescale/imx/imx6_anatopvar.h>
+#include <arm/freescale/imx/imx_ccmvar.h>
+
+#define	READ4(_sc, _reg)	\
+	bus_space_read_4(_sc->bst, _sc->bsh, _reg)
+#define	WRITE4(_sc, _reg, _val)	\
+	bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
+
+#define	SSI_NCHANNELS	1
+
+/* i.MX6 SSI registers */
+
+#define	SSI_STX0	0x00 /* Transmit Data Register n */
+#define	SSI_STX1	0x04 /* Transmit Data Register n */
+#define	SSI_SRX0	0x08 /* Receive Data Register n */
+#define	SSI_SRX1	0x0C /* Receive Data Register n */
+#define	SSI_SCR		0x10 /* Control Register */
+#define	 SCR_I2S_MODE_S	5    /* I2S Mode Select. */
+#define	 SCR_I2S_MODE_M	0x3
+#define	 SCR_SYN	(1 << 4)
+#define	 SCR_NET       	(1 << 3)  /* Network mode */
+#define	 SCR_RE		(1 << 2)  /* Receive Enable. */
+#define	 SCR_TE		(1 << 1)  /* Transmit Enable. */
+#define	 SCR_SSIEN	(1 << 0)  /* SSI Enable */
+#define	SSI_SISR	0x14      /* Interrupt Status Register */
+#define	SSI_SIER	0x18      /* Interrupt Enable Register */
+#define	 SIER_RDMAE	(1 << 22) /* Receive DMA Enable. */
+#define	 SIER_RIE	(1 << 21) /* Receive Interrupt Enable. */
+#define	 SIER_TDMAE	(1 << 20) /* Transmit DMA Enable. */
+#define	 SIER_TIE	(1 << 19) /* Transmit Interrupt Enable. */
+#define	 SIER_TDE0IE	(1 << 12) /* Transmit Data Register Empty 0. */
+#define	 SIER_TUE0IE	(1 << 8)  /* Transmitter Underrun Error 0. */
+#define	 SIER_TFE0IE	(1 << 0)  /* Transmit FIFO Empty 0 IE. */
+#define	SSI_STCR	0x1C	  /* Transmit Configuration Register */
+#define	 STCR_TXBIT0	(1 << 9)  /* Transmit Bit 0 shift MSB/LSB */
+#define	 STCR_TFEN1	(1 << 8)  /* Transmit FIFO Enable 1. */
+#define	 STCR_TFEN0	(1 << 7)  /* Transmit FIFO Enable 0. */
+#define	 STCR_TFDIR	(1 << 6)  /* Transmit Frame Direction. */
+#define	 STCR_TXDIR	(1 << 5)  /* Transmit Clock Direction. */
+#define	 STCR_TSHFD	(1 << 4)  /* Transmit Shift Direction. */
+#define	 STCR_TSCKP	(1 << 3)  /* Transmit Clock Polarity. */
+#define	 STCR_TFSI	(1 << 2)  /* Transmit Frame Sync Invert. */
+#define	 STCR_TFSL	(1 << 1)  /* Transmit Frame Sync Length. */
+#define	 STCR_TEFS	(1 << 0)  /* Transmit Early Frame Sync. */
+#define	SSI_SRCR	0x20      /* Receive Configuration Register */
+#define	SSI_STCCR	0x24      /* Transmit Clock Control Register */
+#define	 STCCR_DIV2	(1 << 18) /* Divide By 2. */
+#define	 STCCR_PSR	(1 << 17) /* Divide clock by 8. */
+#define	 WL3_WL0_S	13
+#define	 WL3_WL0_M	0xf
+#define	 DC4_DC0_S	8
+#define	 DC4_DC0_M	0x1f
+#define	 PM7_PM0_S	0
+#define	 PM7_PM0_M	0xff
+#define	SSI_SRCCR	0x28	/* Receive Clock Control Register */
+#define	SSI_SFCSR	0x2C	/* FIFO Control/Status Register */
+#define	 SFCSR_RFWM1_S	20	/* Receive FIFO Empty WaterMark 1 */
+#define	 SFCSR_RFWM1_M	0xf
+#define	 SFCSR_TFWM1_S	16	/* Transmit FIFO Empty WaterMark 1 */
+#define	 SFCSR_TFWM1_M	0xf
+#define	 SFCSR_RFWM0_S	4	/* Receive FIFO Empty WaterMark 0 */
+#define	 SFCSR_RFWM0_M	0xf
+#define	 SFCSR_TFWM0_S	0	/* Transmit FIFO Empty WaterMark 0 */
+#define	 SFCSR_TFWM0_M	0xf
+#define	SSI_SACNT	0x38	/* AC97 Control Register */
+#define	SSI_SACADD	0x3C	/* AC97 Command Address Register */
+#define	SSI_SACDAT	0x40	/* AC97 Command Data Register */
+#define	SSI_SATAG	0x44	/* AC97 Tag Register */
+#define	SSI_STMSK	0x48	/* Transmit Time Slot Mask Register */
+#define	SSI_SRMSK	0x4C	/* Receive Time Slot Mask Register */
+#define	SSI_SACCST	0x50	/* AC97 Channel Status Register */
+#define	SSI_SACCEN	0x54	/* AC97 Channel Enable Register */
+#define	SSI_SACCDIS	0x58	/* AC97 Channel Disable Register */
+
+static MALLOC_DEFINE(M_SSI, "ssi", "ssi audio");
+
+uint32_t ssi_dma_intr(void *arg, int chn);
+
+struct ssi_rate {
+	uint32_t speed;
+	uint32_t mfi; /* PLL4 Multiplication Factor Integer */
+	uint32_t mfn; /* PLL4 Multiplication Factor Numerator */
+	uint32_t mfd; /* PLL4 Multiplication Factor Denominator */
+	/* More dividers to configure can be added here */
+};
+
+static struct ssi_rate rate_map[] = {
+	{ 192000, 49, 152, 1000 }, /* PLL4 49.152 Mhz */
+	/* TODO: add more frequences */
+	{ 0, 0 },
+};
+
+/*
+ *  i.MX6 example bit clock formula
+ *
+ *  BCLK = 2 channels * 192000 hz * 24 bit = 9216000 hz = 
+ *     (24000000 * (49 + 152/1000.0) / 4 / 4 / 2 / 2 / 2 / 1 / 1)
+ *             ^     ^     ^      ^    ^   ^   ^   ^   ^   ^   ^
+ *             |     |     |      |    |   |   |   |   |   |   |
+ *  Fref ------/     |     |      |    |   |   |   |   |   |   |
+ *  PLL4 div select -/     |      |    |   |   |   |   |   |   |
+ *  PLL4 num --------------/      |    |   |   |   |   |   |   |
+ *  PLL4 denom -------------------/    |   |   |   |   |   |   |
+ *  PLL4 post div ---------------------/   |   |   |   |   |   |
+ *  CCM ssi pre div (CCM_CS1CDR) ----------/   |   |   |   |   |
+ *  CCM ssi post div (CCM_CS1CDR) -------------/   |   |   |   |
+ *  SSI PM7_PM0_S ---------------------------------/   |   |   |
+ *  SSI Fixed divider ---------------------------------/   |   |
+ *  SSI DIV2 ----------------------------------------------/   |
+ *  SSI PSR (prescaler /1 or /8) ------------------------------/
+ *
+ *  MCLK (Master clock) depends on DAC, usually BCLK * 4
+ */
+
+struct sc_info {
+	struct resource		*res[2];
+	bus_space_tag_t		bst;
+	bus_space_handle_t	bsh;
+	device_t		dev;
+	struct mtx		*lock;
+	void			*ih;
+	int			pos;
+	int			dma_size;
+	bus_dma_tag_t		dma_tag;
+	bus_dmamap_t		dma_map;
+	bus_addr_t		buf_base_phys;
+	uint32_t		*buf_base;
+	struct sdma_conf	*conf;
+	struct ssi_rate		*sr;
+	struct sdma_softc	*sdma_sc;
+	int			sdma_ev_rx;
+	int			sdma_ev_tx;
+	int			sdma_channel;
+};
+
+/* Channel registers */
+struct sc_chinfo {
+	struct snd_dbuf		*buffer;
+	struct pcm_channel	*channel;
+	struct sc_pcminfo	*parent;
+
+	/* Channel information */
+	uint32_t	dir;
+	uint32_t	format;
+
+	/* Flags */
+	uint32_t	run;
+};
+
+/* PCM device private data */
+struct sc_pcminfo {
+	device_t		dev;
+	uint32_t		(*ih)(struct sc_pcminfo *scp);
+	uint32_t		chnum;
+	struct sc_chinfo	chan[SSI_NCHANNELS];
+	struct sc_info		*sc;
+};
+
+static struct resource_spec ssi_spec[] = {
+	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
+	{ SYS_RES_IRQ,		0,	RF_ACTIVE },
+	{ -1, 0 }
+};
+
+static int setup_dma(struct sc_pcminfo *scp);
+static void setup_ssi(struct sc_info *);
+static void ssi_configure_clock(struct sc_info *);
+
+/*
+ * Mixer interface.
+ */
+
+static int
+ssimixer_init(struct snd_mixer *m)
+{
+	struct sc_pcminfo *scp;
+	struct sc_info *sc;
+	int mask;
+
+	scp = mix_getdevinfo(m);
+	sc = scp->sc;
+
+	if (sc == NULL)
+		return -1;
+
+	mask = SOUND_MASK_PCM;
+	mask |= SOUND_MASK_VOLUME;
+
+	snd_mtxlock(sc->lock);
+	pcm_setflags(scp->dev, pcm_getflags(scp->dev) | SD_F_SOFTPCMVOL);
+	mix_setdevs(m, mask);
+	snd_mtxunlock(sc->lock);
+
+	return (0);
+}
+
+static int
+ssimixer_set(struct snd_mixer *m, unsigned dev,
+    unsigned left, unsigned right)
+{
+	struct sc_pcminfo *scp;
+
+	scp = mix_getdevinfo(m);
+
+	/* Here we can configure hardware volume on our DAC */
+
+#if 1
+	device_printf(scp->dev, "ssimixer_set() %d %d\n",
+	    left, right);
+#endif
+
+	return (0);
+}
+
+static kobj_method_t ssimixer_methods[] = {
+	KOBJMETHOD(mixer_init,      ssimixer_init),
+	KOBJMETHOD(mixer_set,       ssimixer_set),
+	KOBJMETHOD_END
+};
+MIXER_DECLARE(ssimixer);
+
+
+/*
+ * Channel interface.
+ */
+
+static void *
+ssichan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
+    struct pcm_channel *c, int dir)
+{
+	struct sc_pcminfo *scp;
+	struct sc_chinfo *ch;
+	struct sc_info *sc;
+
+	scp = (struct sc_pcminfo *)devinfo;
+	sc = scp->sc;
+
+	snd_mtxlock(sc->lock);
+	ch = &scp->chan[0];
+	ch->dir = dir;
+	ch->run = 0;
+	ch->buffer = b;
+	ch->channel = c;
+	ch->parent = scp;
+	snd_mtxunlock(sc->lock);
+
+	if (sndbuf_setup(ch->buffer, sc->buf_base, sc->dma_size) != 0) {
+		device_printf(scp->dev, "Can't setup sndbuf.\n");
+		return NULL;
+	}
+
+	return ch;
+}
+
+static int
+ssichan_free(kobj_t obj, void *data)
+{
+	struct sc_chinfo *ch = data;
+	struct sc_pcminfo *scp = ch->parent;
+	struct sc_info *sc = scp->sc;
+
+#if 0
+	device_printf(scp->dev, "ssichan_free()\n");
+#endif
+
+	snd_mtxlock(sc->lock);
+	/* TODO: free channel buffer */
+	snd_mtxunlock(sc->lock);
+
+	return (0);
+}
+
+static int
+ssichan_setformat(kobj_t obj, void *data, uint32_t format)
+{
+	struct sc_chinfo *ch = data;
+
+	ch->format = format;
+
+	return (0);
+}
+
+static uint32_t
+ssichan_setspeed(kobj_t obj, void *data, uint32_t speed)
+{
+	struct sc_pcminfo *scp;
+	struct sc_chinfo *ch;
+	struct ssi_rate *sr;
+	struct sc_info *sc;
+	int threshold;
+	int i;
+
+	ch = data;
+	scp = ch->parent;
+	sc = scp->sc;
+
+	sr = NULL;
+
+	/* First look for equal frequency. */
+	for (i = 0; rate_map[i].speed != 0; i++) {
+		if (rate_map[i].speed == speed)
+			sr = &rate_map[i];
+	}
+
+	/* If no match, just find nearest. */
+	if (sr == NULL) {
+		for (i = 0; rate_map[i].speed != 0; i++) {
+			sr = &rate_map[i];
+			threshold = sr->speed + ((rate_map[i + 1].speed != 0) ?
+			    ((rate_map[i + 1].speed - sr->speed) >> 1) : 0);
+			if (speed < threshold)
+				break;
+		}
+	}
+
+	sc->sr = sr;
+
+	ssi_configure_clock(sc);
+
+	return (sr->speed);
+}
+
+static void
+ssi_configure_clock(struct sc_info *sc)
+{
+	struct ssi_rate *sr;
+
+	sr = sc->sr;
+
+	pll4_configure_output(sr->mfi, sr->mfn, sr->mfd);
+
+	/* Configure other dividers here, if any */
+}
+
+static uint32_t
+ssichan_setblocksize(kobj_t obj, void *data, uint32_t blocksize)
+{
+	struct sc_chinfo *ch = data;
+	struct sc_pcminfo *scp = ch->parent;
+	struct sc_info *sc = scp->sc;
+
+	sndbuf_resize(ch->buffer, sc->dma_size / blocksize, blocksize);
+
+	setup_dma(scp);
+
+	return (sndbuf_getblksz(ch->buffer));
+}
+
+uint32_t
+ssi_dma_intr(void *arg, int chn)
+{
+	struct sc_pcminfo *scp;
+	struct sdma_conf *conf;
+	struct sc_chinfo *ch;
+	struct sc_info *sc;
+	int bufsize;
+
+	scp = arg;
+	ch = &scp->chan[0];
+	sc = scp->sc;
+	conf = sc->conf;
+
+	bufsize = sndbuf_getsize(ch->buffer);
+
+	sc->pos += conf->period;
+	if (sc->pos >= bufsize)
+		sc->pos -= bufsize;
+
+	if (ch->run)
+		chn_intr(ch->channel);
+
+	return (0);
+}
+
+static int
+find_sdma_controller(struct sc_info *sc)
+{
+	struct sdma_softc *sdma_sc;
+	phandle_t node, sdma_node;
+	device_t sdma_dev;
+	int dts_value[8];
+	int len;
+
+	if ((node = ofw_bus_get_node(sc->dev)) == -1)
+		return (ENXIO);
+
+	if ((len = OF_getproplen(node, "dmas")) <= 0)
+		return (ENXIO);
+
+	OF_getprop(node, "dmas", &dts_value, len);
+
+	sc->sdma_ev_rx = fdt32_to_cpu(dts_value[1]);
+	sc->sdma_ev_tx = fdt32_to_cpu(dts_value[5]);
+
+	sdma_node = OF_node_from_xref(fdt32_to_cpu(dts_value[0]));
+
+	sdma_sc = NULL;
+
+	sdma_dev = devclass_get_device(devclass_find("sdma"), 0);
+	if (sdma_dev)
+		sdma_sc = device_get_softc(sdma_dev);
+
+	if (sdma_sc == NULL) {
+		device_printf(sc->dev, "No sDMA found. Can't operate\n");
+		return (ENXIO);
+	};
+
+	sc->sdma_sc = sdma_sc;
+
+	return (0);
+};
+
+static int
+setup_dma(struct sc_pcminfo *scp)
+{
+	struct sdma_conf *conf;
+	struct sc_chinfo *ch;
+	struct sc_info *sc;
+	int fmt;
+
+	ch = &scp->chan[0];
+	sc = scp->sc;
+	conf = sc->conf;
+
+	conf->ih = ssi_dma_intr;
+	conf->ih_user = scp;
+	conf->saddr = sc->buf_base_phys;
+	conf->daddr = rman_get_start(sc->res[0]) + SSI_STX0;
+	conf->event = sc->sdma_ev_tx; /* SDMA TX event */
+	conf->period = sndbuf_getblksz(ch->buffer);
+	conf->num_bd = sndbuf_getblkcnt(ch->buffer);
+
+	/*
+	 * Word Length
+	 * Can be 32, 24, 16 or 8 for sDMA.
+	 *
+	 * SSI supports 24 at max.
+	 */
+
+	fmt = sndbuf_getfmt(ch->buffer);
+
+	if (fmt & AFMT_16BIT) {
+		conf->word_length = 16;
+		conf->command = CMD_2BYTES;
+	} else if (fmt & AFMT_24BIT) {
+		conf->word_length = 24;
+		conf->command = CMD_3BYTES;
+	} else {
+		device_printf(sc->dev, "Unknown format\n");
+		return (-1);
+	}
+
+	return (0);
+}
+
+static int
+ssi_start(struct sc_pcminfo *scp)
+{
+	struct sc_info *sc;
+	int reg;
+
+	sc = scp->sc;
+
+	if (sdma_configure(sc->sdma_channel, sc->conf) != 0) {
+		device_printf(sc->dev, "Can't configure sDMA\n");
+		return (-1);
+	}
+
+	/* Enable DMA interrupt */
+	reg = (SIER_TDMAE);
+	WRITE4(sc, SSI_SIER, reg);
+
+	sdma_start(sc->sdma_channel);
+
+	return (0);
+}
+
+static int
+ssi_stop(struct sc_pcminfo *scp)
+{
+	struct sc_info *sc;
+	int reg;
+
+	sc = scp->sc;
+
+	reg = READ4(sc, SSI_SIER);
+	reg &= ~(SIER_TDMAE);
+	WRITE4(sc, SSI_SIER, reg);
+
+	sdma_stop(sc->sdma_channel);
+
+	bzero(sc->buf_base, sc->dma_size);
+
+	return (0);
+}
+
+static int
+ssichan_trigger(kobj_t obj, void *data, int go)
+{
+	struct sc_pcminfo *scp;
+	struct sc_chinfo *ch;
+	struct sc_info *sc;
+
+	ch = data;
+	scp = ch->parent;
+	sc = scp->sc;
+
+	snd_mtxlock(sc->lock);
+
+	switch (go) {
+	case PCMTRIG_START:
+#if 0
+		device_printf(scp->dev, "trigger start\n");
+#endif
+		ch->run = 1;
+
+		ssi_start(scp);
+
+		break;
+
+	case PCMTRIG_STOP:
+	case PCMTRIG_ABORT:
+#if 0
+		device_printf(scp->dev, "trigger stop or abort\n");
+#endif
+		ch->run = 0;
+
+		ssi_stop(scp);
+
+		break;
+	}
+
+	snd_mtxunlock(sc->lock);
+
+	return (0);
+}
+
+static uint32_t
+ssichan_getptr(kobj_t obj, void *data)
+{
+	struct sc_pcminfo *scp;
+	struct sc_chinfo *ch;
+	struct sc_info *sc;
+
+	ch = data;
+	scp = ch->parent;
+	sc = scp->sc;
+
+	return (sc->pos);
+}
+
+static uint32_t ssi_pfmt[] = {
+	SND_FORMAT(AFMT_S24_LE, 2, 0),
+	0
+};
+
+static struct pcmchan_caps ssi_pcaps = {44100, 192000, ssi_pfmt, 0};
+
+static struct pcmchan_caps *
+ssichan_getcaps(kobj_t obj, void *data)
+{
+
+	return (&ssi_pcaps);
+}
+
+static kobj_method_t ssichan_methods[] = {
+	KOBJMETHOD(channel_init,         ssichan_init),
+	KOBJMETHOD(channel_free,         ssichan_free),
+	KOBJMETHOD(channel_setformat,    ssichan_setformat),
+	KOBJMETHOD(channel_setspeed,     ssichan_setspeed),
+	KOBJMETHOD(channel_setblocksize, ssichan_setblocksize),
+	KOBJMETHOD(channel_trigger,      ssichan_trigger),
+	KOBJMETHOD(channel_getptr,       ssichan_getptr),
+	KOBJMETHOD(channel_getcaps,      ssichan_getcaps),
+	KOBJMETHOD_END
+};
+CHANNEL_DECLARE(ssichan);
+
+static int
+ssi_probe(device_t dev)
+{
+
+	if (!ofw_bus_status_okay(dev))
+		return (ENXIO);
+
+	if (!ofw_bus_is_compatible(dev, "fsl,imx6q-ssi"))
+		return (ENXIO);
+
+	device_set_desc(dev, "i.MX6 Synchronous Serial Interface (SSI)");
+	return (BUS_PROBE_DEFAULT);
+}
+
+static void
+ssi_intr(void *arg)
+{
+	struct sc_pcminfo *scp;
+	struct sc_chinfo *ch;
+	struct sc_info *sc;
+
+	scp = arg;
+	sc = scp->sc;
+	ch = &scp->chan[0];
+
+	/* We don't use SSI interrupt */
+#if 0
+	device_printf(sc->dev, "SSI Intr 0x%08x\n",
+	    READ4(sc, SSI_SISR));
+#endif
+}
+
+static void
+setup_ssi(struct sc_info *sc)
+{
+	int reg;
+
+	reg = READ4(sc, SSI_STCCR);
+	reg &= ~(WL3_WL0_M << WL3_WL0_S);
+	reg |= (0xb << WL3_WL0_S); /* 24 bit */
+	reg &= ~(DC4_DC0_M << DC4_DC0_S);
+	reg |= (1 << DC4_DC0_S); /* 2 words per frame */
+	reg &= ~(STCCR_DIV2); /* Divide by 1 */
+	reg &= ~(STCCR_PSR); /* Divide by 1 */
+	reg &= ~(PM7_PM0_M << PM7_PM0_S);
+	reg |= (1 << PM7_PM0_S); /* Divide by 2 */
+	WRITE4(sc, SSI_STCCR, reg);
+
+	reg = READ4(sc, SSI_SFCSR);
+	reg &= ~(SFCSR_TFWM0_M << SFCSR_TFWM0_S);
+	reg |= (8 << SFCSR_TFWM0_S); /* empty slots */
+	WRITE4(sc, SSI_SFCSR, reg);
+
+	reg = READ4(sc, SSI_STCR);
+	reg |= (STCR_TFEN0);
+	reg &= ~(STCR_TFEN1);
+	reg &= ~(STCR_TSHFD); /* MSB */
+	reg |= (STCR_TXBIT0);
+	reg |= (STCR_TXDIR | STCR_TFDIR);
+	reg |= (STCR_TSCKP); /* falling edge */
+	reg |= (STCR_TFSI);
+	reg &= ~(STCR_TFSI); /* active high frame sync */
+	reg &= ~(STCR_TFSL);
+	reg |= STCR_TEFS;
+	WRITE4(sc, SSI_STCR, reg);
+
+	reg = READ4(sc, SSI_SCR);
+	reg &= ~(SCR_I2S_MODE_M << SCR_I2S_MODE_S); /* Not master */
+	reg |= (SCR_SSIEN | SCR_TE);
+	reg |= (SCR_NET);
+	reg |= (SCR_SYN);
+	WRITE4(sc, SSI_SCR, reg);
+}
+
+static void
+ssi_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
+{
+	bus_addr_t *addr;
+
+	if (err)
+		return;
+
+	addr = (bus_addr_t*)arg;
+	*addr = segs[0].ds_addr;
+}
+
+static int
+ssi_attach(device_t dev)
+{
+	char status[SND_STATUSLEN];
+	struct sc_pcminfo *scp;
+	struct sc_info *sc;
+	int err;
+
+	sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
+	sc->dev = dev;
+	sc->sr = &rate_map[0];
+	sc->pos = 0;
+	sc->conf = malloc(sizeof(struct sdma_conf), M_DEVBUF, M_WAITOK | M_ZERO);
+
+	sc->lock = snd_mtxcreate(device_get_nameunit(dev), "ssi softc");
+	if (sc->lock == NULL) {
+		device_printf(dev, "Cant create mtx\n");
+		return (ENXIO);
+	}
+
+	if (bus_alloc_resources(dev, ssi_spec, sc->res)) {
+		device_printf(dev, "could not allocate resources\n");
+		return (ENXIO);
+	}
+
+	/* Memory interface */
+	sc->bst = rman_get_bustag(sc->res[0]);
+	sc->bsh = rman_get_bushandle(sc->res[0]);
+
+	/* SDMA */
+	if (find_sdma_controller(sc)) {
+		device_printf(dev, "could not find active SDMA\n");
+		return (ENXIO);
+	}
+
+	/* Setup PCM */
+	scp = malloc(sizeof(struct sc_pcminfo), M_DEVBUF, M_NOWAIT | M_ZERO);
+	scp->sc = sc;
+	scp->dev = dev;
+
+	/*
+	 * Maximum possible DMA buffer.
+	 * Will be used partialy to match 24 bit word.
+	 */
+	sc->dma_size = 131072;
+
+	/*
+	 * Must use dma_size boundary as modulo feature required.
+	 * Modulo feature allows setup circular buffer.
+	 */
+
+	err = bus_dma_tag_create(
+	    bus_get_dma_tag(sc->dev),
+	    4, sc->dma_size,		/* alignment, boundary */
+	    BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
+	    BUS_SPACE_MAXADDR,		/* highaddr */
+	    NULL, NULL,			/* filter, filterarg */
+	    sc->dma_size, 1,		/* maxsize, nsegments */
+	    sc->dma_size, 0,		/* maxsegsize, flags */
+	    NULL, NULL,			/* lockfunc, lockarg */
+	    &sc->dma_tag);
+
+	err = bus_dmamem_alloc(sc->dma_tag, (void **)&sc->buf_base,
+	    BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->dma_map);
+	if (err) {
+		device_printf(dev, "cannot allocate framebuffer\n");
+		return (ENXIO);
+	}
+
+	err = bus_dmamap_load(sc->dma_tag, sc->dma_map, sc->buf_base,
+	    sc->dma_size, ssi_dmamap_cb, &sc->buf_base_phys, BUS_DMA_NOWAIT);
+	if (err) {
+		device_printf(dev, "cannot load DMA map\n");
+		return (ENXIO);
+	}
+
+	bzero(sc->buf_base, sc->dma_size);
+
+	/* Setup interrupt handler */
+	err = bus_setup_intr(dev, sc->res[1], INTR_MPSAFE | INTR_TYPE_AV,
+	    NULL, ssi_intr, scp, &sc->ih);
+	if (err) {
+		device_printf(dev, "Unable to alloc interrupt resource.\n");
+		return (ENXIO);
+	}
+
+	pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE);
+
+	err = pcm_register(dev, scp, 1, 0);
+	if (err) {
+		device_printf(dev, "Can't register pcm.\n");
+		return (ENXIO);
+	}
+
+	scp->chnum = 0;
+	pcm_addchan(dev, PCMDIR_PLAY, &ssichan_class, scp);
+	scp->chnum++;
+
+	snprintf(status, SND_STATUSLEN, "at simplebus");
+	pcm_setstatus(dev, status);
+
+	mixer_init(dev, &ssimixer_class, scp);
+	setup_ssi(sc);
+
+	imx_ccm_ssi_configure(dev);
+
+	sc->sdma_channel = sdma_alloc();
+	if (sc->sdma_channel < 0) {
+		device_printf(sc->dev, "Can't get sDMA channel\n");
+		return (1);
+	}
+
+	return (0);
+}
+
+static device_method_t ssi_pcm_methods[] = {
+	DEVMETHOD(device_probe,		ssi_probe),
+	DEVMETHOD(device_attach,	ssi_attach),
+	{ 0, 0 }
+};
+
+static driver_t ssi_pcm_driver = {
+	"pcm",
+	ssi_pcm_methods,
+	PCM_SOFTC_SIZE,
+};
+
+DRIVER_MODULE(ssi, simplebus, ssi_pcm_driver, pcm_devclass, 0, 0);
+MODULE_DEPEND(ssi, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
+MODULE_VERSION(ssi, 1);
diff --git a/sys/arm/freescale/imx/imx_ccmvar.h b/sys/arm/freescale/imx/imx_ccmvar.h
index 354e616..f159437 100644
--- a/sys/arm/freescale/imx/imx_ccmvar.h
+++ b/sys/arm/freescale/imx/imx_ccmvar.h
@@ -51,5 +51,6 @@ uint32_t imx_ccm_ahb_hz(void);
 
 void imx_ccm_usb_enable(device_t _usbdev);
 void imx_ccm_usbphy_enable(device_t _phydev);
+void imx_ccm_ssi_configure(device_t _ssidev);
 
 #endif