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| author | ian <ian@FreeBSD.org> | 2015-05-23 17:30:30 +0000 |
|---|---|---|
| committer | ian <ian@FreeBSD.org> | 2015-05-23 17:30:30 +0000 |
| commit | c063f629c5b85ca49413bf3486cf9b5263bbacb8 (patch) | |
| tree | 4fac85e9ad096f7172763c59e94eb2d7a04318d0 /sys/arm | |
| parent | 26d3f673f7e5ee199b1670f9fe60f725d5ccd4b8 (diff) | |
| download | FreeBSD-src-c063f629c5b85ca49413bf3486cf9b5263bbacb8.zip FreeBSD-src-c063f629c5b85ca49413bf3486cf9b5263bbacb8.tar.gz | |
MFC r278770, r279114, r279215, r279338, r279543:
Add logic for handling new-style ARM cpu ID info.
Correct a comment which was exactly backwards from reality.
There is no reason to do i+dcache writeback and invalidate when changing
the translation table (this may be left over from armv5 days). It's
especially bad to do so using a cache operation that isn't coherent on
SMP systems.
Add casting to make atomic ops work for pointers. (Apparently nobody has
ever done atomic ops on pointers before now on arm).
Revert incorrect casting.
Diffstat (limited to 'sys/arm')
| -rw-r--r-- | sys/arm/arm/cpufunc_asm_armv7.S | 4 | ||||
| -rw-r--r-- | sys/arm/arm/cpuinfo.c | 8 | ||||
| -rw-r--r-- | sys/arm/include/atomic.h | 4 |
3 files changed, 8 insertions, 8 deletions
diff --git a/sys/arm/arm/cpufunc_asm_armv7.S b/sys/arm/arm/cpufunc_asm_armv7.S index 9fe6aa5..5d6907e 100644 --- a/sys/arm/arm/cpufunc_asm_armv7.S +++ b/sys/arm/arm/cpufunc_asm_armv7.S @@ -66,11 +66,7 @@ __FBSDID("$FreeBSD$"); #endif ENTRY(armv7_setttb) - stmdb sp!, {r0, lr} - bl _C_LABEL(armv7_idcache_wbinv_all) /* clean the D cache */ - ldmia sp!, {r0, lr} dsb - orr r0, r0, #PT_ATTR mcr CP15_TTBR0(r0) isb diff --git a/sys/arm/arm/cpuinfo.c b/sys/arm/arm/cpuinfo.c index d20c561..b0b8a88 100644 --- a/sys/arm/arm/cpuinfo.c +++ b/sys/arm/arm/cpuinfo.c @@ -58,9 +58,13 @@ cpuinfo_init(void) /* ARMv4T CPU */ cpuinfo.architecture = 1; cpuinfo.revision = (cpuinfo.midr >> 16) & 0x7F; - } + } else { + /* ARM new id scheme */ + cpuinfo.architecture = (cpuinfo.midr >> 16) & 0x0F; + cpuinfo.revision = (cpuinfo.midr >> 20) & 0x0F; + } } else { - /* must be new id scheme */ + /* non ARM -> must be new id scheme */ cpuinfo.architecture = (cpuinfo.midr >> 16) & 0x0F; cpuinfo.revision = (cpuinfo.midr >> 20) & 0x0F; } diff --git a/sys/arm/include/atomic.h b/sys/arm/include/atomic.h index 5857f5d..57fdf71 100644 --- a/sys/arm/include/atomic.h +++ b/sys/arm/include/atomic.h @@ -582,8 +582,8 @@ atomic_load_64(volatile uint64_t *p) /* * The only way to atomically load 64 bits is with LDREXD which puts the - * exclusive monitor into the open state, so reset it with CLREX because - * we don't actually need to store anything. + * exclusive monitor into the exclusive state, so reset it to open state + * with CLREX because we don't actually need to store anything. */ __asm __volatile( "1: \n" |
