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author | ian <ian@FreeBSD.org> | 2013-12-14 01:12:13 +0000 |
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committer | ian <ian@FreeBSD.org> | 2013-12-14 01:12:13 +0000 |
commit | b37938a4e4173ecd46aa46bb293aad3f58baefbe (patch) | |
tree | 40c74e56c766046a52593f13e5e4e4e0b0aab04c /sys/arm | |
parent | 1185e669672b4edbb49d44b2c876c995baf12a7d (diff) | |
download | FreeBSD-src-b37938a4e4173ecd46aa46bb293aad3f58baefbe.zip FreeBSD-src-b37938a4e4173ecd46aa46bb293aad3f58baefbe.tar.gz |
MFC r258392, r258412:
Call cpu_setup() immediately after the page tables are installed. This
enables data cache and other chip-specific features. It was previously
done via an early SYSINIT, but it was being done after pmap and vm setup,
and those setups need to use mutexes. On some modern ARM platforms,
the ldrex/strex instructions that implement mutexes require the data cache
to be enabled.
Call cpu_setup() from the initarm() routine on platforms that don't use
the common FDT-aware initarm() in arm/machdep.c.
Diffstat (limited to 'sys/arm')
-rw-r--r-- | sys/arm/arm/machdep.c | 7 | ||||
-rw-r--r-- | sys/arm/at91/at91_machdep.c | 1 | ||||
-rw-r--r-- | sys/arm/econa/econa_machdep.c | 1 | ||||
-rw-r--r-- | sys/arm/s3c2xx0/s3c24x0_machdep.c | 1 | ||||
-rw-r--r-- | sys/arm/sa11x0/assabet_machdep.c | 1 | ||||
-rw-r--r-- | sys/arm/xscale/i80321/ep80219_machdep.c | 2 | ||||
-rw-r--r-- | sys/arm/xscale/i80321/iq31244_machdep.c | 2 | ||||
-rw-r--r-- | sys/arm/xscale/i8134x/crb_machdep.c | 2 | ||||
-rw-r--r-- | sys/arm/xscale/ixp425/avila_machdep.c | 2 | ||||
-rw-r--r-- | sys/arm/xscale/pxa/pxa_machdep.c | 1 |
10 files changed, 19 insertions, 1 deletions
diff --git a/sys/arm/arm/machdep.c b/sys/arm/arm/machdep.c index 7348fc2..2b46656 100644 --- a/sys/arm/arm/machdep.c +++ b/sys/arm/arm/machdep.c @@ -361,7 +361,6 @@ cpu_startup(void *dummy) #endif #endif - cpu_setup(""); identify_arm_cpu(); printf("real memory = %ju (%ju MB)\n", (uintmax_t)ptoa(physmem), @@ -1427,6 +1426,12 @@ initarm(struct arm_boot_params *abp) cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)); /* + * Now that proper page tables are installed, call cpu_setup() to enable + * instruction and data caches and other chip-specific features. + */ + cpu_setup(""); + + /* * Only after the SOC registers block is mapped we can perform device * tree fixups, as they may attempt to read parameters from hardware. */ diff --git a/sys/arm/at91/at91_machdep.c b/sys/arm/at91/at91_machdep.c index f7c21f9..32fa129 100644 --- a/sys/arm/at91/at91_machdep.c +++ b/sys/arm/at91/at91_machdep.c @@ -604,6 +604,7 @@ initarm(struct arm_boot_params *abp) * of the stack memory. */ cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE); + cpu_setup(""); set_stackptrs(0); diff --git a/sys/arm/econa/econa_machdep.c b/sys/arm/econa/econa_machdep.c index 0323e7b..04fd208 100644 --- a/sys/arm/econa/econa_machdep.c +++ b/sys/arm/econa/econa_machdep.c @@ -309,6 +309,7 @@ initarm(struct arm_boot_params *abp) * this problem will not occur after initarm(). */ cpu_idcache_wbinv_all(); + cpu_setup(""); /* Set stack for exception handlers */ data_abort_handler_address = (u_int)data_abort_handler; diff --git a/sys/arm/s3c2xx0/s3c24x0_machdep.c b/sys/arm/s3c2xx0/s3c24x0_machdep.c index 3fc0f8e..8f432be 100644 --- a/sys/arm/s3c2xx0/s3c24x0_machdep.c +++ b/sys/arm/s3c2xx0/s3c24x0_machdep.c @@ -355,6 +355,7 @@ initarm(struct arm_boot_params *abp) * this problem will not occur after initarm(). */ cpu_idcache_wbinv_all(); + cpu_setup(""); /* Disable all peripheral interrupts */ ioreg_write32(S3C24X0_INTCTL_BASE + INTCTL_INTMSK, ~0); diff --git a/sys/arm/sa11x0/assabet_machdep.c b/sys/arm/sa11x0/assabet_machdep.c index 79014f2..56b0f30 100644 --- a/sys/arm/sa11x0/assabet_machdep.c +++ b/sys/arm/sa11x0/assabet_machdep.c @@ -371,6 +371,7 @@ initarm(struct arm_boot_params *abp) cpufunc_control(0x337f, 0x107d); arm_vector_init(ARM_VECTORS_LOW, ARM_VEC_ALL); + cpu_setup(""); pmap_curmaxkvaddr = freemempos + KERNEL_PT_VMDATA_NUM * 0x400000; diff --git a/sys/arm/xscale/i80321/ep80219_machdep.c b/sys/arm/xscale/i80321/ep80219_machdep.c index 94b94da..4857fcd 100644 --- a/sys/arm/xscale/i80321/ep80219_machdep.c +++ b/sys/arm/xscale/i80321/ep80219_machdep.c @@ -334,6 +334,8 @@ initarm(struct arm_boot_params *abp) * this problem will not occur after initarm(). */ cpu_idcache_wbinv_all(); + cpu_setup(""); + /* * Fetch the SDRAM start/size from the i80321 SDRAM configration * registers. diff --git a/sys/arm/xscale/i80321/iq31244_machdep.c b/sys/arm/xscale/i80321/iq31244_machdep.c index f1f9128..e706280 100644 --- a/sys/arm/xscale/i80321/iq31244_machdep.c +++ b/sys/arm/xscale/i80321/iq31244_machdep.c @@ -335,6 +335,8 @@ initarm(struct arm_boot_params *abp) * this problem will not occur after initarm(). */ cpu_idcache_wbinv_all(); + cpu_setup(""); + /* * Fetch the SDRAM start/size from the i80321 SDRAM configration * registers. diff --git a/sys/arm/xscale/i8134x/crb_machdep.c b/sys/arm/xscale/i8134x/crb_machdep.c index 6b56290..5bc6c10 100644 --- a/sys/arm/xscale/i8134x/crb_machdep.c +++ b/sys/arm/xscale/i8134x/crb_machdep.c @@ -320,6 +320,8 @@ initarm(struct arm_boot_params *abp) * this problem will not occur after initarm(). */ cpu_idcache_wbinv_all(); + cpu_setup(""); + i80321_calibrate_delay(); i81342_sdram_bounds(&obio_bs_tag, IOP34X_VADDR, &memstart, &memsize); physmem = memsize / PAGE_SIZE; diff --git a/sys/arm/xscale/ixp425/avila_machdep.c b/sys/arm/xscale/ixp425/avila_machdep.c index 825ccb5..11a29a8 100644 --- a/sys/arm/xscale/ixp425/avila_machdep.c +++ b/sys/arm/xscale/ixp425/avila_machdep.c @@ -405,6 +405,8 @@ initarm(struct arm_boot_params *abp) * this problem will not occur after initarm(). */ cpu_idcache_wbinv_all(); + cpu_setup(""); + /* ready to setup the console (XXX move earlier if possible) */ cninit(); /* diff --git a/sys/arm/xscale/pxa/pxa_machdep.c b/sys/arm/xscale/pxa/pxa_machdep.c index b3c32e0..0843088 100644 --- a/sys/arm/xscale/pxa/pxa_machdep.c +++ b/sys/arm/xscale/pxa/pxa_machdep.c @@ -317,6 +317,7 @@ initarm(struct arm_boot_params *abp) * this problem will not occur after initarm(). */ cpu_idcache_wbinv_all(); + cpu_setup(""); /* * Sort out bus_space for on-board devices. |