MFC r269607, r269698:

  Cache the imx6 SoC type in a static var so that it only has to be figured
  out by sniffing hardware registers once.

  Add a missing clock register definition.

2 files changed, 15 insertions, 5 deletions

diff --git a/sys/arm/freescale/imx/imx6_ccmreg.h b/sys/arm/freescale/imx/imx6_ccmreg.h
index 9cb7acc..d50c190 100644
--- a/sys/arm/freescale/imx/imx6_ccmreg.h
+++ b/sys/arm/freescale/imx/imx6_ccmreg.h
@@ -36,6 +36,7 @@
 #define	  CCM_CLPCR_LPM_STOP		  0x02
 #define	CCM_CGPR			0x064
 #define	  CCM_CGPR_INT_MEM_CLK_LPM	  (1 << 17)
+#define	CCM_CCGR0			0x068
 #define	CCM_CCGR1			0x06C
 #define	CCM_CCGR2			0x070
 #define	CCM_CCGR3			0x074
diff --git a/sys/arm/freescale/imx/imx6_machdep.c b/sys/arm/freescale/imx/imx6_machdep.c
index c1074d0..3a01cd8 100644
--- a/sys/arm/freescale/imx/imx6_machdep.c
+++ b/sys/arm/freescale/imx/imx6_machdep.c
@@ -145,12 +145,16 @@ u_int imx_soc_type()
 {
 	uint32_t digprog, hwsoc;
 	uint32_t *pcr;
+	static u_int soctype;
 	const vm_offset_t SCU_CONFIG_PHYSADDR = 0x00a00004;
 #define	HWSOC_MX6SL	0x60
 #define	HWSOC_MX6DL	0x61
 #define	HWSOC_MX6SOLO	0x62
 #define	HWSOC_MX6Q	0x63
 
+	if (soctype != 0)
+		return (soctype);
+
 	digprog = imx6_anatop_read_4(IMX6_ANALOG_DIGPROG_SL);
 	hwsoc = (digprog >> IMX6_ANALOG_DIGPROG_SOCTYPE_SHIFT) & 
 	    IMX6_ANALOG_DIGPROG_SOCTYPE_MASK;
@@ -174,20 +178,25 @@ u_int imx_soc_type()
 
 	switch (hwsoc) {
 	case HWSOC_MX6SL:
-		return (IMXSOC_6SL);
+		soctype = IMXSOC_6SL;
+		break;
 	case HWSOC_MX6SOLO:
-		return (IMXSOC_6S);
+		soctype = IMXSOC_6S;
+		break;
 	case HWSOC_MX6DL:
-		return (IMXSOC_6DL);
+		soctype = IMXSOC_6DL;
+		break;
 	case HWSOC_MX6Q :
-		return (IMXSOC_6Q);
+		soctype = IMXSOC_6Q;
+		break;
 	default:
 		printf("imx_soc_type: Don't understand hwsoc 0x%02x, "
 		    "digprog 0x%08x; assuming IMXSOC_6Q\n", hwsoc, digprog);
+		soctype = IMXSOC_6Q;
 		break;
 	}
 
-	return (IMXSOC_6Q);
+	return (soctype);
 }
 
 /*