Identify the xscale 81342.

6 files changed, 117 insertions, 11 deletions

diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c
index 46b0997..52f1abf 100644
--- a/sys/arm/arm/cpufunc.c
+++ b/sys/arm/arm/cpufunc.c
@@ -73,13 +73,17 @@ __FBSDID("$FreeBSD$");
 #include <arm/xscale/i80321/i80321var.h>
 #endif
 
+#if defined(CPU_XSCALE_81342)
+#include <arm/xscale/i8134x/i81342reg.h>
+#endif
+
 #ifdef CPU_XSCALE_IXP425
 #include <arm/xscale/ixp425/ixp425reg.h>
 #include <arm/xscale/ixp425/ixp425var.h>
 #endif
 
 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
-    defined(CPU_XSCALE_80219)
+    defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
 #include <arm/xscale/xscalereg.h>
 #endif
 
@@ -570,6 +574,62 @@ struct cpu_functions xscale_cpufuncs = {
 /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425
    CPU_XSCALE_80219 */
 
+#ifdef CPU_XSCALE_81342
+struct cpu_functions xscalec3_cpufuncs = {
+	/* CPU functions */
+	
+	cpufunc_id,			/* id			*/
+	xscale_cpwait,			/* cpwait		*/
+
+	/* MMU functions */
+
+	xscale_control,			/* control		*/
+	cpufunc_domains,		/* domain		*/
+	xscalec3_setttb,		/* setttb		*/
+	cpufunc_faultstatus,		/* faultstatus		*/
+	cpufunc_faultaddress,		/* faultaddress		*/
+
+	/* TLB functions */
+
+	armv4_tlb_flushID,		/* tlb_flushID		*/
+	xscale_tlb_flushID_SE,		/* tlb_flushID_SE	*/
+	armv4_tlb_flushI,		/* tlb_flushI		*/
+	(void *)armv4_tlb_flushI,	/* tlb_flushI_SE	*/
+	armv4_tlb_flushD,		/* tlb_flushD		*/
+	armv4_tlb_flushD_SE,		/* tlb_flushD_SE	*/
+
+	/* Cache operations */
+
+	xscalec3_cache_syncI,		/* icache_sync_all	*/
+	xscale_cache_syncI_rng,		/* icache_sync_range	*/
+
+	xscalec3_cache_purgeD,		/* dcache_wbinv_all	*/
+	xscalec3_cache_purgeD_rng,	/* dcache_wbinv_range	*/
+	xscale_cache_flushD_rng,	/* dcache_inv_range	*/
+	xscalec3_cache_cleanD_rng,	/* dcache_wb_range	*/
+
+	xscalec3_cache_purgeID,	/* idcache_wbinv_all	*/
+	xscalec3_cache_purgeID_rng,	/* idcache_wbinv_range	*/
+
+	/* Other functions */
+
+	cpufunc_nullop,			/* flush_prefetchbuf	*/
+	armv4_drain_writebuf,		/* drain_writebuf	*/
+	cpufunc_nullop,			/* flush_brnchtgt_C	*/
+	(void *)cpufunc_nullop,		/* flush_brnchtgt_E	*/
+
+	xscale_cpu_sleep,		/* sleep		*/
+
+	/* Soft functions */
+
+	cpufunc_null_fixup,		/* dataabt_fixup	*/
+	cpufunc_null_fixup,		/* prefetchabt_fixup	*/
+
+	xscalec3_context_switch,	/* context_switch	*/
+
+	xscale_setup			/* cpu setup		*/
+};
+#endif /* CPU_XSCALE_81342 */
 /*
  * Global constants also used by locore.s
  */
@@ -582,7 +642,7 @@ u_int cpu_reset_needs_v4_MMU_disable;	/* flag used in locore.s */
   defined (CPU_ARM10) ||					       \
   defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) ||	       \
   defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) ||	       \
-  defined(CPU_XSCALE_80219)
+  defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
 
 static void get_cachetype_cp15(void);
 
@@ -895,7 +955,6 @@ set_cpufuncs()
 	if (cputype == CPU_ID_80321_400 || cputype == CPU_ID_80321_600 ||
 	    cputype == CPU_ID_80321_400_B0 || cputype == CPU_ID_80321_600_B0 ||
 	    cputype == CPU_ID_80219_400 || cputype == CPU_ID_80219_600) {
-
 		/*
 		 * Reset the Performance Monitoring Unit to a
 		 * pristine state:
@@ -920,6 +979,19 @@ set_cpufuncs()
 	}
 #endif /* CPU_XSCALE_80321 */
 
+#if defined(CPU_XSCALE_81342)
+	if (cputype == CPU_ID_81342) {
+		cpufuncs = xscalec3_cpufuncs;
+#if defined(PERFCTRS)
+		xscale_pmu_init();
+#endif
+
+		cpu_reset_needs_v4_MMU_disable = 1;	/* XScale needs it */
+		get_cachetype_cp15();
+		pmap_pte_init_xscale();
+		return 0;
+	}
+#endif /* CPU_XSCALE_81342 */
 #ifdef CPU_XSCALE_PXA2X0
 	/* ignore core revision to test PXA2xx CPUs */
 	if ((cputype & ~CPU_ID_XSCALE_COREREV_MASK) == CPU_ID_PXA250 ||
@@ -1326,7 +1398,7 @@ late_abort_fixup(arg)
   defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) ||	\
   defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) ||		\
   defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) ||		\
-  defined(CPU_XSCALE_80219)
+  defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
 
 #define IGN	0
 #define OR	1
@@ -1794,7 +1866,7 @@ ixp12x0_setup(args)
 
 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
   defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
-  defined(CPU_XSCALE_80219)
+  defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
 struct cpu_option xscale_options[] = {
 #ifdef COMPAT_12
 	{ "branchpredict", 	BIC, OR,  CPU_CONTROL_BPRD_ENABLE },
diff --git a/sys/arm/arm/identcpu.c b/sys/arm/arm/identcpu.c
index 9973555..0a3e7a1 100644
--- a/sys/arm/arm/identcpu.c
+++ b/sys/arm/arm/identcpu.c
@@ -126,6 +126,13 @@ static const char * const i80321_steppings[16] = {
 	"rev 12",	"rev 13",	"rev 14",	"rev 15",
 };
 
+static const char * const i81342_steppings[16] = {
+	"step A-0",	"rev 1",	"rev 2",	"rev 3",
+	"rev 4",	"rev 5",	"rev 6",	"rev 7",
+	"rev 8",	"rev 9",	"rev 10",	"rev 11",
+	"rev 12",	"rev 13",	"rev 14",	"rev 15",
+};
+
 static const char * const pxa2x0_steppings[16] = {
 	"step A-0",	"step A-1",	"step B-0",	"step B-1",
 	"step B-2",	"step C-0",	"rev 6",	"rev 7",
@@ -229,6 +236,9 @@ const struct cpuidtab cpuids[] = {
 	{ CPU_ID_80321_600_B0,	CPU_CLASS_XSCALE,	"i80321 600MHz",
 	  i80321_steppings },
 
+	{ CPU_ID_81342,		CPU_CLASS_XSCALE,	"i81342",
+	  i81342_steppings },
+
 	{ CPU_ID_80219_400,	CPU_CLASS_XSCALE,	"i80219 400MHz",
 	  xscale_steppings },
 	
diff --git a/sys/arm/include/armreg.h b/sys/arm/include/armreg.h
index 9c0af80..82b69e9 100644
--- a/sys/arm/include/armreg.h
+++ b/sys/arm/include/armreg.h
@@ -157,6 +157,7 @@
 #define	CPU_ID_80321_600_B0	0x69052c30
 #define	CPU_ID_80219_400	0x69052e20 /* A0 stepping/revision. */
 #define	CPU_ID_80219_600	0x69052e30 /* A0 stepping/revision. */
+#define	CPU_ID_81342		0x69056810
 #define	CPU_ID_IXP425_533	0x690541c0
 #define	CPU_ID_IXP425_400	0x690541d0
 #define	CPU_ID_IXP425_266	0x690541f0
diff --git a/sys/arm/include/cpuconf.h b/sys/arm/include/cpuconf.h
index 143179e..88990f5 100644
--- a/sys/arm/include/cpuconf.h
+++ b/sys/arm/include/cpuconf.h
@@ -64,7 +64,8 @@
 #define	ARM_ARCH_4	0
 #endif
 
-#if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || defined(CPU_XSCALE_80219) || \
+#if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
+    defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \
      defined(CPU_XSCALE_PXA2X0)) || defined(CPU_ARM10)
 #define	ARM_ARCH_5	1
 #else
@@ -113,7 +114,7 @@
 
 #if(defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) ||		\
     defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) ||		\
-    defined(CPU_XSCALE_80219))
+    defined(CPU_XSCALE_80219)) || defined(CPU_XSCALE_81342)
 #define	ARM_MMU_XSCALE		1
 #else
 #define	ARM_MMU_XSCALE		0
@@ -132,7 +133,7 @@
  */
 
 #if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
-     defined(CPU_XSCALE_80219))
+     defined(CPU_XSCALE_80219)) || defined(CPU_XSCALE_81342)
 #define ARM_XSCALE_PMU	1
 #else
 #define ARM_XSCALE_PMU	0
diff --git a/sys/arm/include/cpufunc.h b/sys/arm/include/cpufunc.h
index 9686aa2..35387de 100644
--- a/sys/arm/include/cpufunc.h
+++ b/sys/arm/include/cpufunc.h
@@ -374,7 +374,7 @@ extern unsigned arm10_dcache_index_inc;
   defined(CPU_SA1100) || defined(CPU_SA1110) ||			     \
   defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) ||	     \
   defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) ||	     \
-  defined(CPU_XSCALE_80219)
+  defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
   
 void	armv4_tlb_flushID	(void);
 void	armv4_tlb_flushI	(void);
@@ -392,7 +392,7 @@ void	ixp12x0_setup		(char *string);
 
 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) ||	\
   defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) ||	\
-  defined(CPU_XSCALE_80219)
+  defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
 void	xscale_cpwait		(void);
 
 void	xscale_cpu_sleep	(int mode);
@@ -433,6 +433,28 @@ void	xscale_setup		(char *string);
 #endif	/* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 
 	   CPU_XSCALE_80219 */
 
+#ifdef	CPU_XSCALE_81342
+
+void	xscalec3_cache_cleanID	(void);
+void	xscalec3_cache_cleanD	(void);
+
+void	xscalec3_cache_purgeID	(void);
+void	xscalec3_cache_purgeID_E	(u_int entry);
+void	xscalec3_cache_purgeD	(void);
+void	xscalec3_cache_purgeD_E	(u_int entry);
+
+void	xscalec3_cache_syncI	(void);
+void	xscalec3_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
+void	xscalec3_cache_cleanD_rng	(vm_offset_t start, vm_size_t end);
+void	xscalec3_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
+void	xscalec3_cache_purgeD_rng	(vm_offset_t start, vm_size_t end);
+
+
+void	xscalec3_setttb		(u_int ttb);
+void	xscalec3_context_switch	(void);
+
+#endif /* CPU_XSCALE_81342 */
+
 #define tlb_flush	cpu_tlb_flushID
 #define setttb		cpu_setttb
 #define drain_writebuf	cpu_drain_writebuf
diff --git a/sys/arm/include/pmap.h b/sys/arm/include/pmap.h
index cb45c88..a3093a3 100644
--- a/sys/arm/include/pmap.h
+++ b/sys/arm/include/pmap.h
@@ -426,7 +426,7 @@ extern pt_entry_t		pte_l2_s_proto;
 extern void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t);
 extern void (*pmap_zero_page_func)(vm_paddr_t, int, int);
 
-#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
+#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_81342)
 void	pmap_copy_page_generic(vm_paddr_t, vm_paddr_t);
 void	pmap_zero_page_generic(vm_paddr_t, int, int);