MFC r268633, r271046:

  Fixes and enhancements for the if_cgem driver...

  - miibus fixes as suggested by Yonghyeon Pyun.
  - enable VLAN MTU support.
  - fix a few WITNESS complaints in cgem_attach().
  - have cgem_attach() properly init the ifnet struct before calling
    mii_attach() to fix panic when using e1000phy.
  - fix ethernet address changing.
  - fix transmit queue overflow handling.
  - tweak receive queue handling to reduce receive overflows.
  - bring out MAC statistic counters to sysctls.
  - add e1000phy to config file.
  - implement receive hang work-around described in reference guide.
  - change device name from if_cgem to cgem to be consistent with other
    interfaces.

  Fix the Zedboard/Zynq ethernet driver to handle media speed changes so
  that it can connect to switches at speeds other than 1gb.

4 files changed, 137 insertions, 5 deletions

diff --git a/sys/arm/conf/ZEDBOARD b/sys/arm/conf/ZEDBOARD
index 9b079af..c391af4 100644
--- a/sys/arm/conf/ZEDBOARD
+++ b/sys/arm/conf/ZEDBOARD
@@ -72,8 +72,9 @@ options 	KDB
 device		loop
 device		random
 device		ether
-device		if_cgem			# Zynq-7000 gig ethernet device
+device		cgem			# Zynq-7000 gig ethernet device
 device		mii
+device		e1000phy
 device		pty
 device		uart
 device		gpio
diff --git a/sys/arm/xilinx/files.zynq7 b/sys/arm/xilinx/files.zynq7
index 0407ecb..4caf90a 100644
--- a/sys/arm/xilinx/files.zynq7
+++ b/sys/arm/xilinx/files.zynq7
@@ -23,7 +23,7 @@ arm/xilinx/zy7_slcr.c				standard
 arm/xilinx/zy7_devcfg.c				standard
 arm/xilinx/zy7_mp.c				optional smp
 
-dev/cadence/if_cgem.c				optional if_cgem
+dev/cadence/if_cgem.c				optional cgem
 dev/sdhci/sdhci_fdt.c				optional sdhci
 arm/xilinx/zy7_ehci.c 				optional ehci
 arm/xilinx/uart_dev_cdnc.c			optional uart
diff --git a/sys/arm/xilinx/zy7_slcr.c b/sys/arm/xilinx/zy7_slcr.c
index e448d76..5dc15d1 100644
--- a/sys/arm/xilinx/zy7_slcr.c
+++ b/sys/arm/xilinx/zy7_slcr.c
@@ -71,12 +71,14 @@ extern void (*zynq7_cpu_reset);
 #define	ZSLCR_UNLOCK(sc)		mtx_unlock(&(sc)->sc_mtx)
 #define ZSLCR_LOCK_INIT(sc) \
 	mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev),	\
-	    "zy7_slcr", MTX_SPIN)
+	    "zy7_slcr", MTX_DEF)
 #define ZSLCR_LOCK_DESTROY(_sc)	mtx_destroy(&_sc->sc_mtx);
 
 #define RD4(sc, off) 		(bus_read_4((sc)->mem_res, (off)))
 #define WR4(sc, off, val) 	(bus_write_4((sc)->mem_res, (off), (val)))
 
+#define ZYNQ_DEFAULT_PS_CLK_FREQUENCY	33333333	/* 33.3 Mhz */
+
 
 SYSCTL_NODE(_hw, OID_AUTO, zynq, CTLFLAG_RD, 0, "Xilinx Zynq-7000");
 
@@ -84,7 +86,7 @@ static char zynq_bootmode[64];
 SYSCTL_STRING(_hw_zynq, OID_AUTO, bootmode, CTLFLAG_RD, zynq_bootmode, 0,
 	      "Zynq boot mode");
 
-static char zynq_pssid[80];
+static char zynq_pssid[100];
 SYSCTL_STRING(_hw_zynq, OID_AUTO, pssid, CTLFLAG_RD, zynq_pssid, 0,
 	   "Zynq PSS IDCODE");
 
@@ -92,6 +94,22 @@ static uint32_t zynq_reboot_status;
 SYSCTL_INT(_hw_zynq, OID_AUTO, reboot_status, CTLFLAG_RD, &zynq_reboot_status,
 	   0, "Zynq REBOOT_STATUS register");
 
+static int ps_clk_frequency;
+SYSCTL_INT(_hw_zynq, OID_AUTO, ps_clk_frequency, CTLFLAG_RD, &ps_clk_frequency,
+	   0, "Zynq PS_CLK Frequency");
+
+static int io_pll_frequency;
+SYSCTL_INT(_hw_zynq, OID_AUTO, io_pll_frequency, CTLFLAG_RD, &io_pll_frequency,
+	   0, "Zynq IO PLL Frequency");
+
+static int arm_pll_frequency;
+SYSCTL_INT(_hw_zynq, OID_AUTO, arm_pll_frequency, CTLFLAG_RD,
+	   &arm_pll_frequency, 0, "Zynq ARM PLL Frequency");
+
+static int ddr_pll_frequency;
+SYSCTL_INT(_hw_zynq, OID_AUTO, ddr_pll_frequency, CTLFLAG_RD,
+	   &ddr_pll_frequency, 0, "Zynq DDR PLL Frequency");
+
 static void
 zy7_slcr_unlock(struct zy7_slcr_softc *sc)
 {
@@ -189,6 +207,54 @@ zy7_slcr_postload_pl(int en_level_shifters)
 	ZSLCR_UNLOCK(sc);
 }
 
+/* Override cgem_set_refclk() in gigabit ethernet driver
+ * (sys/dev/cadence/if_cgem.c).  This function is called to
+ * request a change in the gem's reference clock speed.
+ */
+int
+cgem_set_ref_clk(int unit, int frequency)
+{
+	struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
+	int div0, div1;
+
+	if (!sc)
+		return (-1);
+
+	/* Find suitable divisor pairs.  Round result to nearest khz
+	 * to test for match.
+	 */
+	for (div1 = 1; div1 <= ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX; div1++) {
+		div0 = (io_pll_frequency + div1 * frequency / 2) /
+			div1 / frequency;
+		if (div0 > 0 && div0 <= ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_MAX &&
+		    ((io_pll_frequency / div0 / div1) + 500) / 1000 ==
+		    (frequency + 500) / 1000)
+			break;
+	}
+
+	if (div1 > ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX)
+		return (-1);
+
+	ZSLCR_LOCK(sc);
+
+	/* Unlock SLCR registers. */
+	zy7_slcr_unlock(sc);
+
+	/* Modify GEM reference clock. */
+	WR4(sc, unit ? ZY7_SLCR_GEM1_CLK_CTRL : ZY7_SLCR_GEM0_CLK_CTRL,
+	    (div1 << ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_SHIFT) |
+	    (div0 << ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_SHIFT) |
+	    ZY7_SLCR_GEM_CLK_CTRL_SRCSEL_IO_PLL |
+	    ZY7_SLCR_GEM_CLK_CTRL_CLKACT);
+
+	/* Lock SLCR registers. */
+	zy7_slcr_lock(sc);
+
+	ZSLCR_UNLOCK(sc);
+
+	return (0);
+}
+
 static int
 zy7_slcr_probe(device_t dev)
 {
@@ -208,8 +274,13 @@ zy7_slcr_attach(device_t dev)
 {
 	struct zy7_slcr_softc *sc = device_get_softc(dev);
 	int rid;
+	phandle_t node;
+	pcell_t cell;
 	uint32_t bootmode;
 	uint32_t pss_idcode;
+	uint32_t arm_pll_ctrl;
+	uint32_t ddr_pll_ctrl;
+	uint32_t io_pll_ctrl;
 	static char *bootdev_names[] = {
 		"JTAG", "Quad-SPI", "NOR", "(3?)",
 		"NAND", "SD Card", "(6?)", "(7?)"
@@ -260,6 +331,53 @@ zy7_slcr_attach(device_t dev)
 
 	zynq_reboot_status = RD4(sc, ZY7_SLCR_REBOOT_STAT);
 
+	/* Derive PLL frequencies from PS_CLK. */
+	node = ofw_bus_get_node(dev);
+	if (OF_getprop(node, "clock-frequency", &cell, sizeof(cell)) > 0)
+		ps_clk_frequency = fdt32_to_cpu(cell);
+	else
+		ps_clk_frequency = ZYNQ_DEFAULT_PS_CLK_FREQUENCY;
+
+	arm_pll_ctrl = RD4(sc, ZY7_SLCR_ARM_PLL_CTRL);
+	ddr_pll_ctrl = RD4(sc, ZY7_SLCR_DDR_PLL_CTRL);
+	io_pll_ctrl = RD4(sc, ZY7_SLCR_IO_PLL_CTRL);
+
+	/* Determine ARM PLL frequency. */
+	if (((arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) == 0 &&
+	     (arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_FORCE) != 0) ||
+	    ((arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) != 0 &&
+	     (bootmode & ZY7_SLCR_BOOT_MODE_PLL_BYPASS) != 0))
+		/* PLL is bypassed. */
+		arm_pll_frequency = ps_clk_frequency;
+	else
+		arm_pll_frequency = ps_clk_frequency *
+			((arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_FDIV_MASK) >>
+			 ZY7_SLCR_PLL_CTRL_FDIV_SHIFT);
+
+	/* Determine DDR PLL frequency. */
+	if (((ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) == 0 &&
+	     (ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_FORCE) != 0) ||
+	    ((ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) != 0 &&
+	     (bootmode & ZY7_SLCR_BOOT_MODE_PLL_BYPASS) != 0))
+		/* PLL is bypassed. */
+		ddr_pll_frequency = ps_clk_frequency;
+	else
+		ddr_pll_frequency = ps_clk_frequency *
+			((ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_FDIV_MASK) >>
+			 ZY7_SLCR_PLL_CTRL_FDIV_SHIFT);
+
+	/* Determine IO PLL frequency. */
+	if (((io_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) == 0 &&
+	     (io_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_FORCE) != 0) ||
+	    ((io_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) != 0 &&
+	     (bootmode & ZY7_SLCR_BOOT_MODE_PLL_BYPASS) != 0))
+		/* PLL is bypassed. */
+		io_pll_frequency = ps_clk_frequency;
+	else
+		io_pll_frequency = ps_clk_frequency *
+			((io_pll_ctrl & ZY7_SLCR_PLL_CTRL_FDIV_MASK) >>
+			 ZY7_SLCR_PLL_CTRL_FDIV_SHIFT);
+
 	/* Lock SLCR registers. */
 	zy7_slcr_lock(sc);
 
diff --git a/sys/arm/xilinx/zy7_slcr.h b/sys/arm/xilinx/zy7_slcr.h
index af30b09..70c4661 100644
--- a/sys/arm/xilinx/zy7_slcr.h
+++ b/sys/arm/xilinx/zy7_slcr.h
@@ -126,6 +126,18 @@
 #define ZY7_SLCR_GEM1_RCLK_CTRL		0x013c
 #define ZY7_SLCR_GEM0_CLK_CTRL		0x0140
 #define ZY7_SLCR_GEM1_CLK_CTRL		0x0144
+#define   ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MASK		(0x3f<<20)
+#define   ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_SHIFT		20
+#define   ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX		0x3f
+#define   ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_MASK		(0x3f<<8)
+#define   ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_SHIFT		8
+#define   ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_MAX		0x3f
+#define   ZY7_SLCR_GEM_CLK_CTRL_SRCSEL_MASK		(7<<4)
+#define   ZY7_SLCR_GEM_CLK_CTRL_SRCSEL_IO_PLL		(0<<4)
+#define   ZY7_SLCR_GEM_CLK_CTRL_SRCSEL_ARM_PLL		(2<<4)
+#define   ZY7_SLCR_GEM_CLK_CTRL_SRCSEL_DDR_PLL		(3<<4)
+#define   ZY7_SLCR_GEM_CLK_CTRL_SRCSEL_EMIO_CLK		(4<<4)
+#define   ZY7_SLCR_GEM_CLK_CTRL_CLKACT			1
 #define ZY7_SLCR_SMC_CLK_CTRL		0x0148
 #define ZY7_SLCR_LQSPI_CLK_CTRL		0x014c
 #define ZY7_SLCR_SDIO_CLK_CTRL		0x0150
@@ -274,6 +286,7 @@
 
 #ifdef _KERNEL
 extern void zy7_slcr_preload_pl(void);
-extern void zy7_slcr_postload_pl(int);
+extern void zy7_slcr_postload_pl(int en_level_shifters);
+extern int cgem_set_ref_clk(int unit, int frequency);
 #endif
 #endif /* _ZY7_SLCR_H_ */