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author | andrew <andrew@FreeBSD.org> | 2016-09-13 14:14:39 +0000 |
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committer | andrew <andrew@FreeBSD.org> | 2016-09-13 14:14:39 +0000 |
commit | 9ebff16104b6a438f21c5cae6ead584e2867b490 (patch) | |
tree | 5d0f2ce60ebdedd0dce6be5a869dacdfb6ea15f5 /sys/arm64 | |
parent | b31f1c992e6cebc40c3bb756ff601ffb0f3e189f (diff) | |
download | FreeBSD-src-9ebff16104b6a438f21c5cae6ead584e2867b490.zip FreeBSD-src-9ebff16104b6a438f21c5cae6ead584e2867b490.tar.gz |
MFC 305767:
Add a warning about a known erratum we have observed on ThunderX pass 1.1.
As this is evaluation hardware with only a few users, and there is a lack
of information add a warning when booting on this hardware.
Diffstat (limited to 'sys/arm64')
-rw-r--r-- | sys/arm64/arm64/identcpu.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c index 70a2d84..c047c54 100644 --- a/sys/arm64/arm64/identcpu.c +++ b/sys/arm64/arm64/identcpu.c @@ -179,6 +179,28 @@ print_cpu_features(u_int cpu) } printf("\n"); + /* + * There is a hardware errata where, if one CPU is performing a TLB + * invalidation while another is performing a store-exclusive the + * store-exclusive may return the wrong status. A workaround seems + * to be to use an IPI to invalidate on each CPU, however given the + * limited number of affected units (pass 1.1 is the evaluation + * hardware revision), and the lack of information from Cavium + * this has not been implemented. + * + * At the time of writing this the only information is from: + * https://lkml.org/lkml/2016/8/4/722 + */ + /* + * XXX: CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1 on it's own also + * triggers on pass 2.0+. + */ + if (cpu == 0 && CPU_VAR(PCPU_GET(midr)) == 0 && + CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1) + printf("WARNING: ThunderX Pass 1.1 detected.\nThis has known " + "hardware bugs that may cause the incorrect operation of " + "atomic operations.\n"); + if (cpu != 0 && cpu_print_regs == 0) return; |