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| author | andrew <andrew@FreeBSD.org> | 2017-05-30 11:03:05 +0000 |
|---|---|---|
| committer | andrew <andrew@FreeBSD.org> | 2017-05-30 11:03:05 +0000 |
| commit | 5dffdf8890fd393717edd4fe864fa30bf98bba14 (patch) | |
| tree | 9c7aaee943ada350c9624c04a22f46b40d877408 /sys/arm64 | |
| parent | 1f3c97ecfed994b264c7f384f0cecac12f34eabf (diff) | |
| download | FreeBSD-src-5dffdf8890fd393717edd4fe864fa30bf98bba14.zip FreeBSD-src-5dffdf8890fd393717edd4fe864fa30bf98bba14.tar.gz | |
MFC r316755:
Add SCTLR bits added in ARMv8.1 and ARMv8.2 and start to use them in the
early boot code.
Diffstat (limited to 'sys/arm64')
| -rw-r--r-- | sys/arm64/arm64/locore.S | 7 | ||||
| -rw-r--r-- | sys/arm64/include/armreg.h | 8 |
2 files changed, 10 insertions, 5 deletions
diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S index 215975f..ed3bc87 100644 --- a/sys/arm64/arm64/locore.S +++ b/sys/arm64/arm64/locore.S @@ -624,12 +624,13 @@ tcr: TCR_CACHE_ATTRS | TCR_SMP_ATTRS) sctlr_set: /* Bits to set */ - .quad (SCTLR_UCI | SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \ + .quad (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_UCI | SCTLR_SPAN | \ + SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \ SCTLR_I | SCTLR_SED | SCTLR_SA0 | SCTLR_SA | SCTLR_C | SCTLR_M) sctlr_clear: /* Bits to clear */ - .quad (SCTLR_EE | SCTLR_EOE | SCTLR_WXN | SCTLR_UMA | SCTLR_ITD | \ - SCTLR_THEE | SCTLR_CP15BEN | SCTLR_A) + .quad (SCTLR_EE | SCTLR_EOE | SCTLR_IESB | SCTLR_WXN | SCTLR_UMA | \ + SCTLR_ITD | SCTLR_THEE | SCTLR_CP15BEN | SCTLR_A) .globl abort abort: diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index d812124..51e410f 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -380,8 +380,8 @@ #define PAR_S_MASK (0x1 << PAR_S_SHIFT) /* SCTLR_EL1 - System Control Register */ -#define SCTLR_RES0 0xc8222400 /* Reserved, write 0 */ -#define SCTLR_RES1 0x30d00800 /* Reserved, write 1 */ +#define SCTLR_RES0 0xc8222400 /* Reserved ARMv8.0, write 0 */ +#define SCTLR_RES1 0x30d00800 /* Reserved ARMv8.0, write 1 */ #define SCTLR_M 0x00000001 #define SCTLR_A 0x00000002 @@ -399,9 +399,13 @@ #define SCTLR_nTWI 0x00010000 #define SCTLR_nTWE 0x00040000 #define SCTLR_WXN 0x00080000 +#define SCTLR_IESB 0x00200000 +#define SCTLR_SPAN 0x00800000 #define SCTLR_EOE 0x01000000 #define SCTLR_EE 0x02000000 #define SCTLR_UCI 0x04000000 +#define SCTLR_nTLSMD 0x10000000 +#define SCTLR_LSMAOE 0x20000000 /* SPSR_EL1 */ /* |
