diff options
author | andrew <andrew@FreeBSD.org> | 2016-09-07 12:28:30 +0000 |
---|---|---|
committer | andrew <andrew@FreeBSD.org> | 2016-09-07 12:28:30 +0000 |
commit | 1f4d334f50994f5b4591b186cd740d14ae7f603f (patch) | |
tree | 9f5665cf4fa80b833d8e746f83735ef6772e2605 /sys/arm64 | |
parent | ae964e954722098da41ab6de612259f229aab1b3 (diff) | |
download | FreeBSD-src-1f4d334f50994f5b4591b186cd740d14ae7f603f.zip FreeBSD-src-1f4d334f50994f5b4591b186cd740d14ae7f603f.tar.gz |
MFC 304140:
Add the ARMv8.1 identification registers to the list we print when booting.
Sponsored by: ABT Systems Ltd
Diffstat (limited to 'sys/arm64')
-rw-r--r-- | sys/arm64/arm64/identcpu.c | 105 | ||||
-rw-r--r-- | sys/arm64/include/armreg.h | 48 |
2 files changed, 150 insertions, 3 deletions
diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c index 72e2021..70a2d84 100644 --- a/sys/arm64/arm64/identcpu.c +++ b/sys/arm64/arm64/identcpu.c @@ -188,6 +188,27 @@ print_cpu_features(u_int cpu) if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_ISAR0) != 0) { printed = 0; printf(" Instruction Set Attributes 0 = <"); + + switch (ID_AA64ISAR0_RDM(cpu_desc[cpu].id_aa64isar0)) { + case ID_AA64ISAR0_RDM_NONE: + break; + case ID_AA64ISAR0_RDM_IMPL: + printf("%sRDM", SEP_STR); + break; + default: + printf("%sUnknown RDM", SEP_STR); + } + + switch (ID_AA64ISAR0_ATOMIC(cpu_desc[cpu].id_aa64isar0)) { + case ID_AA64ISAR0_ATOMIC_NONE: + break; + case ID_AA64ISAR0_ATOMIC_IMPL: + printf("%sAtomic", SEP_STR); + break; + default: + printf("%sUnknown Atomic", SEP_STR); + } + switch (ID_AA64ISAR0_AES(cpu_desc[cpu].id_aa64isar0)) { case ID_AA64ISAR0_AES_NONE: break; @@ -466,8 +487,82 @@ print_cpu_features(u_int cpu) /* AArch64 Memory Model Feature Register 1 */ if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_MMFR1) != 0) { - printf(" Memory Model Features 1 = <%#lx>\n", - cpu_desc[cpu].id_aa64mmfr1); + printed = 0; + printf(" Memory Model Features 1 = <"); + + switch (ID_AA64MMFR1_PAN(cpu_desc[cpu].id_aa64mmfr1)) { + case ID_AA64MMFR1_PAN_NONE: + break; + case ID_AA64MMFR1_PAN_IMPL: + printf("%sPAN", SEP_STR); + break; + default: + printf("%sUnknown PAN", SEP_STR); + break; + } + + switch (ID_AA64MMFR1_LO(cpu_desc[cpu].id_aa64mmfr1)) { + case ID_AA64MMFR1_LO_NONE: + break; + case ID_AA64MMFR1_LO_IMPL: + printf("%sLO", SEP_STR); + break; + default: + printf("%sUnknown LO", SEP_STR); + break; + } + + switch (ID_AA64MMFR1_HPDS(cpu_desc[cpu].id_aa64mmfr1)) { + case ID_AA64MMFR1_HPDS_NONE: + break; + case ID_AA64MMFR1_HPDS_IMPL: + printf("%sHPDS", SEP_STR); + break; + default: + printf("%sUnknown HPDS", SEP_STR); + break; + } + + switch (ID_AA64MMFR1_VH(cpu_desc[cpu].id_aa64mmfr1)) { + case ID_AA64MMFR1_VH_NONE: + break; + case ID_AA64MMFR1_VH_IMPL: + printf("%sVHE", SEP_STR); + break; + default: + printf("%sUnknown VHE", SEP_STR); + break; + } + + switch (ID_AA64MMFR1_VMIDBITS(cpu_desc[cpu].id_aa64mmfr1)) { + case ID_AA64MMFR1_VMIDBITS_8: + break; + case ID_AA64MMFR1_VMIDBITS_16: + printf("%s16 VMID bits", SEP_STR); + break; + default: + printf("%sUnknown VMID bits", SEP_STR); + break; + } + + switch (ID_AA64MMFR1_HAFDBS(cpu_desc[cpu].id_aa64mmfr1)) { + case ID_AA64MMFR1_HAFDBS_NONE: + break; + case ID_AA64MMFR1_HAFDBS_AF: + printf("%sAF", SEP_STR); + break; + case ID_AA64MMFR1_HAFDBS_AF_DBS: + printf("%sAF+DBS", SEP_STR); + break; + default: + printf("%sUnknown Hardware update AF/DBS", SEP_STR); + break; + } + + if ((cpu_desc[cpu].id_aa64mmfr1 & ~ID_AA64MMFR1_MASK) != 0) + printf("%s%#lx", SEP_STR, + cpu_desc[cpu].id_aa64mmfr1 & ~ID_AA64MMFR1_MASK); + printf(">\n"); } /* AArch64 Debug Feature Register 0 */ @@ -489,6 +584,9 @@ print_cpu_features(u_int cpu) case ID_AA64DFR0_PMU_VER_3: printf("%sPMUv3", SEP_STR); break; + case ID_AA64DFR0_PMU_VER_3_1: + printf("%sPMUv3+16 bit evtCount", SEP_STR); + break; case ID_AA64DFR0_PMU_VER_IMPL: printf("%sImplementation defined PMU", SEP_STR); break; @@ -512,6 +610,9 @@ print_cpu_features(u_int cpu) case ID_AA64DFR0_DEBUG_VER_8: printf("%sDebug v8", SEP_STR); break; + case ID_AA64DFR0_DEBUG_VER_8_VHE: + printf("%sDebug v8+VHE", SEP_STR); + break; default: printf("%sUnknown Debug", SEP_STR); break; diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index 40d07f0..bb4f585 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -146,6 +146,7 @@ #define ID_AA64DFR0_DEBUG_VER_MASK (0xf << ID_AA64DFR0_DEBUG_VER_SHIFT) #define ID_AA64DFR0_DEBUG_VER(x) ((x) & ID_AA64DFR0_DEBUG_VER_MASK) #define ID_AA64DFR0_DEBUG_VER_8 (0x6 << ID_AA64DFR0_DEBUG_VER_SHIFT) +#define ID_AA64DFR0_DEBUG_VER_8_VHE (0x7 << ID_AA64DFR0_DEBUG_VER_SHIFT) #define ID_AA64DFR0_TRACE_VER_SHIFT 4 #define ID_AA64DFR0_TRACE_VER_MASK (0xf << ID_AA64DFR0_TRACE_VER_SHIFT) #define ID_AA64DFR0_TRACE_VER(x) ((x) & ID_AA64DFR0_TRACE_VER_MASK) @@ -156,6 +157,7 @@ #define ID_AA64DFR0_PMU_VER(x) ((x) & ID_AA64DFR0_PMU_VER_MASK) #define ID_AA64DFR0_PMU_VER_NONE (0x0 << ID_AA64DFR0_PMU_VER_SHIFT) #define ID_AA64DFR0_PMU_VER_3 (0x1 << ID_AA64DFR0_PMU_VER_SHIFT) +#define ID_AA64DFR0_PMU_VER_3_1 (0x4 << ID_AA64DFR0_PMU_VER_SHIFT) #define ID_AA64DFR0_PMU_VER_IMPL (0xf << ID_AA64DFR0_PMU_VER_SHIFT) #define ID_AA64DFR0_BRPS_SHIFT 12 #define ID_AA64DFR0_BRPS_MASK (0xf << ID_AA64DFR0_BRPS_SHIFT) @@ -171,7 +173,7 @@ ((((x) >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) + 1) /* ID_AA64ISAR0_EL1 */ -#define ID_AA64ISAR0_MASK 0x000ffff0 +#define ID_AA64ISAR0_MASK 0xf0fffff0 #define ID_AA64ISAR0_AES_SHIFT 4 #define ID_AA64ISAR0_AES_MASK (0xf << ID_AA64ISAR0_AES_SHIFT) #define ID_AA64ISAR0_AES(x) ((x) & ID_AA64ISAR0_AES_MASK) @@ -193,6 +195,16 @@ #define ID_AA64ISAR0_CRC32(x) ((x) & ID_AA64ISAR0_CRC32_MASK) #define ID_AA64ISAR0_CRC32_NONE (0x0 << ID_AA64ISAR0_CRC32_SHIFT) #define ID_AA64ISAR0_CRC32_BASE (0x1 << ID_AA64ISAR0_CRC32_SHIFT) +#define ID_AA64ISAR0_ATOMIC_SHIFT 20 +#define ID_AA64ISAR0_ATOMIC_MASK (0xf << ID_AA64ISAR0_ATOMIC_SHIFT) +#define ID_AA64ISAR0_ATOMIC(x) ((x) & ID_AA64ISAR0_ATOMIC_MASK) +#define ID_AA64ISAR0_ATOMIC_NONE (0x0 << ID_AA64ISAR0_ATOMIC_SHIFT) +#define ID_AA64ISAR0_ATOMIC_IMPL (0x2 << ID_AA64ISAR0_ATOMIC_SHIFT) +#define ID_AA64ISAR0_RDM_SHIFT 28 +#define ID_AA64ISAR0_RDM_MASK (0xf << ID_AA64ISAR0_RDM_SHIFT) +#define ID_AA64ISAR0_RDM(x) ((x) & ID_AA64ISAR0_RDM_MASK) +#define ID_AA64ISAR0_RDM_NONE (0x0 << ID_AA64ISAR0_RDM_SHIFT) +#define ID_AA64ISAR0_RDM_IMPL (0x1 << ID_AA64ISAR0_RDM_SHIFT) /* ID_AA64MMFR0_EL1 */ #define ID_AA64MMFR0_MASK 0xffffffff @@ -241,6 +253,40 @@ #define ID_AA64MMFR0_TGRAN4_IMPL (0x0 << ID_AA64MMFR0_TGRAN4_SHIFT) #define ID_AA64MMFR0_TGRAN4_NONE (0xf << ID_AA64MMFR0_TGRAN4_SHIFT) +/* ID_AA64MMFR1_EL1 */ +#define ID_AA64MMFR1_MASK 0x00ffffff +#define ID_AA64MMFR1_HAFDBS_SHIFT 0 +#define ID_AA64MMFR1_HAFDBS_MASK (0xf << ID_AA64MMFR1_HAFDBS_SHIFT) +#define ID_AA64MMFR1_HAFDBS(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK) +#define ID_AA64MMFR1_HAFDBS_NONE (0x0 << ID_AA64MMFR1_HAFDBS_SHIFT) +#define ID_AA64MMFR1_HAFDBS_AF (0x1 << ID_AA64MMFR1_HAFDBS_SHIFT) +#define ID_AA64MMFR1_HAFDBS_AF_DBS (0x2 << ID_AA64MMFR1_HAFDBS_SHIFT) +#define ID_AA64MMFR1_VMIDBITS_SHIFT 4 +#define ID_AA64MMFR1_VMIDBITS_MASK (0xf << ID_AA64MMFR1_VMIDBITS_SHIFT) +#define ID_AA64MMFR1_VMIDBITS(x) ((x) & ID_AA64MMFR1_VMIDBITS_MASK) +#define ID_AA64MMFR1_VMIDBITS_8 (0x0 << ID_AA64MMFR1_VMIDBITS_SHIFT) +#define ID_AA64MMFR1_VMIDBITS_16 (0x2 << ID_AA64MMFR1_VMIDBITS_SHIFT) +#define ID_AA64MMFR1_VH_SHIFT 8 +#define ID_AA64MMFR1_VH_MASK (0xf << ID_AA64MMFR1_VH_SHIFT) +#define ID_AA64MMFR1_VH(x) ((x) & ID_AA64MMFR1_VH_MASK) +#define ID_AA64MMFR1_VH_NONE (0x0 << ID_AA64MMFR1_VH_SHIFT) +#define ID_AA64MMFR1_VH_IMPL (0x1 << ID_AA64MMFR1_VH_SHIFT) +#define ID_AA64MMFR1_HPDS_SHIFT 12 +#define ID_AA64MMFR1_HPDS_MASK (0xf << ID_AA64MMFR1_HPDS_SHIFT) +#define ID_AA64MMFR1_HPDS(x) ((x) & ID_AA64MMFR1_HPDS_MASK) +#define ID_AA64MMFR1_HPDS_NONE (0x0 << ID_AA64MMFR1_HPDS_SHIFT) +#define ID_AA64MMFR1_HPDS_IMPL (0x1 << ID_AA64MMFR1_HPDS_SHIFT) +#define ID_AA64MMFR1_LO_SHIFT 16 +#define ID_AA64MMFR1_LO_MASK (0xf << ID_AA64MMFR1_LO_SHIFT) +#define ID_AA64MMFR1_LO(x) ((x) & ID_AA64MMFR1_LO_MASK) +#define ID_AA64MMFR1_LO_NONE (0x0 << ID_AA64MMFR1_LO_SHIFT) +#define ID_AA64MMFR1_LO_IMPL (0x1 << ID_AA64MMFR1_LO_SHIFT) +#define ID_AA64MMFR1_PAN_SHIFT 20 +#define ID_AA64MMFR1_PAN_MASK (0xf << ID_AA64MMFR1_PAN_SHIFT) +#define ID_AA64MMFR1_PAN(x) ((x) & ID_AA64MMFR1_PAN_MASK) +#define ID_AA64MMFR1_PAN_NONE (0x0 << ID_AA64MMFR1_PAN_SHIFT) +#define ID_AA64MMFR1_PAN_IMPL (0x1 << ID_AA64MMFR1_PAN_SHIFT) + /* ID_AA64PFR0_EL1 */ #define ID_AA64PFR0_MASK 0x0fffffff #define ID_AA64PFR0_EL0_SHIFT 0 |