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authorzbb <zbb@FreeBSD.org>2016-01-18 13:31:29 +0000
committerzbb <zbb@FreeBSD.org>2016-01-18 13:31:29 +0000
commitcc4c2bd6ffdf37d6c5b85e82e909de2ecbb47de5 (patch)
tree863e56b7557f5e47afbf032b3fa2180754656d7c /sys/arm64
parent0107aadb82e37e90347f8f0992b7a06d79fb9f2c (diff)
downloadFreeBSD-src-cc4c2bd6ffdf37d6c5b85e82e909de2ecbb47de5.zip
FreeBSD-src-cc4c2bd6ffdf37d6c5b85e82e909de2ecbb47de5.tar.gz
Update ThunderX PCIe driver to fit new DTS layout
In recent EFI the DTS entries changed for PCIe controller. This commit fixes internal PCIe, external is yet TBD. Submitted by: Dominik Ermel <der@semihalf.com> Obtained from: Semihalf Sponsored by: The FreeBSD Foundation Differential revision: https://reviews.freebsd.org/D4976
Diffstat (limited to 'sys/arm64')
-rw-r--r--sys/arm64/cavium/thunder_pcie.c12
-rw-r--r--sys/arm64/cavium/thunder_pcie_common.c6
-rw-r--r--sys/arm64/cavium/thunder_pcie_common.h4
-rw-r--r--sys/arm64/cavium/thunder_pcie_pem.c2
4 files changed, 12 insertions, 12 deletions
diff --git a/sys/arm64/cavium/thunder_pcie.c b/sys/arm64/cavium/thunder_pcie.c
index 8abdacd..20aab1e 100644
--- a/sys/arm64/cavium/thunder_pcie.c
+++ b/sys/arm64/cavium/thunder_pcie.c
@@ -92,7 +92,7 @@ __FBSDID("$FreeBSD$");
#define PCI_ADDR_CELL_SIZE 2
struct thunder_pcie_softc {
- struct pcie_range ranges[MAX_RANGES_TUPLES];
+ struct pcie_range ranges[RANGES_TUPLES_MAX];
struct rman mem_rman;
struct resource *res;
int ecam;
@@ -132,7 +132,8 @@ thunder_pcie_probe(device_t dev)
if (!ofw_bus_status_okay(dev))
return (ENXIO);
- if (ofw_bus_is_compatible(dev, "cavium,thunder-pcie")) {
+ if (ofw_bus_is_compatible(dev, "cavium,thunder-pcie") ||
+ ofw_bus_is_compatible(dev, "cavium,pci-host-thunder-ecam")) {
device_set_desc(dev, "Cavium Integrated PCI/PCI-E Controller");
return (BUS_PROBE_DEFAULT);
}
@@ -180,7 +181,7 @@ thunder_pcie_attach(device_t dev)
return (error);
}
- for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) {
+ for (tuple = 0; tuple < RANGES_TUPLES_MAX; tuple++) {
base = sc->ranges[tuple].phys_base;
size = sc->ranges[tuple].size;
if ((base == 0) || (size == 0))
@@ -245,8 +246,7 @@ parse_pci_mem_ranges(struct thunder_pcie_softc *sc)
tuples_count = cells_count /
(pci_addr_cells + parent_addr_cells + size_cells);
- if ((tuples_count > MAX_RANGES_TUPLES) ||
- (tuples_count < MIN_RANGES_TUPLES)) {
+ if (tuples_count > RANGES_TUPLES_MAX) {
device_printf(sc->dev,
"Unexpected number of 'ranges' tuples in FDT\n");
rv = ENXIO;
@@ -296,7 +296,7 @@ parse_pci_mem_ranges(struct thunder_pcie_softc *sc)
}
}
- for (; tuple < MAX_RANGES_TUPLES; tuple++) {
+ for (; tuple < RANGES_TUPLES_MAX; tuple++) {
/* zero-fill remaining tuples to mark empty elements in array */
sc->ranges[tuple].phys_base = 0;
sc->ranges[tuple].size = 0;
diff --git a/sys/arm64/cavium/thunder_pcie_common.c b/sys/arm64/cavium/thunder_pcie_common.c
index 59c383f..e1b7fb2 100644
--- a/sys/arm64/cavium/thunder_pcie_common.c
+++ b/sys/arm64/cavium/thunder_pcie_common.c
@@ -48,7 +48,7 @@ range_addr_is_pci(struct pcie_range *ranges, uint64_t addr, uint64_t size)
struct pcie_range *r;
int tuple;
- for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) {
+ for (tuple = 0; tuple < RANGES_TUPLES_MAX; tuple++) {
r = &ranges[tuple];
if (addr >= r->pci_base &&
addr < (r->pci_base + r->size) &&
@@ -68,7 +68,7 @@ range_addr_is_phys(struct pcie_range *ranges, uint64_t addr, uint64_t size)
struct pcie_range *r;
int tuple;
- for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) {
+ for (tuple = 0; tuple < RANGES_TUPLES_MAX; tuple++) {
r = &ranges[tuple];
if (addr >= r->phys_base &&
addr < (r->phys_base + r->size) &&
@@ -90,7 +90,7 @@ range_addr_pci_to_phys(struct pcie_range *ranges, uint64_t pci_addr)
int tuple;
/* Find physical address corresponding to given bus address */
- for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) {
+ for (tuple = 0; tuple < RANGES_TUPLES_MAX; tuple++) {
r = &ranges[tuple];
if (pci_addr >= r->pci_base &&
pci_addr < (r->pci_base + r->size)) {
diff --git a/sys/arm64/cavium/thunder_pcie_common.h b/sys/arm64/cavium/thunder_pcie_common.h
index a3c67c2..731675b 100644
--- a/sys/arm64/cavium/thunder_pcie_common.h
+++ b/sys/arm64/cavium/thunder_pcie_common.h
@@ -29,8 +29,8 @@
#ifndef _CAVIUM_THUNDER_PCIE_COMMON_H_
#define _CAVIUM_THUNDER_PCIE_COMMON_H_
-#define MAX_RANGES_TUPLES 5
-#define MIN_RANGES_TUPLES 2
+#define RANGES_TUPLES_MAX 6
+#define RANGES_TUPLES_INVALID (RANGES_TUPLES_MAX + 1)
struct pcie_range {
uint64_t pci_base;
diff --git a/sys/arm64/cavium/thunder_pcie_pem.c b/sys/arm64/cavium/thunder_pcie_pem.c
index 9ea3f77..e5007ac 100644
--- a/sys/arm64/cavium/thunder_pcie_pem.c
+++ b/sys/arm64/cavium/thunder_pcie_pem.c
@@ -114,7 +114,7 @@ struct thunder_pem_softc {
struct resource *reg;
bus_space_tag_t reg_bst;
bus_space_handle_t reg_bsh;
- struct pcie_range ranges[MAX_RANGES_TUPLES];
+ struct pcie_range ranges[RANGES_TUPLES_MAX];
struct rman mem_rman;
struct rman io_rman;
bus_space_handle_t pem_sli_base;
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