Finally bring it support for the i80219 XScale processor.

Submitted by:	Max M. Boyarov <m.boyarov bsd by>

12 files changed, 729 insertions, 71 deletions

diff --git a/sys/arm/xscale/i80321/ep80219_machdep.c b/sys/arm/xscale/i80321/ep80219_machdep.c
new file mode 100644
index 0000000..52178b2
--- /dev/null
+++ b/sys/arm/xscale/i80321/ep80219_machdep.c
@@ -0,0 +1,521 @@
+/*	$NetBSD: hpc_machdep.c,v 1.70 2003/09/16 08:18:22 agc Exp $	*/
+
+/*-
+ * Copyright (c) 1994-1998 Mark Brinicombe.
+ * Copyright (c) 1994 Brini.
+ * All rights reserved.
+ *
+ * This code is derived from software written for Brini by Mark Brinicombe
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Brini.
+ * 4. The name of the company nor the name of the author may be used to
+ *    endorse or promote products derived from this software without specific
+ *    prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RiscBSD kernel project
+ *
+ * machdep.c
+ *
+ * Machine dependant functions for kernel setup
+ *
+ * This file needs a lot of work. 
+ *
+ * Created      : 17/09/94
+ */
+
+#include "opt_msgbuf.h"
+#include "opt_ddb.h"
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#define _ARM32_BUS_DMA_PRIVATE
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/sysproto.h>
+#include <sys/signalvar.h>
+#include <sys/imgact.h>
+#include <sys/kernel.h>
+#include <sys/ktr.h>
+#include <sys/linker.h>
+#include <sys/lock.h>
+#include <sys/malloc.h>
+#include <sys/mutex.h>
+#include <sys/pcpu.h>
+#include <sys/proc.h>
+#include <sys/ptrace.h>
+#include <sys/cons.h>
+#include <sys/bio.h>
+#include <sys/bus.h>
+#include <sys/buf.h>
+#include <sys/exec.h>
+#include <sys/kdb.h>
+#include <sys/msgbuf.h>
+#include <machine/reg.h>
+#include <machine/cpu.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm.h>
+#include <vm/vm_object.h>
+#include <vm/vm_page.h>
+#include <vm/vm_pager.h>
+#include <vm/vm_map.h>
+#include <vm/vnode_pager.h>
+#include <machine/pmap.h>
+#include <machine/vmparam.h>
+#include <machine/pcb.h>
+#include <machine/undefined.h>
+#include <machine/machdep.h>
+#include <machine/metadata.h>
+#include <machine/armreg.h>
+#include <machine/bus.h>
+#include <sys/reboot.h>
+
+#include <arm/xscale/i80321/i80321reg.h>
+#include <arm/xscale/i80321/i80321var.h>
+#include <arm/xscale/i80321/iq80321reg.h>
+#include <arm/xscale/i80321/obiovar.h>
+
+#define KERNEL_PT_SYS			0	/* Page table for mapping proc0 zero page */
+#define KERNEL_PT_IOPXS			1
+#define KERNEL_PT_BEFOREKERN	2
+#define KERNEL_PT_AFKERNEL		3	/* L2 table for mapping after kernel */
+#define KERNEL_PT_AFKERNEL_NUM	9
+
+/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */
+#define NUM_KERNEL_PTS		(KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM)
+
+/* Define various stack sizes in pages */
+#define IRQ_STACK_SIZE	1
+#define ABT_STACK_SIZE	1
+#ifdef IPKDB
+#define UND_STACK_SIZE	2
+#else
+#define UND_STACK_SIZE	1
+#endif
+
+extern u_int data_abort_handler_address;
+extern u_int prefetch_abort_handler_address;
+extern u_int undefined_handler_address;
+
+struct pv_addr kernel_pt_table[NUM_KERNEL_PTS];
+
+extern void *_end;
+
+extern vm_offset_t sa1_cache_clean_addr;
+
+extern int *end;
+
+struct pcpu __pcpu;
+struct pcpu *pcpup = &__pcpu;
+
+/* Physical and virtual addresses for some global pages */
+
+vm_paddr_t phys_avail[10];
+vm_paddr_t dump_avail[4];
+vm_offset_t physical_pages;
+vm_offset_t clean_sva, clean_eva;
+
+struct pv_addr systempage;
+struct pv_addr msgbufpv;
+struct pv_addr irqstack;
+struct pv_addr undstack;
+struct pv_addr abtstack;
+struct pv_addr kernelstack;
+struct pv_addr minidataclean;
+
+static struct trapframe proc0_tf;
+
+
+/* #define IQ80321_OBIO_BASE 0xfe800000UL */
+/* #define IQ80321_OBIO_SIZE 0x00100000UL */
+
+/* Static device mappings. */
+static const struct pmap_devmap ep80219_devmap[] = {
+	/* 
+	 * Map the on-board devices VA == PA so that we can access them
+	 * with the MMU on or off.
+	 */
+	{
+		IQ80321_OBIO_BASE,
+		IQ80321_OBIO_BASE,
+		IQ80321_OBIO_SIZE,
+		VM_PROT_READ|VM_PROT_WRITE,                             
+		PTE_NOCACHE,
+	},
+	{
+		IQ80321_IOW_VBASE,
+		VERDE_OUT_XLATE_IO_WIN0_BASE,
+		VERDE_OUT_XLATE_IO_WIN_SIZE,
+		VM_PROT_READ|VM_PROT_WRITE,
+		PTE_NOCACHE,
+	},	    
+	{
+		IQ80321_80321_VBASE,
+		VERDE_PMMR_BASE,
+		VERDE_PMMR_SIZE,
+		VM_PROT_READ|VM_PROT_WRITE,
+		PTE_NOCACHE,
+	},
+	{
+		0,
+		0,
+		0,
+		0,
+		0,
+	}
+};
+
+#ifdef DDB
+extern vm_offset_t ksym_start, ksym_end;
+#endif
+
+extern vm_offset_t xscale_cache_clean_addr;
+
+void *
+initarm(void *arg, void *arg2)
+{
+	struct pv_addr  kernel_l1pt;
+	int loop;
+	u_int l1pagetable;
+	vm_offset_t freemempos;
+	vm_offset_t freemem_pt;
+	vm_offset_t afterkern;
+	vm_offset_t freemem_after;
+	vm_offset_t lastaddr;
+#ifdef DDB
+	vm_offset_t zstart = 0, zend = 0;
+#endif
+	int i = 0;
+	uint32_t fake_preload[35];
+	uint32_t memsize, memstart;
+
+	i = 0;
+
+	set_cpufuncs();
+	fake_preload[i++] = MODINFO_NAME;
+	fake_preload[i++] = strlen("elf kernel") + 1;
+	strcpy((char*)&fake_preload[i++], "elf kernel");
+	i += 2;
+	fake_preload[i++] = MODINFO_TYPE;
+	fake_preload[i++] = strlen("elf kernel") + 1;
+	strcpy((char*)&fake_preload[i++], "elf kernel");
+	i += 2;
+	fake_preload[i++] = MODINFO_ADDR;
+	fake_preload[i++] = sizeof(vm_offset_t);
+	fake_preload[i++] = KERNBASE + 0x00200000;
+	fake_preload[i++] = MODINFO_SIZE;
+	fake_preload[i++] = sizeof(uint32_t);
+	fake_preload[i++] = (uint32_t)&end - KERNBASE - 0x00200000;
+#ifdef DDB
+	if (*(uint32_t *)KERNVIRTADDR == MAGIC_TRAMP_NUMBER) {
+		fake_preload[i++] = MODINFO_METADATA|MODINFOMD_SSYM;
+		fake_preload[i++] = sizeof(vm_offset_t);
+		fake_preload[i++] = *(uint32_t *)(KERNVIRTADDR + 4);
+		fake_preload[i++] = MODINFO_METADATA|MODINFOMD_ESYM;
+		fake_preload[i++] = sizeof(vm_offset_t);
+		fake_preload[i++] = *(uint32_t *)(KERNVIRTADDR + 8);
+		lastaddr = *(uint32_t *)(KERNVIRTADDR + 8);
+		zend = lastaddr;
+		zstart = *(uint32_t *)(KERNVIRTADDR + 4);
+		ksym_start = zstart;
+		ksym_end = zend;
+	} else
+#endif
+		lastaddr = (vm_offset_t)&end;
+	
+	fake_preload[i++] = 0;
+	fake_preload[i] = 0;
+	preload_metadata = (void *)fake_preload;
+
+
+	pcpu_init(pcpup, 0, sizeof(struct pcpu));
+	PCPU_SET(curthread, &thread0);
+
+#define KERNEL_TEXT_BASE (KERNBASE + 0x00200000)
+	freemempos = 0xa0200000;
+	/* Define a macro to simplify memory allocation */
+#define	valloc_pages(var, np)			\
+	alloc_pages((var).pv_pa, (np));				\
+	(var).pv_va = (var).pv_pa + 0x20000000;
+
+#define alloc_pages(var, np)			\
+	freemempos -= (np * PAGE_SIZE);		\
+	(var) = freemempos;		\
+	memset((char *)(var), 0, ((np) * PAGE_SIZE));
+
+	while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
+		freemempos -= PAGE_SIZE;
+	valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
+	for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
+		if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
+			valloc_pages(kernel_pt_table[loop],
+						 L2_TABLE_SIZE / PAGE_SIZE);
+		} else {
+			kernel_pt_table[loop].pv_pa = freemempos +
+			    (loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
+			    L2_TABLE_SIZE_REAL;
+			kernel_pt_table[loop].pv_va = 
+			    kernel_pt_table[loop].pv_pa + 0x20000000;
+		}
+		i++;
+	}
+	freemem_pt = freemempos;
+	freemempos = 0xa0100000;
+	/*
+	 * Allocate a page for the system page mapped to V0x00000000
+	 * This page will just contain the system vectors and can be
+	 * shared by all processes.
+	 */
+	valloc_pages(systempage, 1);
+
+	/* Allocate stacks for all modes */
+	valloc_pages(irqstack, IRQ_STACK_SIZE);
+	valloc_pages(abtstack, ABT_STACK_SIZE);
+	valloc_pages(undstack, UND_STACK_SIZE);
+	valloc_pages(kernelstack, KSTACK_PAGES);
+	alloc_pages(minidataclean.pv_pa, 1);
+	valloc_pages(msgbufpv, round_page(MSGBUF_SIZE) / PAGE_SIZE);
+#ifdef ARM_USE_SMALL_ALLOC
+	freemempos -= PAGE_SIZE;
+	freemem_pt = trunc_page(freemem_pt);
+	freemem_after = freemempos - ((freemem_pt - 0xa0100000) /
+								  PAGE_SIZE) * sizeof(struct arm_small_page);
+	arm_add_smallalloc_pages((void *)(freemem_after + 0x20000000)
+							 , (void *)0xc0100000, freemem_pt - 0xa0100000, 1);
+	freemem_after -= ((freemem_after - 0xa0001000) / PAGE_SIZE) *
+	    sizeof(struct arm_small_page);
+	arm_add_smallalloc_pages((void *)(freemem_after + 0x20000000),
+							 (void *)0xc0001000,
+							 trunc_page(freemem_after) - 0xa0001000, 0);
+	
+	freemempos = trunc_page(freemem_after);
+	freemempos -= PAGE_SIZE;
+#endif
+	/*
+	 * Allocate memory for the l1 and l2 page tables. The scheme to avoid
+	 * wasting memory by allocating the l1pt on the first 16k memory was
+	 * taken from NetBSD rpc_machdep.c. NKPT should be greater than 12 for
+	 * this to work (which is supposed to be the case).
+	 */
+
+	/*
+	 * Now we start construction of the L1 page table
+	 * We start by mapping the L2 page tables into the L1.
+	 * This means that we can replace L1 mappings later on if necessary
+	 */
+	l1pagetable = kernel_l1pt.pv_va;
+
+	/* Map the L2 pages tables in the L1 page table */
+	pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00100000 - 1),
+				   &kernel_pt_table[KERNEL_PT_SYS]);
+	pmap_link_l2pt(l1pagetable, IQ80321_IOPXS_VBASE,
+				   &kernel_pt_table[KERNEL_PT_IOPXS]);
+	pmap_link_l2pt(l1pagetable, KERNBASE,
+				   &kernel_pt_table[KERNEL_PT_BEFOREKERN]);
+	pmap_map_chunk(l1pagetable, KERNBASE, IQ80321_SDRAM_START, 0x100000,
+				   VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
+	pmap_map_chunk(l1pagetable, KERNBASE + 0x100000, IQ80321_SDRAM_START + 0x100000,
+				   0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
+	pmap_map_chunk(l1pagetable, KERNBASE + 0x200000, IQ80321_SDRAM_START + 0x200000,
+				   (((uint32_t)(lastaddr) - KERNBASE - 0x200000) + L1_S_SIZE) & ~(L1_S_SIZE - 1),
+				   VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
+	freemem_after = ((int)lastaddr + PAGE_SIZE) & ~(PAGE_SIZE - 1);
+	afterkern = round_page(((vm_offset_t)lastaddr + L1_S_SIZE) & ~(L1_S_SIZE 
+																   - 1));
+	for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
+		pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000,
+					   &kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
+	}
+	pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa, 
+				   VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
+	
+
+#ifdef ARM_USE_SMALL_ALLOC
+	if ((freemem_after + 2 * PAGE_SIZE) <= afterkern) {
+		arm_add_smallalloc_pages((void *)(freemem_after),
+		    (void*)(freemem_after + PAGE_SIZE),
+		    afterkern - (freemem_after + PAGE_SIZE), 0);
+		    
+	}
+#endif
+
+	/* Map the Mini-Data cache clean area. */
+	xscale_setup_minidata(l1pagetable, afterkern,
+						  minidataclean.pv_pa);
+
+	/* Map the vector page. */
+	pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
+				   VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
+	pmap_devmap_bootstrap(l1pagetable, ep80219_devmap);
+	/*
+	 * Give the XScale global cache clean code an appropriately
+	 * sized chunk of unmapped VA space starting at 0xff000000
+	 * (our device mappings end before this address).
+	 */
+	xscale_cache_clean_addr = 0xff000000U;
+
+	cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
+	setttb(kernel_l1pt.pv_pa);
+	cpu_tlb_flushID();
+	cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
+	/*
+	 * Pages were allocated during the secondary bootstrap for the
+	 * stacks for different CPU modes.
+	 * We must now set the r13 registers in the different CPU modes to
+	 * point to these stacks.
+	 * Since the ARM stacks use STMFD etc. we must set r13 to the top end
+	 * of the stack memory.
+	 */
+
+				   
+	set_stackptr(PSR_IRQ32_MODE,
+	    irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE);
+	set_stackptr(PSR_ABT32_MODE,
+	    abtstack.pv_va + ABT_STACK_SIZE * PAGE_SIZE);
+	set_stackptr(PSR_UND32_MODE,
+	    undstack.pv_va + UND_STACK_SIZE * PAGE_SIZE);
+
+
+
+	/*
+	 * We must now clean the cache again....
+	 * Cleaning may be done by reading new data to displace any
+	 * dirty data in the cache. This will have happened in setttb()
+	 * but since we are boot strapping the addresses used for the read
+	 * may have just been remapped and thus the cache could be out
+	 * of sync. A re-clean after the switch will cure this.
+	 * After booting there are no gross reloations of the kernel thus
+	 * this problem will not occur after initarm().
+	 */
+	cpu_idcache_wbinv_all();
+	/*
+	 * Fetch the SDRAM start/size from the i80321 SDRAM configration
+	 * registers.
+	 */
+	i80321_calibrate_delay();
+	i80321_sdram_bounds(&obio_bs_tag, IQ80321_80321_VBASE + VERDE_MCU_BASE,
+	    &memstart, &memsize);
+	physmem = memsize / PAGE_SIZE;
+	cninit();
+
+	/* Set stack for exception handlers */
+	
+	data_abort_handler_address = (u_int)data_abort_handler;
+	prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
+	undefined_handler_address = (u_int)undefinedinstruction_bounce;
+	undefined_init();
+				
+	proc_linkup(&proc0, &ksegrp0, &thread0);
+	thread0.td_kstack = kernelstack.pv_va;
+	thread0.td_pcb = (struct pcb *)
+		(thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1;
+	thread0.td_pcb->pcb_flags = 0;
+	thread0.td_frame = &proc0_tf;
+	pcpup->pc_curpcb = thread0.td_pcb;
+	
+	/* Enable MMU, I-cache, D-cache, write buffer. */
+
+	arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
+
+
+
+	pmap_curmaxkvaddr = afterkern + PAGE_SIZE;
+	pmap_bootstrap(pmap_curmaxkvaddr, 
+	    0xd0000000, &kernel_l1pt);
+	msgbufp = (void*)msgbufpv.pv_va;
+	msgbufinit(msgbufp, MSGBUF_SIZE);
+	mutex_init();
+	
+	i = 0;
+#ifdef ARM_USE_SMALL_ALLOC
+	phys_avail[i++] = 0xa0000000;
+	phys_avail[i++] = 0xa0001000; 	/*
+					 *XXX: Gross hack to get our
+					 * pages in the vm_page_array
+					 . */
+#endif
+	phys_avail[i++] = round_page(virtual_avail - KERNBASE + IQ80321_SDRAM_START);
+	phys_avail[i++] = trunc_page(0xa0000000 + memsize - 1);
+	phys_avail[i++] = 0;
+	phys_avail[i] = 0;
+	dump_avail[0] = 0xa0000000;
+	dump_avail[1] = 0xa0000000 + memsize;
+	dump_avail[2] = 0;
+	dump_avail[3] = 0;
+	
+	/* Do basic tuning, hz etc */
+	init_param1();
+	init_param2(physmem);
+	avail_end = 0xa0000000 + memsize - 1;
+	kdb_init();
+	return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
+	    sizeof(struct pcb)));
+}
+
+extern int
+machdep_pci_route_interrupt(device_t pcib, device_t dev, int pin)
+{
+	int bus;
+	int device;
+	int func;
+	uint32_t busno;
+	struct i80321_pci_softc *sc = device_get_softc(pcib);
+	bus = pci_get_bus(dev);
+	device = pci_get_slot(dev);
+	func = pci_get_function(dev);
+	busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
+	busno = PCIXSR_BUSNO(busno);
+	if (busno == 0xff)
+		busno = 0;
+	if (bus != busno)
+		goto no_mapping;
+	switch (device) {
+		/* EP80219 PCI */
+	case 1: /* Ethernet i82555 10/100 */
+		printf("Device %d routed to irq %d\n", device, ICU_INT_XINT(0));
+		return (ICU_INT_XINT(0));
+	case 2: /* UART */
+		printf("Device %d routed to irq %d\n", device, ICU_INT_XINT(1));
+		return (ICU_INT_XINT(1));
+	case 3:
+		/*
+		 * The S-ATA chips are behind the bridge, and all of
+		 * the S-ATA interrupts are wired together.
+		 */
+		printf("Device %d routed to irq %d\n", device, ICU_INT_XINT(2));
+		return (ICU_INT_XINT(2));
+	case 4: /* MINI-PIC_INT */
+		printf("Device %d routed to irq %d\n", device, ICU_INT_XINT(3));
+		return( ICU_INT_XINT(3));
+	default:
+no_mapping:
+		printf("No mapping for %d/%d/%d/%c\n", bus, device, func, pin);
+		
+	}
+	return (0);
+
+}
diff --git a/sys/arm/xscale/i80321/files.ep80219 b/sys/arm/xscale/i80321/files.ep80219
new file mode 100644
index 0000000..cbf2e39
--- /dev/null
+++ b/sys/arm/xscale/i80321/files.ep80219
@@ -0,0 +1,12 @@
+#$FreeBSD$
+#
+#
+# EP80219 Board Specific
+#
+arm/xscale/i80321/iq80321.c		standard
+arm/xscale/i80321/ep80219_machdep.c	standard
+arm/xscale/i80321/obio.c		standard
+arm/xscale/i80321/obio_space.c		standard
+arm/xscale/i80321/uart_cpu_i80321.c	optional	uart
+arm/xscale/i80321/uart_bus_i80321.c	optional	uart
+dev/uart/uart_dev_ns8250.c		optional	uart
diff --git a/sys/arm/xscale/i80321/files.i80219 b/sys/arm/xscale/i80321/files.i80219
new file mode 100644
index 0000000..87e961c
--- /dev/null
+++ b/sys/arm/xscale/i80321/files.i80219
@@ -0,0 +1,13 @@
+#$FreeBSD$
+#
+# IOP Specific
+# 
+arm/arm/cpufunc_asm_xscale.S		standard
+arm/arm/irq_dispatch.S			standard
+arm/xscale/i80321/i80321.c		standard
+arm/xscale/i80321/i80321_dma.c		optional	dma
+arm/xscale/i80321/i80321_mcu.c		standard
+arm/xscale/i80321/i80321_pci.c		optional	pci
+arm/xscale/i80321/i80321_space.c	standard
+arm/xscale/i80321/i80321_timer.c	standard
+arm/xscale/i80321/i80321_wdog.c		optional	iopwdog
diff --git a/sys/arm/xscale/i80321/i80321_intr.h b/sys/arm/xscale/i80321/i80321_intr.h
index 5f777ce..4e432da 100644
--- a/sys/arm/xscale/i80321/i80321_intr.h
+++ b/sys/arm/xscale/i80321/i80321_intr.h
@@ -73,9 +73,21 @@ i80321_set_intrsteer(void)
 	    : "r" (intr_steer & ICU_INT_HWMASK));
 }
 
+#if defined ( CPU_XSCALE_80219 )
+#define INT_SWMASK														\
+	((1U << ICU_INT_bit26) |											\
+	 (1U << ICU_INT_bit25) |											\
+	 (1U << ICU_INT_bit23) |											\
+	 (1U << ICU_INT_bit22) |											\
+	 (1U << ICU_INT_bit7)  |											\
+	 (1U << ICU_INT_bit6)  |											\
+	 (1U << ICU_INT_bit5)  |											\
+	 (1U << ICU_INT_bit4))
+#else
 #define INT_SWMASK                                                      \
         ((1U << ICU_INT_bit26) | (1U << ICU_INT_bit22) |                \
          (1U << ICU_INT_bit5)  | (1U << ICU_INT_bit4))
+#endif
 
 #if 0
 static __inline void __attribute__((__unused__))
diff --git a/sys/arm/xscale/i80321/i80321_pci.c b/sys/arm/xscale/i80321/i80321_pci.c
index b905bbf..abda074d 100644
--- a/sys/arm/xscale/i80321/i80321_pci.c
+++ b/sys/arm/xscale/i80321/i80321_pci.c
@@ -68,20 +68,6 @@ __FBSDID("$FreeBSD$");
 #include <dev/pci/pcireg.h>
 extern struct i80321_softc *i80321_softc;
 
-struct i80321_pci_softc {
-	device_t 		sc_dev;
-	bus_space_tag_t 	sc_st;
-	bus_space_handle_t 	sc_atu_sh;
-	bus_space_tag_t		sc_pciio;
-	bus_space_tag_t		sc_pcimem;
-	int			sc_busno;
-	struct rman		sc_mem_rman;
-	struct rman		sc_io_rman;
-	struct rman		sc_irq_rman;
-	uint32_t		sc_mem;
-	uint32_t		sc_io;
-};
-
 static int
 i80321_pci_probe(device_t dev)
 {
@@ -260,62 +246,6 @@ i80321_pci_write_config(device_t dev, int bus, int slot, int func, int reg,
 }
 
 static int
-i80321_pci_route_interrupt(device_t pcib, device_t dev, int pin)
-{
-	int bus;
-	int device;
-	int func;
-	uint32_t busno;
-	struct i80321_pci_softc *sc = device_get_softc(pcib);
-	bus = pci_get_bus(dev);
-	device = pci_get_slot(dev);
-	func = pci_get_function(dev);
-	busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
-	busno = PCIXSR_BUSNO(busno);
-	if (busno == 0xff)
-		busno = 0;
-	if (bus != busno)
-		goto no_mapping;
-	switch (device) {
-		/* IQ31244 PCI */
-	case 1: /* PCIX-PCIX bridge */
-		/*
-		 * The S-ATA chips are behind the bridge, and all of
-		 * the S-ATA interrupts are wired together.
-		 */
-		return (ICU_INT_XINT(2));
-	case 2: /* PCI slot */
-		/* All pins are wired together. */
-		return (ICU_INT_XINT(3));
-	case 3: /* i82546 dual Gig-E */
-		if (pin == 1 || pin == 2)
-			return (ICU_INT_XINT(0));
-		goto no_mapping;
-		/* IQ80321 PCI */
-	case 4: /* i82544 Gig-E */
-	case 8: /*
-		 * Apparently you can set the device for the ethernet adapter
-		 * to 8 with a jumper, so handle that as well
-		 */
-		if (pin == 1)
-			return (ICU_INT_XINT(0));
-		goto no_mapping;
-	case 6: /* S-PCI-X slot */
-		if (pin == 1)
-			return (ICU_INT_XINT(2));
-		if (pin == 2)
-			return (ICU_INT_XINT(3));
-		goto no_mapping;
-	default:
-no_mapping:
-		printf("No mapping for %d/%d/%d/%c\n", bus, device, func, pin);
-		
-	}
-	return (0);
-
-}
-
-static int
 i80321_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
 {
 	struct i80321_pci_softc *sc = device_get_softc(dev);
@@ -453,7 +383,7 @@ static device_method_t i80321_pci_methods[] = {
 	DEVMETHOD(pcib_maxslots,	i80321_pci_maxslots),
 	DEVMETHOD(pcib_read_config,	i80321_pci_read_config),
 	DEVMETHOD(pcib_write_config,	i80321_pci_write_config),
-	DEVMETHOD(pcib_route_interrupt,	i80321_pci_route_interrupt),
+	DEVMETHOD(pcib_route_interrupt,	machdep_pci_route_interrupt),
 
 	{0, 0}
 };
diff --git a/sys/arm/xscale/i80321/i80321reg.h b/sys/arm/xscale/i80321/i80321reg.h
index 19092da..5804e99 100644
--- a/sys/arm/xscale/i80321/i80321reg.h
+++ b/sys/arm/xscale/i80321/i80321reg.h
@@ -91,14 +91,18 @@
 #define	VERDE_MCU_BASE			0x0500
 #define	VERDE_MCU_SIZE			0x0100
 
+#if defined(CPU_XSCALE_80321)
 #define	VERDE_SSP_BASE			0x0600
 #define	VERDE_SSP_SIZE			0x0080
+#endif
 
 #define	VERDE_PBIU_BASE			0x0680
 #define	VERDE_PBIU_SIZE			0x0080
 
+#if defined(CPU_XSCALE_80321)
 #define	VERDE_AAU_BASE			0x0800
 #define	VERDE_AAU_SIZE			0x0100
+#endif 
 
 #define	VERDE_I2C_BASE			0x1680
 #define	VERDE_I2C_BASE0			(VERDE_I2C_BASE + 0x00)
@@ -335,9 +339,23 @@
 #define	ICU_INT_XINT0		27	/* external interrupts */
 #define	ICU_INT_XINT(x)		((x) + ICU_INT_XINT0)
 #define	ICU_INT_bit26		26
+
+#if defined (CPU_XSCALE_80219)
+#define	ICU_INT_bit25		25	/* reserved */
+#else
+/* CPU_XSCALE_80321 */
 #define	ICU_INT_SSP		25	/* SSP serial port */
+#endif
+
 #define	ICU_INT_MUE		24	/* msg unit error */
+
+#if defined (CPU_XSCALE_80219)
+#define	ICU_INT_bit23		23	/* reserved */
+#else
+/* CPU_XSCALE_80321 */
 #define	ICU_INT_AAUE		23	/* AAU error */
+#endif
+
 #define	ICU_INT_bit22		22
 #define	ICU_INT_DMA1E		21	/* DMA Ch 1 error */
 #define	ICU_INT_DMA0E		20	/* DMA Ch 0 error */
@@ -353,8 +371,16 @@
 #define	ICU_INT_TMR1		10	/* timer 1 */
 #define	ICU_INT_TMR0		9	/* timer 0 */
 #define	ICU_INT_CPPM		8	/* core processor PMU */
+
+#if defined(CPU_XSCALE_80219)
+#define	ICU_INT_bit7		7 /* reserved */
+#define	ICU_INT_bit6		6 /* reserved */
+#else
+/* CPU_XSCALE_80321 */
 #define	ICU_INT_AAU_EOC		7	/* AAU end-of-chain */
 #define	ICU_INT_AAU_EOT		6	/* AAU end-of-transfer */
+#endif
+
 #define	ICU_INT_bit5		5
 #define	ICU_INT_bit4		4
 #define	ICU_INT_DMA1_EOC	3	/* DMA1 end-of-chain */
@@ -362,15 +388,30 @@
 #define	ICU_INT_DMA0_EOC	1	/* DMA0 end-of-chain */
 #define	ICU_INT_DMA0_EOT	0	/* DMA0 end-of-transfer */
 
+#if defined (CPU_XSCALE_80219)
+#define	ICU_INT_HWMASK		(0xffffffff &	 \
+							 ~((1 << ICU_INT_bit26) |	\
+							   (1 << ICU_INT_bit25) |	\
+							   (1 << ICU_INT_bit23) |	\
+							   (1 << ICU_INT_bit22) |	\
+							   (1 << ICU_INT_bit7)  |	\
+							   (1 << ICU_INT_bit6)  |	\
+							   (1 << ICU_INT_bit5)  |	\
+							   (1 << ICU_INT_bit4)))
+
+#else
+/* CPU_XSCALE_80321 */
 #define	ICU_INT_HWMASK		(0xffffffff & \
 					~((1 << ICU_INT_bit26) | \
 					  (1 << ICU_INT_bit22) | \
 					  (1 << ICU_INT_bit5)  | \
 					  (1 << ICU_INT_bit4)))
+#endif
 
 /*
  * SSP Serial Port
  */
+#if defined (CPU_XSCALE_80321)
 
 #define	SSP_SSCR0	0x00		/* SSC control 0 */
 #define	SSP_SSCR1	0x04		/* SSC control 1 */
@@ -421,6 +462,8 @@
 #define	SSP_SSITR_TRFS		(1U << 6)/* Test Rx FIFO service */
 #define	SSP_SSITR_TROR		(1U << 7)/* Test Rx overrun */
 
+#endif /* CPU_XSCALE_80321 */
+
 /*
  * Peripheral Bus Interface Unit
  */
diff --git a/sys/arm/xscale/i80321/i80321var.h b/sys/arm/xscale/i80321/i80321var.h
index 903b18e..2766fd2 100644
--- a/sys/arm/xscale/i80321/i80321var.h
+++ b/sys/arm/xscale/i80321/i80321var.h
@@ -111,6 +111,22 @@ struct i80321_softc {
 	struct rman sc_irq_rman;
 			
 };
+
+
+struct i80321_pci_softc {
+	device_t 		sc_dev;
+	bus_space_tag_t 	sc_st;
+	bus_space_handle_t 	sc_atu_sh;
+	bus_space_tag_t		sc_pciio;
+	bus_space_tag_t		sc_pcimem;
+	int			sc_busno;
+	struct rman		sc_mem_rman;
+	struct rman		sc_io_rman;
+	struct rman		sc_irq_rman;
+	uint32_t		sc_mem;
+	uint32_t		sc_io;
+};
+
 void	i80321_sdram_bounds(bus_space_tag_t, bus_space_handle_t,
 	    vm_paddr_t *, vm_size_t *);
 
@@ -120,5 +136,7 @@ void	i80321_calibrate_delay(void);
 void	i80321_bs_init(bus_space_tag_t, void *);
 void	i80321_io_bs_init(bus_space_tag_t, void *);
 void	i80321_mem_bs_init(bus_space_tag_t, void *);
+extern int machdep_pci_route_interrupt(device_t pcib, device_t dev, int pin);
+
 
 #endif /* _ARM_XSCALE_I80321VAR_H_ */
diff --git a/sys/arm/xscale/i80321/iq31244_machdep.c b/sys/arm/xscale/i80321/iq31244_machdep.c
index e31706e..16c22d4 100644
--- a/sys/arm/xscale/i80321/iq31244_machdep.c
+++ b/sys/arm/xscale/i80321/iq31244_machdep.c
@@ -478,3 +478,60 @@ initarm(void *arg, void *arg2)
 	return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
 	    sizeof(struct pcb)));
 }
+
+
+extern int
+machdep_pci_route_interrupt(device_t pcib, device_t dev, int pin)
+{
+	int bus;
+	int device;
+	int func;
+	uint32_t busno;
+	struct i80321_pci_softc *sc = device_get_softc(pcib);
+	bus = pci_get_bus(dev);
+	device = pci_get_slot(dev);
+	func = pci_get_function(dev);
+	busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
+	busno = PCIXSR_BUSNO(busno);
+	if (busno == 0xff)
+		busno = 0;
+	if (bus != busno)
+		goto no_mapping;
+	switch (device) {
+		/* IQ31244 PCI */
+	case 1: /* PCIX-PCIX bridge */
+		/*
+		 * The S-ATA chips are behind the bridge, and all of
+		 * the S-ATA interrupts are wired together.
+		 */
+		return (ICU_INT_XINT(2));
+	case 2: /* PCI slot */
+		/* All pins are wired together. */
+		return (ICU_INT_XINT(3));
+	case 3: /* i82546 dual Gig-E */
+		if (pin == 1 || pin == 2)
+			return (ICU_INT_XINT(0));
+		goto no_mapping;
+		/* IQ80321 PCI */
+	case 4: /* i82544 Gig-E */
+	case 8: /*
+		 * Apparently you can set the device for the ethernet adapter
+		 * to 8 with a jumper, so handle that as well
+		 */
+		if (pin == 1)
+			return (ICU_INT_XINT(0));
+		goto no_mapping;
+	case 6: /* S-PCI-X slot */
+		if (pin == 1)
+			return (ICU_INT_XINT(2));
+		if (pin == 2)
+			return (ICU_INT_XINT(3));
+		goto no_mapping;
+	default:
+no_mapping:
+		printf("No mapping for %d/%d/%d/%c\n", bus, device, func, pin);
+		
+	}
+	return (0);
+
+}
diff --git a/sys/arm/xscale/i80321/iq80321.c b/sys/arm/xscale/i80321/iq80321.c
index 625ad1b..13b5917 100644
--- a/sys/arm/xscale/i80321/iq80321.c
+++ b/sys/arm/xscale/i80321/iq80321.c
@@ -157,16 +157,34 @@ iq80321_attach(device_t dev)
 	b0u = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCIR_BARS+0x4);
 	b1l = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCIR_BARS+0x8);
 	b1u = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCIR_BARS+0xc);
+
+#ifdef VERBOSE_INIT_ARM	
+	printf("i80321: BAR0 = %08x.%08x BAR1 = %08x.%08x\n",
+		   b0l,b0u, b1l, b1u );
+#endif
+
 #define PCI_MAPREG_MEM_ADDR_MASK	0xfffffff0
 	b0l &= PCI_MAPREG_MEM_ADDR_MASK;
 	b0u &= PCI_MAPREG_MEM_ADDR_MASK;
 	b1l &= PCI_MAPREG_MEM_ADDR_MASK;
 	b1u &= PCI_MAPREG_MEM_ADDR_MASK;
 
+#ifdef VERBOSE_INIT_ARM	
+	printf("i80219: BAR0 = %08x.%08x BAR1 = %08x.%08x\n",
+		   b0l,b0u, b1l, b1u );
+#endif
+
 	if ((b0u != b1u) || (b0l != 0) || ((b1l & ~0x80000000U) != 0))
 		sc->sc_is_host = 0;
 	else
 		sc->sc_is_host = 1;
+
+	/* FIXME: i force it's */	
+
+#ifdef CPU_XSCALE_80219
+	sc->sc_is_host = 1;
+#endif
+	
 	i80321_sdram_bounds(sc->sc_st, sc->sc_mcu_sh, &memstart, &memsize);
 	/*
 	 * We set up the Inbound Windows as follows:
@@ -224,6 +242,21 @@ iq80321_attach(device_t dev)
 	sc->sc_iwin[3].iwin_base_hi = 0;
 	sc->sc_iwin[3].iwin_xlate = 0;
 	sc->sc_iwin[3].iwin_size = 0;
+	
+#ifdef 	VERBOSE_INIT_ARM
+	printf("i80321: Reserve space for private devices (Inbound Window 1) \n hi:0x%08x lo:0x%08x xlate:0x%08x size:0x%08x\n",
+		   sc->sc_iwin[1].iwin_base_hi,
+		   sc->sc_iwin[1].iwin_base_lo,
+		   sc->sc_iwin[1].iwin_xlate,
+		   sc->sc_iwin[1].iwin_size
+		);
+	printf("i80321: RAM access (Inbound Window 2) \n hi:0x%08x lo:0x%08x xlate:0x%08x size:0x%08x\n",
+		   sc->sc_iwin[2].iwin_base_hi,
+		   sc->sc_iwin[2].iwin_base_lo,
+		   sc->sc_iwin[2].iwin_xlate,
+		   sc->sc_iwin[2].iwin_size
+		);
+#endif
 
 	/*
 	 * We set up the Outbound Windows as follows:
@@ -259,11 +292,15 @@ iq80321_attach(device_t dev)
 	device_add_child(dev, "obio", 0);
 	device_add_child(dev, "itimer", 0);
 	device_add_child(dev, "iopwdog", 0);
+#ifndef 	CPU_XSCALE_80219
 	device_add_child(dev, "iqseg", 0);
+#endif	
 	device_add_child(dev, "pcib", busno);
 	device_add_child(dev, "i80321_dma", 0);
 	device_add_child(dev, "i80321_dma", 1);
+#ifndef CPU_XSCALE_80219	
 	device_add_child(dev, "i80321_aau", 0);
+#endif
 	bus_generic_probe(dev);
 	bus_generic_attach(dev);
 
diff --git a/sys/arm/xscale/i80321/iq80321reg.h b/sys/arm/xscale/i80321/iq80321reg.h
index 1e518eb..d887fcd 100644
--- a/sys/arm/xscale/i80321/iq80321reg.h
+++ b/sys/arm/xscale/i80321/iq80321reg.h
@@ -85,6 +85,7 @@
 #define	IQ80321_80321_VBASE	(IQ80321_IOW_VBASE +			\
 				 VERDE_OUT_XLATE_IO_WIN_SIZE)
 
+#define	IQ80321_SDRAM_START	0xa0000000
 /*
  * The IQ80321 on-board devices are mapped VA==PA during bootstrap.
  * Conveniently, the size of the on-board register space is 1 section
@@ -95,6 +96,7 @@
 
 #define	IQ80321_UART1		0xfe800000UL	/* TI 16550 */
 
+#if defined( CPU_XSCALE_80321 )
 #define	IQ80321_7SEG_MSB	0xfe840000UL
 #define	IQ80321_7SEG_LSB	0xfe850000UL
 
@@ -104,5 +106,6 @@
 #define	BATTERY_STAT_PRES	(1U << 0)
 #define	BATTERY_STAT_CHRG	(1U << 1)
 #define	BATTERY_STAT_DISCHRG	(1U << 2)
+#endif /* CPU_XSCALE_80321 */
 
 #endif /* _IQ80321REG_H_ */
diff --git a/sys/arm/xscale/i80321/std.ep80219 b/sys/arm/xscale/i80321/std.ep80219
new file mode 100644
index 0000000..9f5cbb7
--- /dev/null
+++ b/sys/arm/xscale/i80321/std.ep80219
@@ -0,0 +1,7 @@
+#EP80219 board configuration
+#$FreeBSD$
+include	"../xscale/i80321/std.i80219"
+files		"../xscale/i80321/files.ep80219"
+makeoptions	KERNPHYSADDR=0xa0200000
+makeoptions	KERNVIRTADDR=0xc0200000
+options	COUNTS_PER_SEC=198000000
diff --git a/sys/arm/xscale/i80321/std.i80219 b/sys/arm/xscale/i80321/std.i80219
new file mode 100644
index 0000000..8ff075c
--- /dev/null
+++ b/sys/arm/xscale/i80321/std.i80219
@@ -0,0 +1,5 @@
+#XScale i80219 generic configuration
+#$FreeBSD$
+files		"../xscale/i80321/files.i80219"
+include		"../xscale/std.xscale"
+cpu 		CPU_XSCALE_80219