MFC 265852: Map device memory using PTE_DEVICE rather than PTE_NOCACHE.

1 files changed, 18 insertions, 18 deletions

diff --git a/sys/arm/xscale/ixp425/avila_machdep.c b/sys/arm/xscale/ixp425/avila_machdep.c
index 3fdad96..b1d6734 100644
--- a/sys/arm/xscale/ixp425/avila_machdep.c
+++ b/sys/arm/xscale/ixp425/avila_machdep.c
@@ -118,31 +118,31 @@ struct pv_addr minidataclean;
 static const struct arm_devmap_entry ixp425_devmap[] = {
 	/* Physical/Virtual address for I/O space */
     { IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
 	/* Expansion Bus */
     { IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
 	/* CFI Flash on the Expansion Bus */
     { IXP425_EXP_BUS_CS0_VBASE, IXP425_EXP_BUS_CS0_HWBASE,
-      IXP425_EXP_BUS_CS0_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      IXP425_EXP_BUS_CS0_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
 	/* IXP425 PCI Configuration */
     { IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
 	/* SDRAM Controller */
     { IXP425_MCU_VBASE, IXP425_MCU_HWBASE, IXP425_MCU_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
 	/* PCI Memory Space */
     { IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
 	/* Q-Mgr Memory Space */
     { IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
     { 0 },
 };
@@ -151,45 +151,45 @@ static const struct arm_devmap_entry ixp425_devmap[] = {
 static const struct arm_devmap_entry ixp435_devmap[] = {
 	/* Physical/Virtual address for I/O space */
     { IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
     { IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
 	/* IXP425 PCI Configuration */
     { IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
 	/* DDRII Controller NB: mapped same place as IXP425 */
     { IXP425_MCU_VBASE, IXP435_MCU_HWBASE, IXP425_MCU_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
 	/* PCI Memory Space */
     { IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
 	/* Q-Mgr Memory Space */
     { IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
 	/* CFI Flash on the Expansion Bus */
     { IXP425_EXP_BUS_CS0_VBASE, IXP425_EXP_BUS_CS0_HWBASE,
-      IXP425_EXP_BUS_CS0_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      IXP425_EXP_BUS_CS0_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
 	/* USB1 Memory Space */
     { IXP435_USB1_VBASE, IXP435_USB1_HWBASE, IXP435_USB1_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 	/* USB2 Memory Space */
     { IXP435_USB2_VBASE, IXP435_USB2_HWBASE, IXP435_USB2_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
 	/* GPS Memory Space */
     { CAMBRIA_GPS_VBASE, CAMBRIA_GPS_HWBASE, CAMBRIA_GPS_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
 	/* RS485 Memory Space */
     { CAMBRIA_RS485_VBASE, CAMBRIA_RS485_HWBASE, CAMBRIA_RS485_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
     { 0 }
 };