Add initial IOP342 support.

Thanks to Intel for providing sample hardware.

Approved by:	re (blanket)

16 files changed, 2869 insertions, 0 deletions

diff --git a/sys/arm/xscale/i8134x/crb_machdep.c b/sys/arm/xscale/i8134x/crb_machdep.c
new file mode 100644
index 0000000..032528b
--- /dev/null
+++ b/sys/arm/xscale/i8134x/crb_machdep.c
@@ -0,0 +1,451 @@
+/*	$NetBSD: hpc_machdep.c,v 1.70 2003/09/16 08:18:22 agc Exp $	*/
+
+/*-
+ * Copyright (c) 1994-1998 Mark Brinicombe.
+ * Copyright (c) 1994 Brini.
+ * All rights reserved.
+ *
+ * This code is derived from software written for Brini by Mark Brinicombe
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Brini.
+ * 4. The name of the company nor the name of the author may be used to
+ *    endorse or promote products derived from this software without specific
+ *    prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RiscBSD kernel project
+ *
+ * machdep.c
+ *
+ * Machine dependant functions for kernel setup
+ *
+ * This file needs a lot of work. 
+ *
+ * Created      : 17/09/94
+ */
+
+#include "opt_msgbuf.h"
+#include "opt_ddb.h"
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#define _ARM32_BUS_DMA_PRIVATE
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/sysproto.h>
+#include <sys/signalvar.h>
+#include <sys/imgact.h>
+#include <sys/kernel.h>
+#include <sys/ktr.h>
+#include <sys/linker.h>
+#include <sys/lock.h>
+#include <sys/malloc.h>
+#include <sys/mutex.h>
+#include <sys/pcpu.h>
+#include <sys/proc.h>
+#include <sys/ptrace.h>
+#include <sys/cons.h>
+#include <sys/bio.h>
+#include <sys/bus.h>
+#include <sys/buf.h>
+#include <sys/exec.h>
+#include <sys/kdb.h>
+#include <sys/msgbuf.h>
+#include <machine/reg.h>
+#include <machine/cpu.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm.h>
+#include <vm/vm_object.h>
+#include <vm/vm_page.h>
+#include <vm/vm_pager.h>
+#include <vm/vm_map.h>
+#include <vm/vnode_pager.h>
+#include <machine/pmap.h>
+#include <machine/vmparam.h>
+#include <machine/pcb.h>
+#include <machine/undefined.h>
+#include <machine/machdep.h>
+#include <machine/metadata.h>
+#include <machine/armreg.h>
+#include <machine/bus.h>
+#include <sys/reboot.h>
+
+
+#include <arm/xscale/i80321/i80321var.h> /* For i80321_calibrate_delay() */
+
+#include <arm/xscale/i8134x/i81342reg.h>
+#include <arm/xscale/i8134x/i81342var.h>
+#include <arm/xscale/i8134x/obiovar.h>
+
+
+#define KERNEL_PT_SYS		0	/* Page table for mapping proc0 zero page */
+#define	KERNEL_PT_IOPXS		1
+#define KERNEL_PT_BEFOREKERN	2
+#define KERNEL_PT_AFKERNEL	3	/* L2 table for mapping after kernel */
+#define	KERNEL_PT_AFKERNEL_NUM	9
+
+/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */
+#define NUM_KERNEL_PTS		(KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM)
+
+/* Define various stack sizes in pages */
+#define IRQ_STACK_SIZE	1
+#define ABT_STACK_SIZE	1
+#ifdef IPKDB
+#define UND_STACK_SIZE	2
+#else
+#define UND_STACK_SIZE	1
+#endif
+
+extern u_int data_abort_handler_address;
+extern u_int prefetch_abort_handler_address;
+extern u_int undefined_handler_address;
+
+struct pv_addr kernel_pt_table[NUM_KERNEL_PTS];
+
+extern void *_end;
+
+extern vm_offset_t sa1_cache_clean_addr;
+
+extern int *end;
+
+struct pcpu __pcpu;
+struct pcpu *pcpup = &__pcpu;
+
+/* Physical and virtual addresses for some global pages */
+
+vm_paddr_t phys_avail[10];
+vm_paddr_t dump_avail[4];
+vm_offset_t physical_pages;
+vm_offset_t clean_sva, clean_eva;
+
+struct pv_addr systempage;
+struct pv_addr msgbufpv;
+struct pv_addr irqstack;
+struct pv_addr undstack;
+struct pv_addr abtstack;
+struct pv_addr kernelstack;
+
+static struct trapframe proc0_tf;
+
+/* Static device mappings. */
+static const struct pmap_devmap iq81342_devmap[] = {
+	    {
+		    IOP34X_VADDR,
+		    IOP34X_HWADDR,
+		    IOP34X_SIZE,
+		    VM_PROT_READ|VM_PROT_WRITE,
+		    PTE_NOCACHE,
+	    },
+	    {
+		    /*
+		     * Cheat and map a whole section, this will bring
+		     * both PCI-X and PCI-E outbound I/O
+		     */
+		    IOP34X_PCIX_OIOBAR_VADDR &~ (0x100000 - 1),
+		    IOP34X_PCIX_OIOBAR &~ (0x100000 - 1),
+		    0x100000,
+		    VM_PROT_READ|VM_PROT_WRITE,
+		    PTE_NOCACHE,
+	    },
+	    {	    
+		    0,
+		    0,
+		    0,
+		    0,
+		    0,
+	    }
+};
+
+#define SDRAM_START 0x00000000
+
+#ifdef DDB
+extern vm_offset_t ksym_start, ksym_end;
+#endif
+
+extern vm_offset_t xscale_cache_clean_addr;
+
+void *
+initarm(void *arg, void *arg2)
+{
+	struct pv_addr  kernel_l1pt;
+	int loop;
+	u_int l1pagetable;
+	vm_offset_t freemempos;
+	vm_offset_t freemem_pt;
+	vm_offset_t afterkern;
+	vm_offset_t freemem_after;
+	vm_offset_t lastaddr;
+#ifdef DDB
+	vm_offset_t zstart = 0, zend = 0;
+#endif
+	int i;
+	uint32_t fake_preload[35];
+	uint32_t memsize, memstart;
+
+	i = 0;
+
+	set_cpufuncs();
+	fake_preload[i++] = MODINFO_NAME;
+	fake_preload[i++] = strlen("elf kernel") + 1;
+	strcpy((char*)&fake_preload[i++], "elf kernel");
+	i += 2;
+	fake_preload[i++] = MODINFO_TYPE;
+	fake_preload[i++] = strlen("elf kernel") + 1;
+	strcpy((char*)&fake_preload[i++], "elf kernel");
+	i += 2;
+	fake_preload[i++] = MODINFO_ADDR;
+	fake_preload[i++] = sizeof(vm_offset_t);
+	fake_preload[i++] = KERNBASE + 0x00200000;
+	fake_preload[i++] = MODINFO_SIZE;
+	fake_preload[i++] = sizeof(uint32_t);
+	fake_preload[i++] = (uint32_t)&end - KERNBASE - 0x00200000;
+#ifdef DDB
+	if (*(uint32_t *)KERNVIRTADDR == MAGIC_TRAMP_NUMBER) {
+		fake_preload[i++] = MODINFO_METADATA|MODINFOMD_SSYM;
+		fake_preload[i++] = sizeof(vm_offset_t);
+		fake_preload[i++] = *(uint32_t *)(KERNVIRTADDR + 4);
+		fake_preload[i++] = MODINFO_METADATA|MODINFOMD_ESYM;
+		fake_preload[i++] = sizeof(vm_offset_t);
+		fake_preload[i++] = *(uint32_t *)(KERNVIRTADDR + 8);
+		lastaddr = *(uint32_t *)(KERNVIRTADDR + 8);
+		zend = lastaddr;
+		zstart = *(uint32_t *)(KERNVIRTADDR + 4);
+		ksym_start = zstart;
+		ksym_end = zend;
+	} else
+#endif
+		lastaddr = (vm_offset_t)&end;
+
+	fake_preload[i++] = 0;
+	fake_preload[i] = 0;
+	preload_metadata = (void *)fake_preload;
+
+
+	pcpu_init(pcpup, 0, sizeof(struct pcpu));
+	PCPU_SET(curthread, &thread0);
+
+#define KERNEL_TEXT_BASE (KERNBASE + 0x00200000)
+	freemempos = 0x00200000;
+	/* Define a macro to simplify memory allocation */
+#define	valloc_pages(var, np)			\
+	alloc_pages((var).pv_pa, (np));		\
+	(var).pv_va = (var).pv_pa + 0xc0000000;
+
+#define alloc_pages(var, np)			\
+	freemempos -= (np * PAGE_SIZE);		\
+	(var) = freemempos;		\
+	memset((char *)(var), 0, ((np) * PAGE_SIZE));
+
+	while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
+		freemempos -= PAGE_SIZE;
+	valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
+	for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
+		if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
+			valloc_pages(kernel_pt_table[loop],
+			    L2_TABLE_SIZE / PAGE_SIZE);
+		} else {
+			kernel_pt_table[loop].pv_pa = freemempos +
+			    (loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
+			    L2_TABLE_SIZE_REAL;
+			kernel_pt_table[loop].pv_va = 
+			    kernel_pt_table[loop].pv_pa + 0xc0000000;
+		}
+	}
+	freemem_pt = freemempos;
+	freemempos = 0x00100000;
+	/*
+	 * Allocate a page for the system page mapped to V0x00000000
+	 * This page will just contain the system vectors and can be
+	 * shared by all processes.
+	 */
+	valloc_pages(systempage, 1);
+
+	/* Allocate stacks for all modes */
+	valloc_pages(irqstack, IRQ_STACK_SIZE);
+	valloc_pages(abtstack, ABT_STACK_SIZE);
+	valloc_pages(undstack, UND_STACK_SIZE);
+	valloc_pages(kernelstack, KSTACK_PAGES);
+	valloc_pages(msgbufpv, round_page(MSGBUF_SIZE) / PAGE_SIZE);
+#ifdef ARM_USE_SMALL_ALLOC
+	freemempos -= PAGE_SIZE;
+	freemem_pt = trunc_page(freemem_pt);
+	freemem_after = freemempos - ((freemem_pt - 0x00100000) /
+	    PAGE_SIZE) * sizeof(struct arm_small_page);
+	arm_add_smallalloc_pages((void *)(freemem_after + 0xc0000000)
+	    , (void *)0xc0100000, freemem_pt - 0x00100000, 1);
+	freemem_after -= ((freemem_after - 0x00001000) / PAGE_SIZE) *
+	    sizeof(struct arm_small_page);
+#if 0
+	arm_add_smallalloc_pages((void *)(freemem_after + 0xc0000000)
+	, (void *)0xc0001000, trunc_page(freemem_after) - 0x00001000, 0);
+#endif
+	freemempos = trunc_page(freemem_after);
+	freemempos -= PAGE_SIZE;
+#endif
+	/*
+	 * Now we start construction of the L1 page table
+	 * We start by mapping the L2 page tables into the L1.
+	 * This means that we can replace L1 mappings later on if necessary
+	 */
+	l1pagetable = kernel_l1pt.pv_va;
+
+	/* Map the L2 pages tables in the L1 page table */
+	pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00100000 - 1),
+	    &kernel_pt_table[KERNEL_PT_SYS]);
+	pmap_map_chunk(l1pagetable, KERNBASE, SDRAM_START, 0x100000,
+	    VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
+
+	pmap_map_chunk(l1pagetable, KERNBASE + 0x100000, SDRAM_START + 0x100000,
+	    0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
+
+	pmap_map_chunk(l1pagetable, KERNBASE + 0x200000, SDRAM_START + 0x200000,
+	   (((uint32_t)(lastaddr) - KERNBASE - 0x200000) + L1_S_SIZE) & ~(L1_S_SIZE - 1),
+	    VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
+	freemem_after = ((int)lastaddr + PAGE_SIZE) & ~(PAGE_SIZE - 1);
+	afterkern = round_page(((vm_offset_t)lastaddr + L1_S_SIZE) & ~(L1_S_SIZE 
+	    - 1));
+	for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
+		pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000,
+		    &kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
+	}
+	
+
+#ifdef ARM_USE_SMALL_ALLOC
+	if ((freemem_after + 2 * PAGE_SIZE) <= afterkern) {
+		arm_add_smallalloc_pages((void *)(freemem_after),
+		    (void*)(freemem_after + PAGE_SIZE),
+		    afterkern - (freemem_after + PAGE_SIZE), 0);
+		    
+	}
+#endif
+
+	/* Map the vector page. */
+	pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
+	    VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
+	pmap_devmap_bootstrap(l1pagetable, iq81342_devmap);
+	/*
+	 * Give the XScale global cache clean code an appropriately
+	 * sized chunk of unmapped VA space starting at 0xff000000
+	 * (our device mappings end before this address).
+	 */
+	xscale_cache_clean_addr = 0xff000000U;
+
+	cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
+	setttb(kernel_l1pt.pv_pa);
+	cpu_tlb_flushID();
+	cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
+	/*
+	 * Pages were allocated during the secondary bootstrap for the
+	 * stacks for different CPU modes.
+	 * We must now set the r13 registers in the different CPU modes to
+	 * point to these stacks.
+	 * Since the ARM stacks use STMFD etc. we must set r13 to the top end
+	 * of the stack memory.
+	 */
+
+				   
+	set_stackptr(PSR_IRQ32_MODE,
+	    irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE);
+	set_stackptr(PSR_ABT32_MODE,
+	    abtstack.pv_va + ABT_STACK_SIZE * PAGE_SIZE);
+	set_stackptr(PSR_UND32_MODE,
+	    undstack.pv_va + UND_STACK_SIZE * PAGE_SIZE);
+
+
+
+	/*
+	 * We must now clean the cache again....
+	 * Cleaning may be done by reading new data to displace any
+	 * dirty data in the cache. This will have happened in setttb()
+	 * but since we are boot strapping the addresses used for the read
+	 * may have just been remapped and thus the cache could be out
+	 * of sync. A re-clean after the switch will cure this.
+	 * After booting there are no gross reloations of the kernel thus
+	 * this problem will not occur after initarm().
+	 */
+	cpu_idcache_wbinv_all();
+	i80321_calibrate_delay();
+	i81342_sdram_bounds(&obio_bs_tag, IOP34X_VADDR, &memstart, &memsize);
+	physmem = memsize / PAGE_SIZE;
+	cninit();
+	/* Set stack for exception handlers */
+	
+	data_abort_handler_address = (u_int)data_abort_handler;
+	prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
+	undefined_handler_address = (u_int)undefinedinstruction_bounce;
+	undefined_init();
+				
+#ifdef KSE
+	proc_linkup(&proc0, &ksegrp0, &thread0);
+#else
+	proc_linkup(&proc0, &thread0);
+#endif
+	thread0.td_kstack = kernelstack.pv_va;
+	thread0.td_pcb = (struct pcb *)
+		(thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1;
+	thread0.td_pcb->pcb_flags = 0;
+	thread0.td_frame = &proc0_tf;
+	pcpup->pc_curpcb = thread0.td_pcb;
+	
+	arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
+
+	pmap_curmaxkvaddr = afterkern + PAGE_SIZE;
+	/*
+	 * ARM_USE_SMALL_ALLOC uses dump_avail, so it must be filled before
+	 * calling pmap_bootstrap.
+	 */
+	dump_avail[0] = 0x00000000;
+	dump_avail[1] = 0x00000000 + memsize;
+	dump_avail[2] = 0;
+	dump_avail[3] = 0;
+					
+	pmap_bootstrap(pmap_curmaxkvaddr, 
+	    0xd0000000, &kernel_l1pt);
+	msgbufp = (void*)msgbufpv.pv_va;
+	msgbufinit(msgbufp, MSGBUF_SIZE);
+	mutex_init();
+	
+	i = 0;
+#ifdef ARM_USE_SMALL_ALLOC
+	phys_avail[i++] = 0x00000000;
+	phys_avail[i++] = 0x00001000; 	/*
+					 *XXX: Gross hack to get our
+					 * pages in the vm_page_array
+					 . */
+#endif
+	phys_avail[i++] = round_page(virtual_avail - KERNBASE + SDRAM_START);
+	phys_avail[i++] = trunc_page(0x00000000 + memsize - 1);
+	phys_avail[i++] = 0;
+	phys_avail[i] = 0;
+	
+	/* Do basic tuning, hz etc */
+	init_param1();
+	init_param2(physmem);
+	kdb_init();
+	return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
+	    sizeof(struct pcb)));
+}
diff --git a/sys/arm/xscale/i8134x/files.crb b/sys/arm/xscale/i8134x/files.crb
new file mode 100644
index 0000000..d5e2b6f
--- /dev/null
+++ b/sys/arm/xscale/i8134x/files.crb
@@ -0,0 +1,2 @@
+# $FreeBSD$
+arm/xscale/i8134x/crb_machdep.c		standard
diff --git a/sys/arm/xscale/i8134x/files.i81342 b/sys/arm/xscale/i8134x/files.i81342
new file mode 100644
index 0000000..c5d5df1
--- /dev/null
+++ b/sys/arm/xscale/i8134x/files.i81342
@@ -0,0 +1,15 @@
+# $FreeBSD$
+arm/arm/cpufunc_asm_xscale.S		standard
+arm/arm/cpufunc_asm_xscale_c3.S		standard
+arm/arm/irq_dispatch.S			standard
+arm/xscale/i80321/i80321_timer.c	standard
+arm/xscale/i80321/i80321_wdog.c		optional	iopwdog
+arm/xscale/i8134x/i81342.c		standard
+arm/xscale/i8134x/i81342_mcu.c		standard
+arm/xscale/i8134x/i81342_pci.c		optional	pci
+arm/xscale/i8134x/i81342_space.c	standard
+arm/xscale/i8134x/obio.c		standard
+arm/xscale/i8134x/obio_space.c		standard
+arm/xscale/i8134x/uart_bus_i81342.c	optional	uart
+arm/xscale/i8134x/uart_cpu_i81342.c	optional	uart
+dev/uart/uart_dev_ns8250.c		optional	uart
diff --git a/sys/arm/xscale/i8134x/i81342.c b/sys/arm/xscale/i8134x/i81342.c
new file mode 100644
index 0000000..f33e79a
--- /dev/null
+++ b/sys/arm/xscale/i8134x/i81342.c
@@ -0,0 +1,463 @@
+/*-
+ * Copyright (c) 2006 Olivier Houchard
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+
+#define	_ARM32_BUS_DMA_PRIVATE
+#include <machine/bus.h>
+#include <machine/intr.h>
+
+#include <arm/xscale/i8134x/i81342reg.h>
+#include <arm/xscale/i8134x/i81342var.h>
+
+#define	WDTCR_ENABLE1		0x1e1e1e1e
+#define	WDTCR_ENABLE2		0xe1e1e1e1
+
+static volatile int intr_enabled0;
+static volatile int intr_enabled1;
+static volatile int intr_enabled2;
+static volatile int intr_enabled3;
+
+struct bus_space i81342_bs_tag;
+
+/* Read the interrupt pending register */
+
+static __inline
+uint32_t intpnd0_read(void)
+{
+	uint32_t ret;
+
+	__asm __volatile("mrc p6, 0, %0, c0, c3, 0"
+	    : "=r" (ret));
+	return (ret);
+}
+
+static __inline
+uint32_t intpnd1_read(void)
+{
+	uint32_t ret;
+
+	__asm __volatile("mrc p6, 0, %0, c1, c3, 0"
+	    : "=r" (ret));
+	return (ret);
+}
+
+static __inline
+uint32_t intpnd2_read(void)
+{
+	uint32_t ret;
+
+	__asm __volatile("mrc p6, 0, %0, c2, c3, 0"
+	    : "=r" (ret));
+	return (ret);
+}
+
+static __inline
+uint32_t intpnd3_read(void)
+{
+	uint32_t ret;
+
+	__asm __volatile("mrc p6, 0, %0, c3, c3, 0"
+	    : "=r" (ret));
+	return (ret);
+}
+
+/* Read the interrupt control register */
+/* 0 masked, 1 unmasked */
+static __inline
+uint32_t intctl0_read(void)
+{
+	uint32_t ret;
+
+	__asm __volatile("mrc p6, 0, %0, c0, c4, 0"
+	    : "=r" (ret));
+	return (ret);
+}
+
+static __inline
+uint32_t intctl1_read(void)
+{
+	uint32_t ret;
+
+	__asm __volatile("mrc p6, 0, %0, c1, c4, 0"
+	    : "=r" (ret));
+	return (ret);
+}
+
+static __inline
+uint32_t intctl2_read(void)
+{
+	uint32_t ret;
+
+	__asm __volatile("mrc p6, 0, %0, c2, c4, 0"
+	    : "=r" (ret));
+	return (ret);
+}
+
+static __inline
+uint32_t intctl3_read(void)
+{
+	uint32_t ret;
+
+	__asm __volatile("mrc p6, 0, %0, c3, c4, 0"
+	    : "=r" (ret));
+	return (ret);
+}
+
+/* Write the interrupt control register */
+
+static __inline
+void intctl0_write(uint32_t val)
+{
+
+	__asm __volatile("mcr p6, 0, %0, c0, c4, 0"
+	    : : "r" (val));
+}
+
+static __inline
+void intctl1_write(uint32_t val)
+{
+
+	__asm __volatile("mcr p6, 0, %0, c1, c4, 0"
+	    : : "r" (val));
+}
+
+static __inline
+void intctl2_write(uint32_t val)
+{
+
+	__asm __volatile("mcr p6, 0, %0, c2, c4, 0"
+	    : : "r" (val));
+}
+
+static __inline
+void intctl3_write(uint32_t val)
+{
+
+	__asm __volatile("mcr p6, 0, %0, c3, c4, 0"
+	    : : "r" (val));
+}
+
+/* Read the interrupt steering register */
+/* 0 IRQ 1 FIQ */
+static __inline
+uint32_t intstr0_read(void)
+{
+	uint32_t ret;
+
+	__asm __volatile("mrc p6, 0, %0, c0, c5, 0"
+	    : "=r" (ret));
+	return (ret);
+}
+
+static __inline
+uint32_t intstr1_read(void)
+{
+	uint32_t ret;
+
+	__asm __volatile("mrc p6, 0, %0, c1, c5, 0"
+	    : "=r" (ret));
+	return (ret);
+}
+
+static __inline
+uint32_t intstr2_read(void)
+{
+	uint32_t ret;
+
+	__asm __volatile("mrc p6, 0, %0, c2, c5, 0"
+	    : "=r" (ret));
+	return (ret);
+}
+
+static __inline
+uint32_t intstr3_read(void)
+{
+	uint32_t ret;
+
+	__asm __volatile("mrc p6, 0, %0, c3, c5, 0"
+	    : "=r" (ret));
+	return (ret);
+}
+
+/* Write the interrupt steering register */
+
+static __inline
+void intstr0_write(uint32_t val)
+{
+
+	__asm __volatile("mcr p6, 0, %0, c0, c5, 0"
+	    : : "r" (val));
+}
+
+static __inline
+void intstr1_write(uint32_t val)
+{
+
+	__asm __volatile("mcr p6, 0, %0, c1, c5, 0"
+	    : : "r" (val));
+}
+
+static __inline
+void intstr2_write(uint32_t val)
+{
+
+	__asm __volatile("mcr p6, 0, %0, c2, c5, 0"
+	    : : "r" (val));
+}
+
+static __inline
+void intstr3_write(uint32_t val)
+{
+
+	__asm __volatile("mcr p6, 0, %0, c3, c5, 0"
+	    : : "r" (val));
+}
+
+void
+cpu_reset(void)
+{
+
+	disable_interrupts(I32_bit);
+	/* XXX: Use the watchdog to reset for now */
+	__asm __volatile("mcr p6, 0, %0, c8, c9, 0\n"
+	    		 "mcr p6, 0, %1, c7, c9, 0\n"
+			 "mcr p6, 0, %2, c7, c9, 0\n"
+	    : : "r" (1), "r" (WDTCR_ENABLE1), "r" (WDTCR_ENABLE2));
+	while (1);
+}
+
+void
+arm_mask_irq(uintptr_t nb)
+{
+
+	if (nb < 32) {
+		intr_enabled0 &= ~(1 << nb);
+		intctl0_write(intr_enabled0);
+	} else if (nb < 64) {
+		intr_enabled1 &= ~(1 << (nb - 32));
+		intctl1_write(intr_enabled1);
+	} else if (nb < 96) {
+		intr_enabled2 &= ~(1 << (nb - 64));
+		intctl2_write(intr_enabled2);
+	} else {
+		intr_enabled3 &= ~(1 << (nb - 96));
+		intctl3_write(intr_enabled3);
+	}
+}
+
+void
+arm_unmask_irq(uintptr_t nb)
+{
+	if (nb < 32) {
+		intr_enabled0 |= (1 << nb);
+		intctl0_write(intr_enabled0);
+	} else if (nb < 64) {
+		intr_enabled1 |= (1 << (nb - 32));
+		intctl1_write(intr_enabled1);
+	} else if (nb < 96) {
+		intr_enabled2 |= (1 << (nb - 64));
+		intctl2_write(intr_enabled2);
+	} else {
+		intr_enabled3 |= (1 << (nb - 96));
+		intctl3_write(intr_enabled3);
+	}
+}
+
+int
+arm_get_next_irq(void)
+{
+	uint32_t val;
+	val = intpnd0_read() & intr_enabled0;
+	if (val)
+		return (ffs(val) - 1);
+	val = intpnd1_read() & intr_enabled1;
+	if (val)
+		return (32 + ffs(val) - 1);
+	val = intpnd2_read() & intr_enabled2;
+	if (val)
+		return (64 + ffs(val) - 1);
+	val = intpnd3_read() & intr_enabled3;
+	if (val)
+		return (96 + ffs(val) - 1);
+	return (-1);
+}
+
+int
+bus_dma_get_range_nb(void)
+{
+	return (0);
+}
+
+struct arm32_dma_range *
+bus_dma_get_range(void)
+{
+	return (NULL);
+}
+
+static int
+i81342_probe(device_t dev)
+{
+	unsigned int freq;
+
+	freq = *(volatile unsigned int *)(IOP34X_VADDR + IOP34X_PFR);
+
+	switch (freq & IOP34X_FREQ_MASK) {
+	case IOP34X_FREQ_600:
+		device_set_desc(dev, "Intel 81342 600MHz");
+		break;
+	case IOP34X_FREQ_667:
+		device_set_desc(dev, "Intel 81342 667MHz");
+		break;
+	case IOP34X_FREQ_800:
+		device_set_desc(dev, "Intel 81342 800MHz");
+		break;
+	case IOP34X_FREQ_833:
+		device_set_desc(dev, "Intel 81342 833MHz");
+		break;
+	case IOP34X_FREQ_1000:
+		device_set_desc(dev, "Intel 81342 1000MHz");
+		break;
+	case IOP34X_FREQ_1200:
+		device_set_desc(dev, "Intel 81342 1200MHz");
+		break;
+	default:
+		device_set_desc(dev, "Intel 81342 unknown frequency");
+		break;
+	}
+	return (0);
+}
+
+static void
+i81342_identify(driver_t *driver, device_t parent)
+{
+	
+	BUS_ADD_CHILD(parent, 0, "iq", 0);
+}
+
+static int
+i81342_attach(device_t dev)
+{
+	struct i81342_softc *sc = device_get_softc(dev);
+	uint32_t esstrsr;
+
+	i81342_bs_init(&i81342_bs_tag, sc);
+	sc->sc_st = &i81342_bs_tag;
+	sc->sc_sh = IOP34X_VADDR;
+	esstrsr = bus_space_read_4(sc->sc_st, sc->sc_sh, IOP34X_ESSTSR0);
+	sc->sc_atux_sh = IOP34X_ATUX_ADDR(esstrsr) - IOP34X_HWADDR +
+	    IOP34X_VADDR;
+	sc->sc_atue_sh = IOP34X_ATUE_ADDR(esstrsr) - IOP34X_HWADDR +
+	    IOP34X_VADDR;
+	/* Disable all interrupts. */
+	intctl0_write(0);
+	intctl1_write(0);
+	intctl2_write(0);
+	intctl3_write(0);
+	/* Defaults to IRQ */
+	intstr0_write(0);
+	intstr1_write(0);
+	intstr2_write(0);
+	intstr3_write(0);
+	sc->sc_irq_rman.rm_type = RMAN_ARRAY;
+	sc->sc_irq_rman.rm_descr = "i81342 IRQs";
+	if (rman_init(&sc->sc_irq_rman) != 0 ||
+	    rman_manage_region(&sc->sc_irq_rman, 0, 127) != 0)
+		panic("i81342_attach: failed to set up IRQ rman");
+
+	device_add_child(dev, "obio", 0);
+	device_add_child(dev, "itimer", 0);
+	device_add_child(dev, "iopwdog", 0);
+	device_add_child(dev, "pcib", 0);
+	device_add_child(dev, "pcib", 1);
+	bus_generic_probe(dev);
+	bus_generic_attach(dev);
+	return (0);
+}
+
+static struct resource *
+i81342_alloc_resource(device_t dev, device_t child, int type, int *rid,
+    u_long start, u_long end, u_long count, u_int flags)
+{
+	struct i81342_softc *sc = device_get_softc(dev);
+	struct resource *rv;
+
+	if (type == SYS_RES_IRQ) {
+		rv = rman_reserve_resource(&sc->sc_irq_rman,
+		    start, end, count, flags, child);
+		if (rv != NULL)
+			rman_set_rid(rv, *rid);
+		return (rv);
+	}
+	
+	return (NULL);
+}
+
+static int
+i81342_setup_intr(device_t dev, device_t child, struct resource *ires, 
+    int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 
+    void **cookiep)
+{
+	
+
+	BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, filt, intr,
+	    arg, cookiep);
+	arm_unmask_irq(rman_get_start(ires));
+	return (0);
+}
+
+static int
+i81342_teardown_intr(device_t dev, device_t child, struct resource *res,
+    void *cookie)
+{
+	return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie));
+}
+
+static device_method_t i81342_methods[] = {
+	DEVMETHOD(device_probe, i81342_probe),
+	DEVMETHOD(device_attach, i81342_attach),
+	DEVMETHOD(device_identify, i81342_identify),
+	DEVMETHOD(bus_alloc_resource, i81342_alloc_resource),
+	DEVMETHOD(bus_setup_intr, i81342_setup_intr),
+	DEVMETHOD(bus_teardown_intr, i81342_teardown_intr),
+	{0, 0},
+};
+
+static driver_t i81342_driver = {
+	"iq",
+	i81342_methods,
+	sizeof(struct i81342_softc),
+};
+static devclass_t i81342_devclass;
+
+DRIVER_MODULE(iq, nexus, i81342_driver, i81342_devclass, 0, 0);
diff --git a/sys/arm/xscale/i8134x/i81342_mcu.c b/sys/arm/xscale/i8134x/i81342_mcu.c
new file mode 100644
index 0000000..40afe98
--- /dev/null
+++ b/sys/arm/xscale/i8134x/i81342_mcu.c
@@ -0,0 +1,57 @@
+/*-
+ * Copyright (c) 2006 Olivier Houchard
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/bus.h>
+
+#include <machine/bus.h>
+#include <arm/xscale/i8134x/i81342reg.h>
+#include <arm/xscale/i8134x/i81342var.h>
+
+void
+i81342_sdram_bounds(bus_space_tag_t bt, bus_space_handle_t bh, 
+    vm_paddr_t *start, vm_size_t *size)
+{
+	uint32_t reg;
+	int bank_nb;
+
+	reg = bus_space_read_4(bt, bh, SMC_SDBR);
+	*start = (reg & SMC_SDBR_BASEADDR_MASK);
+	reg = bus_space_read_4(bt, bh, SMC_SBSR);
+	if (reg & SMC_SBSR_BANK_NB)
+		bank_nb = 1;
+	else
+		bank_nb = 2;
+	
+	*size = (reg & SMC_SBSR_BANK_SZ_MASK) * bank_nb;
+}
diff --git a/sys/arm/xscale/i8134x/i81342_pci.c b/sys/arm/xscale/i8134x/i81342_pci.c
new file mode 100644
index 0000000..8c79241
--- /dev/null
+++ b/sys/arm/xscale/i8134x/i81342_pci.c
@@ -0,0 +1,542 @@
+/*-
+ * Copyright (c) 2006 Olivier Houchard
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/types.h>
+#include <sys/rman.h>
+
+#include <machine/bus.h>
+#include <machine/cpu.h>
+#include <machine/pcb.h>
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm_extern.h>
+#include <machine/pmap.h>
+
+#include <arm/xscale/i8134x/i81342reg.h>
+#include <arm/xscale/i8134x/i81342var.h>
+
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcib_private.h>
+#include "pcib_if.h"
+
+#include <dev/pci/pcireg.h>
+
+static pcib_read_config_t i81342_pci_read_config;
+static pcib_write_config_t i81342_pci_write_config;
+
+static int
+i81342_pci_probe(device_t dev)
+{
+	struct i81342_pci_softc *sc;
+	
+	sc = device_get_softc(dev);
+	if (device_get_unit(dev) == 0) {
+		device_set_desc(dev, "i81342 PCI-X bus");
+		sc->sc_is_atux = 1;
+	} else {
+		device_set_desc(dev, "i81342 PCIe bus");
+		sc->sc_is_atux = 0;
+	}
+	return (0);
+}
+
+#define PCI_MAPREG_MEM_PREFETCHABLE_MASK	0x00000008
+#define PCI_MAPREG_MEM_TYPE_64BIT		0x00000004
+
+static int
+i81342_pci_attach(device_t dev)
+{
+	struct i81342_softc *parent_sc;
+	struct i81342_pci_softc *sc;
+	uint32_t memsize, memstart;
+	uint32_t reg;
+	int func;
+	uint32_t busno;
+
+	sc = device_get_softc(dev);
+	parent_sc = device_get_softc(device_get_parent(dev));
+	sc->sc_atu_sh = sc->sc_is_atux ? parent_sc->sc_atux_sh :
+	    parent_sc->sc_atue_sh;
+	sc->sc_st = parent_sc->sc_st;
+	if (bus_space_read_4(sc->sc_st, parent_sc->sc_sh, IOP34X_ESSTSR0)
+	    & IOP34X_INT_SEL_PCIX) {
+		if (sc->sc_is_atux)
+			func = 5;
+		else
+			func = 0;
+	} else {
+		if (sc->sc_is_atux)
+			func = 0;
+		else
+			func = 5;
+	}
+	i81342_io_bs_init(&sc->sc_pciio, sc);
+	i81342_mem_bs_init(&sc->sc_pcimem, sc);
+	i81342_sdram_bounds(sc->sc_st, IOP34X_VADDR, &memstart, &memsize);
+	if (sc->sc_is_atux) {
+		reg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCSR);
+		if (reg & ATUX_P_RSTOUT) {
+			bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_PCSR,
+			    reg &~ ATUX_P_RSTOUT);
+			DELAY(200);
+		}
+	}
+	/* Setup the Inbound windows. */
+	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IABAR0, 0);
+	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IAUBAR0, 0);
+	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR0, 0);
+
+	/* Set the mapping Physical address <=> PCI address */
+	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IABAR1,
+	    memstart | PCI_MAPREG_MEM_PREFETCHABLE_MASK |
+	    PCI_MAPREG_MEM_TYPE_64BIT);
+	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IAUBAR1, 0);
+	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR1, ~(memsize - 1)
+	     &~(0xfff));
+	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR1, memstart);
+	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IAUTVR1, 0);
+
+	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IABAR2, 0);
+	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IAUBAR2, 0);
+	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR2, 0);
+
+	/* Setup the Outbound IO Bar */
+	if (sc->sc_is_atux)
+		bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OIOBAR,
+		    (IOP34X_PCIX_OIOBAR >> 4) | func);
+	else
+		bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OIOBAR,
+		    (IOP34X_PCIE_OIOBAR >> 4) | func);
+
+	/* Setup the Outbound windows */
+	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OUMBAR0, 0);
+	if (sc->sc_is_atux)
+		bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OUMBAR1,
+		    (IOP34X_PCIX_OMBAR >> 32) | (func << ATU_OUMBAR_FUNC) |
+		    ATU_OUMBAR_EN);
+	else
+		bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OUMBAR1,
+		    (IOP34X_PCIE_OMBAR >> 32) | (func << ATU_OUMBAR_FUNC) |
+		    ATU_OUMBAR_EN);
+	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OUMWTVR1, 0);
+	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OUMBAR2, 0);
+	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OUMBAR3, 0);
+
+	/* Enable the outbound windows. */
+	reg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_CR);
+	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_CR,
+	    reg | ATU_CR_OUT_EN);
+	
+	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ISR,
+	    bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_ISR) & ATUX_ISR_ERRMSK);
+	/*
+	 * Enable bus mastering, memory access, SERR, and parity
+	 * checking on the ATU.
+	 */
+	if (sc->sc_is_atux) {
+		busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
+		busno = PCIXSR_BUSNO(busno);
+	} else {
+		busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCSR);
+		busno = PCIE_BUSNO(busno);
+	}
+	reg = bus_space_read_2(sc->sc_st, sc->sc_atu_sh, ATU_CMD);
+	reg |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_PERRESPEN |
+	    PCIM_CMD_SERRESPEN;
+	bus_space_write_2(sc->sc_st, sc->sc_atu_sh, ATU_CMD, reg);
+	sc->sc_busno = busno;
+	/* Initialize memory and i/o rmans. */
+	sc->sc_io_rman.rm_type = RMAN_ARRAY;
+	sc->sc_io_rman.rm_descr = "I81342 PCI I/O Ports";
+	if (rman_init(&sc->sc_io_rman) != 0 ||
+		rman_manage_region(&sc->sc_io_rman, 
+		sc->sc_is_atux ? IOP34X_PCIX_OIOBAR_VADDR :
+		IOP34X_PCIE_OIOBAR_VADDR,
+		(sc->sc_is_atux ? IOP34X_PCIX_OIOBAR_VADDR :
+		IOP34X_PCIE_OIOBAR_VADDR) + IOP34X_OIOBAR_SIZE) != 0) {
+		panic("i80321_pci_probe: failed to set up I/O rman");
+	}
+	sc->sc_mem_rman.rm_type = RMAN_ARRAY;
+	sc->sc_mem_rman.rm_descr = "I81342 PCI Memory";
+	if (rman_init(&sc->sc_mem_rman) != 0 ||
+	    rman_manage_region(&sc->sc_mem_rman, 
+	    0, 0xffffffff) != 0) {
+		panic("i81342_pci_attach: failed to set up memory rman");
+	}
+	sc->sc_irq_rman.rm_type = RMAN_ARRAY;
+	sc->sc_irq_rman.rm_descr = "i81342 PCI IRQs";
+	if (sc->sc_is_atux) {
+		if (rman_init(&sc->sc_irq_rman) != 0 ||
+		    rman_manage_region(&sc->sc_irq_rman, ICU_INT_XINT0, 
+		    ICU_INT_XINT3) != 0)
+			panic("i83142_pci_attach: failed to set up IRQ rman");
+	} else {
+		if (rman_init(&sc->sc_irq_rman) != 0 ||
+		    rman_manage_region(&sc->sc_irq_rman, ICU_INT_ATUE_MA, 
+		    ICU_INT_ATUE_MD) != 0)
+			panic("i81342_pci_attach: failed to set up IRQ rman");
+
+	}
+	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ISR,
+	    bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_ISR) & ATUX_ISR_ERRMSK);
+	device_add_child(dev, "pci", busno);
+	return (bus_generic_attach(dev));
+}
+
+static int
+i81342_pci_maxslots(device_t dev)
+{
+
+	return (PCI_SLOTMAX);
+}
+
+static void
+i81342_pci_conf_setup(struct i81342_pci_softc *sc, int bus, int slot, int func,
+    int reg, uint32_t *addr)
+{
+	uint32_t busno;
+
+	if (sc->sc_is_atux) {
+		busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
+		busno = PCIXSR_BUSNO(busno);
+	} else {
+		busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCSR);
+		busno = PCIE_BUSNO(busno);
+	}
+	bus &= 0xff;
+	slot &= 0x1f;
+	func &= 0x7;
+	if (sc->sc_is_atux) {
+		if (busno == bus)
+			*addr = (1 << (slot + 16)) | (slot << 11) |
+			    (func << 8) | reg;
+		else
+			*addr = (bus << 16) | (slot << 11) | (func << 11) | 
+			    reg | 1;
+	} else {
+		*addr = (bus << 24) | (slot << 19) | (func << 16) | reg;
+		if (bus != busno)
+			*addr |= 1;
+	}
+}
+
+static u_int32_t
+i81342_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func,
+    u_int reg, int bytes)
+{
+	struct i81342_pci_softc *sc = device_get_softc(dev);
+	uint32_t addr;
+	uint32_t ret = 0;
+	uint32_t isr;
+	int err = 0;
+	vm_offset_t va;
+
+	i81342_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr);
+	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, sc->sc_is_atux ?
+	    ATUX_OCCAR : ATUE_OCCAR, addr);
+	if (sc->sc_is_atux)
+		va = sc->sc_atu_sh + ATUX_OCCDR;
+	else
+		va = sc->sc_atu_sh + ATUE_OCCDR;
+	switch (bytes) {
+	case 1:
+		err = badaddr_read((void*)(va + (reg & 3)), 1, &ret);
+		break;
+	case 2:
+		err = badaddr_read((void*)(va + (reg & 3)), 2, &ret);
+		break;
+	case 4:
+		err = badaddr_read((void *)(va) , 4, &ret);
+		break;
+	default:
+		printf("i81342_read_config: invalid size %d\n", bytes);
+		ret = -1;
+	}
+	if (err) {
+		isr = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_ISR);
+		if (sc->sc_is_atux)
+			isr &= ATUX_ISR_ERRMSK;
+		else
+			isr &= ATUE_ISR_ERRMSK;
+		bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ISR, isr);
+		ret = -1;
+	}
+
+	return (ret);
+}
+
+static void
+i81342_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func, 
+    u_int reg, u_int32_t data, int bytes)
+{
+	struct i81342_pci_softc *sc = device_get_softc(dev);
+	uint32_t addr;
+	vm_offset_t va;
+
+	i81342_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr);
+	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, sc->sc_is_atux ?
+	    ATUX_OCCAR : ATUE_OCCAR, addr);
+	va = sc->sc_is_atux ? ATUX_OCCDR : ATUE_OCCDR;
+		switch (bytes) {
+	case 1:
+		bus_space_write_1(sc->sc_st, sc->sc_atu_sh, va + (reg & 3)
+		    , data);
+		break;
+	case 2:
+		bus_space_write_2(sc->sc_st, sc->sc_atu_sh, va + (reg & 3)
+		    , data);
+		break;
+	case 4:
+		bus_space_write_4(sc->sc_st, sc->sc_atu_sh, va, data);
+		break;
+	default:
+		printf("i81342_pci_write_config: Invalid size : %d\n", bytes);
+	}
+
+
+}
+
+static struct resource *
+i81342_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
+   u_long start, u_long end, u_long count, u_int flags)
+{
+	struct i81342_pci_softc *sc = device_get_softc(bus);	
+	struct resource *rv;
+	struct rman *rm;
+	bus_space_tag_t bt = NULL;
+	bus_space_handle_t bh = 0;
+
+	switch (type) {
+	case SYS_RES_IRQ:
+		rm = &sc->sc_irq_rman;
+		break;
+	case SYS_RES_MEMORY:
+		rm = &sc->sc_mem_rman;
+		bt = &sc->sc_pcimem;
+		bh = 0;
+		break;
+	case SYS_RES_IOPORT:
+		rm = &sc->sc_io_rman;
+		bt = &sc->sc_pciio;
+		bh = sc->sc_is_atux ? IOP34X_PCIX_OIOBAR_VADDR :
+		    IOP34X_PCIE_OIOBAR_VADDR;
+		start += bh;
+		end += bh;
+		break;
+	default:
+		return (NULL);
+	}
+
+	rv = rman_reserve_resource(rm, start, end, count, flags, child);
+	if (rv == NULL)
+		return (NULL);
+	rman_set_rid(rv, *rid);
+	if (type != SYS_RES_IRQ) {
+		if (type == SYS_RES_MEMORY)
+			bh += (rman_get_start(rv));
+		rman_set_bustag(rv, bt);
+		rman_set_bushandle(rv, bh);
+		if (flags & RF_ACTIVE) {
+			if (bus_activate_resource(child, type, *rid, rv)) {
+				rman_release_resource(rv);
+				return (NULL);
+			}
+		} 
+	}
+	return (rv);
+
+
+	return (NULL);
+}
+
+static int
+i81342_pci_activate_resource(device_t bus, device_t child, int type, int rid,
+    struct resource *r)
+{
+	u_long p;
+	int error;
+	
+	if (type == SYS_RES_MEMORY) {
+		error = bus_space_map(rman_get_bustag(r),
+		    rman_get_bushandle(r), rman_get_size(r), 0, &p);
+		if (error)
+			return (error);
+		rman_set_bushandle(r, p);
+	
+	}
+	return (rman_activate_resource(r));
+}
+
+static int
+i81342_pci_setup_intr(device_t dev, device_t child, struct resource *ires,
+    int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
+    void **cookiep)
+{
+
+	return (BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags,
+	    filt, intr, arg, cookiep));
+}
+
+
+
+static int
+i81342_pci_teardown_intr(device_t dev, device_t child, struct resource *res,
+    void *cookie)
+{
+	return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie));
+}
+
+static int
+i81342_pci_route_interrupt(device_t pcib, device_t dev, int pin)
+{
+	struct i81342_pci_softc *sc;
+	int device;
+	
+	device = pci_get_slot(dev);
+	sc = device_get_softc(pcib);
+	/* XXX: Is board specific */
+	if (sc->sc_is_atux) {
+		/* PCI-X */
+		switch(device) {
+		case 1:
+			switch (pin) {
+			case 1:
+				return (ICU_INT_XINT1);
+			case 2:
+				return (ICU_INT_XINT2);
+			case 3:
+				return (ICU_INT_XINT3);
+			case 4:
+				return (ICU_INT_XINT0);
+			default:
+				break;
+			}
+		case 2:
+			switch (pin) {
+			case 1:
+				return (ICU_INT_XINT2);
+			case 2:
+				return (ICU_INT_XINT3);
+			case 3:
+				return (ICU_INT_XINT2);
+			case 4:
+				return (ICU_INT_XINT3);
+			default:
+				break;
+			}
+		}
+		
+	} else {
+		switch (pin) {
+		case 1:
+			return (ICU_INT_ATUE_MA);
+		case 2:
+			return (ICU_INT_ATUE_MB);
+		case 3:
+			return (ICU_INT_ATUE_MC);
+		case 4:
+			return (ICU_INT_ATUE_MD);
+		default:
+			break;
+		}
+	}
+	printf("Warning: couldn't map %s IRQ for device %d pin %d\n",
+	    sc->sc_is_atux ? "PCI-X" : "PCIe", device, pin);
+	return (-1);
+}
+
+static int
+i81342_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
+{
+	struct i81342_pci_softc *sc = device_get_softc(dev);
+	switch (which) {
+	case PCIB_IVAR_BUS:
+
+		*result = sc->sc_busno;
+		return (0);
+		
+	}
+	return (ENOENT);
+}
+
+static int
+i81342_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
+{
+	struct i81342_pci_softc * sc = device_get_softc(dev);
+
+	switch (which) {
+	case PCIB_IVAR_BUS:
+		sc->sc_busno = result;
+		return (0);
+	}
+	return (ENOENT);
+}
+
+static device_method_t i81342_pci_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		i81342_pci_probe),
+	DEVMETHOD(device_attach,	i81342_pci_attach),
+	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
+	DEVMETHOD(device_suspend,	bus_generic_suspend),
+	DEVMETHOD(device_resume,	bus_generic_resume),
+
+	/* Bus interface */
+	DEVMETHOD(bus_print_child,	bus_generic_print_child),
+	DEVMETHOD(bus_read_ivar,	i81342_read_ivar),
+	DEVMETHOD(bus_write_ivar,	i81342_write_ivar),
+	DEVMETHOD(bus_alloc_resource,	i81342_pci_alloc_resource),
+	DEVMETHOD(bus_release_resource,	bus_generic_release_resource),
+	DEVMETHOD(bus_activate_resource, i81342_pci_activate_resource),
+	DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
+	DEVMETHOD(bus_setup_intr,	i81342_pci_setup_intr),
+	DEVMETHOD(bus_teardown_intr,	i81342_pci_teardown_intr),
+
+	/* pcib interface */
+	DEVMETHOD(pcib_maxslots,	i81342_pci_maxslots),
+	DEVMETHOD(pcib_read_config,	i81342_pci_read_config),
+	DEVMETHOD(pcib_write_config,	i81342_pci_write_config),
+	DEVMETHOD(pcib_route_interrupt,	i81342_pci_route_interrupt),
+
+	{0, 0}
+};
+
+static driver_t i81342_pci_driver = {
+	"pcib",
+	i81342_pci_methods,
+	sizeof(struct i81342_pci_softc),
+};
+
+static devclass_t i81342_pci_devclass;
+
+DRIVER_MODULE(ipci, iq, i81342_pci_driver, i81342_pci_devclass, 0, 0);
diff --git a/sys/arm/xscale/i8134x/i81342_space.c b/sys/arm/xscale/i8134x/i81342_space.c
new file mode 100644
index 0000000..50865f17
--- /dev/null
+++ b/sys/arm/xscale/i8134x/i81342_space.c
@@ -0,0 +1,345 @@
+/*	$NetBSD: i80321_space.c,v 1.6 2003/10/06 15:43:35 thorpej Exp $	*/
+
+/*-
+ * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * bus_space functions for i81342 I/O Processor.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/malloc.h>
+
+#include <machine/pcb.h>
+
+#include <vm/vm.h>
+#include <vm/vm_kern.h>
+#include <vm/pmap.h>
+#include <vm/vm_page.h>
+#include <vm/vm_extern.h>
+
+#include <machine/bus.h>
+
+#include <arm/xscale/i8134x/i81342reg.h>
+#include <arm/xscale/i8134x/i81342var.h>
+
+/* Prototypes for all the bus_space structure functions */
+bs_protos(i81342);
+bs_protos(i81342_io);
+bs_protos(i81342_mem);
+bs_protos(generic);
+bs_protos(generic_armv4);
+
+/*
+ * Template bus_space -- copied, and the bits that are NULL are
+ * filled in.
+ */
+const struct bus_space i81342_bs_tag_template = {
+	/* cookie */
+	(void *) 0,
+
+	/* mapping/unmapping */
+	NULL,
+	NULL,
+	i81342_bs_subregion,
+
+	/* allocation/deallocation */
+	NULL,
+	NULL,
+
+	/* barrier */
+	i81342_bs_barrier,
+
+	/* read (single) */
+	generic_bs_r_1,
+	generic_armv4_bs_r_2,
+	generic_bs_r_4,
+	NULL,
+
+	/* read multiple */
+	generic_bs_rm_1,
+	generic_armv4_bs_rm_2,
+	generic_bs_rm_4,
+	NULL,
+
+	/* read region */
+	generic_bs_rr_1,
+	generic_armv4_bs_rr_2,
+	generic_bs_rr_4,
+	NULL,
+
+	/* write (single) */
+	generic_bs_w_1,
+	generic_armv4_bs_w_2,
+	generic_bs_w_4,
+	NULL,
+
+	/* write multiple */
+	generic_bs_wm_1,
+	generic_armv4_bs_wm_2,
+	generic_bs_wm_4,
+	NULL,
+
+	/* write region */
+	NULL,
+	generic_armv4_bs_wr_2,
+	generic_bs_wr_4,
+	NULL,
+
+	/* set multiple */
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+
+	/* set region */
+	NULL,
+	generic_armv4_bs_sr_2,
+	generic_bs_sr_4,
+	NULL,
+
+	/* copy */
+	NULL,
+	generic_armv4_bs_c_2,
+	NULL,
+	NULL,
+
+	/* read (single) stream */
+	generic_bs_r_1,
+	generic_armv4_bs_r_2,
+	generic_bs_r_4,
+	NULL,
+
+	/* read multiple stream */
+	generic_bs_rm_1,
+	generic_armv4_bs_rm_2,
+	generic_bs_rm_4,
+	NULL,
+
+	/* read region stream */
+	generic_bs_rr_1,
+	generic_armv4_bs_rr_2,
+	generic_bs_rr_4,
+	NULL,
+
+	/* write (single) stream */
+	generic_bs_w_1,
+	generic_armv4_bs_w_2,
+	generic_bs_w_4,
+	NULL,
+
+	/* write multiple stream */
+	generic_bs_wm_1,
+	generic_armv4_bs_wm_2,
+	generic_bs_wm_4,
+	NULL,
+
+	/* write region stream */
+	NULL,
+	generic_armv4_bs_wr_2,
+	generic_bs_wr_4,
+	NULL,
+};
+
+void
+i81342_bs_init(bus_space_tag_t bs, void *cookie)
+{
+
+	*bs = i81342_bs_tag_template;
+	bs->bs_cookie = cookie;
+}
+
+void
+i81342_io_bs_init(bus_space_tag_t bs, void *cookie)
+{
+
+	*bs = i81342_bs_tag_template;
+	bs->bs_cookie = cookie;
+
+	bs->bs_map = i81342_io_bs_map;
+	bs->bs_unmap = i81342_io_bs_unmap;
+	bs->bs_alloc = i81342_io_bs_alloc;
+	bs->bs_free = i81342_io_bs_free;
+
+}
+
+void
+i81342_mem_bs_init(bus_space_tag_t bs, void *cookie)
+{
+
+	*bs = i81342_bs_tag_template;
+	bs->bs_cookie = cookie;
+
+	bs->bs_map = i81342_mem_bs_map;
+	bs->bs_unmap = i81342_mem_bs_unmap;
+	bs->bs_alloc = i81342_mem_bs_alloc;
+	bs->bs_free = i81342_mem_bs_free;
+
+}
+
+/* *** Routines shared by i81342, PCI IO, and PCI MEM. *** */
+
+int
+i81342_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset,
+    bus_size_t size, bus_space_handle_t *nbshp)
+{
+
+	*nbshp = bsh + offset;
+	return (0);
+}
+
+void
+i81342_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset,
+    bus_size_t len, int flags)
+{
+
+	/* Nothing to do. */
+}
+
+/* *** Routines for PCI IO. *** */
+
+int
+i81342_io_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flags,
+    bus_space_handle_t *bshp)
+{
+
+	*bshp = bpa;
+	return (0);
+}
+
+void
+i81342_io_bs_unmap(void *t, bus_space_handle_t h, bus_size_t size)
+{
+
+	/* Nothing to do. */
+}
+
+int
+i81342_io_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
+    bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
+    bus_addr_t *bpap, bus_space_handle_t *bshp)
+{
+
+	panic("i81342_io_bs_alloc(): not implemented");
+}
+
+void    
+i81342_io_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
+{
+
+	panic("i81342_io_bs_free(): not implemented");
+}
+
+
+/* *** Routines for PCI MEM. *** */
+extern int badaddr_read(void *, int, void *);
+static vm_offset_t allocable = 0xe1000000;
+int
+i81342_mem_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flags,
+    bus_space_handle_t *bshp)
+{
+	struct i81342_pci_softc *sc = (struct i81342_pci_softc *)t;
+	struct i81342_pci_map *tmp;
+	vm_offset_t addr, endaddr;
+	vm_paddr_t paddr;
+
+	/* Lookup to see if we already have a mapping at this address. */
+	tmp = sc->sc_pci_mappings;
+	while (tmp) {
+		if (tmp->paddr <= bpa && tmp->paddr + tmp->size >
+		    bpa + size) {
+			*bshp = bpa - tmp->paddr + tmp->vaddr;
+			return (0);
+		}
+		tmp = tmp->next;
+	}
+	addr = allocable;
+	endaddr = ((addr + size) &~ (0x1000000 - 1)) + 0x1000000;
+	if (endaddr >= IOP34X_VADDR)
+		panic("PCI virtual memory exhausted");
+	allocable = endaddr;
+	tmp = malloc(sizeof(*tmp), M_DEVBUF, M_WAITOK);
+	tmp->next = NULL;
+	paddr = bpa &~ (0x100000 - 1);
+	tmp->paddr = paddr;
+	tmp->vaddr = addr;
+	tmp->size = 0;
+	while (addr < endaddr) {
+		pmap_kenter_supersection(addr, paddr + (sc->sc_is_atux ?
+		    IOP34X_PCIX_OMBAR : IOP34X_PCIE_OMBAR), 0);
+		addr += 0x1000000;
+		paddr += 0x1000000;
+		tmp->size += 0x1000000;
+	}
+	tmp->next = sc->sc_pci_mappings;
+	sc->sc_pci_mappings = tmp;
+	*bshp = bpa - tmp->paddr + tmp->vaddr;
+	return (0);
+}
+
+void
+i81342_mem_bs_unmap(void *t, bus_space_handle_t h, bus_size_t size)
+{
+#if 0
+	vm_offset_t va, endva;
+
+	va = trunc_page((vm_offset_t)t);
+	endva = va + round_page(size);
+
+	/* Free the kernel virtual mapping. */
+	kmem_free(kernel_map, va, endva - va);
+#endif
+}
+
+int
+i81342_mem_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
+    bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
+    bus_addr_t *bpap, bus_space_handle_t *bshp)
+{
+
+	panic("i81342_mem_bs_alloc(): not implemented");
+}
+
+void    
+i81342_mem_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
+{
+
+	panic("i81342_mem_bs_free(): not implemented");
+}
diff --git a/sys/arm/xscale/i8134x/i81342reg.h b/sys/arm/xscale/i8134x/i81342reg.h
new file mode 100644
index 0000000..6380f00
--- /dev/null
+++ b/sys/arm/xscale/i8134x/i81342reg.h
@@ -0,0 +1,306 @@
+/*-
+ * Copyright (c) 2006 Olivier Houchard
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* $FreeBSD$ */
+
+#ifndef I83142_REG_H_
+#define I83142_REG_H_
+/* Physical Memory Map */
+/* 
+ * 0x000000000 - 0x07FFFFFFF SDRAM
+ * 0x090100000 - 0x0901FFFFF ATUe Outbound IO Window
+ * 0x0F0000000 - 0x0F1FFFFFF Flash
+ * 0x0F2000000 - 0x0F20FFFFF PCE1
+ * 0x0F3000000 - 0x0FFCFFFFF Compact Flash
+ * 0x0FFD00000 - 0x0FFDFFFFF MMR
+ * 0x0FFFB0000 - 0x0FFFBFFFF ATU-X Outbound I/O Window
+ * 0x0FFFD0000 - 0x0FFFDFFFF ATUe Outbound I/O Window
+ * 0x100000000 - 0x1FFFFFFFF ATU-X outbound Memory Translation Window
+ * 0x2FF000000 - 0x2FFFFFFFF ATUe Outbound Memory Translation Window
+ */
+
+#define IOP34X_VADDR		0xf0000000
+#define IOP34X_HWADDR		0xffd00000
+#define IOP34X_SIZE		0x100000
+
+#define IOP34X_PBBAR0		0x81588 /* PBI Base Address Register 0 */
+#define IOP34X_PBBAR0_ADDRMASK	0xfffff000
+#define IOP34X_PBBAR1		0x81590
+#define IOP34X_ESSTSR0		0x82188
+#define IOP34X_CONTROLLER_ONLY	(1 << 14)
+#define IOP34X_INT_SEL_PCIX	(1 << 15)
+#define IOP34X_PFR		0x82180 /* Processor Frequency Register */
+#define IOP34X_FREQ_MASK	((1 << 16) | (1 << 17) | (1 << 18))
+#define IOP34X_FREQ_600		(0)
+#define IOP34X_FREQ_667		(1 << 16)
+#define IOP34X_FREQ_800		(1 << 17)
+#define IOP34X_FREQ_833		((1 << 17) | (1 << 16))
+#define IOP34X_FREQ_1000	(1 << 18)
+#define IOP34X_FREQ_1200	((1 << 16) | (1 << 18))
+
+#define IOP34X_UART0_VADDR	IOP34X_VADDR + 0x82300
+#define IOP34X_UART0_HWADDR	IOP34X_HWADDR + 0x82300
+#define IOP34X_UART1_VADDR	IOP34X_VADDR + 0x82340
+#define IOP34X_UART1_HWADDR	IOP34X_HWADDR + 0x82340
+#define IOP34X_PBI_HWADDR	0xffd81580
+
+/* SDRAM Memory Controller */
+#define SMC_SDBR		0x8180c /* Base Register */
+#define SMC_SDBR_BASEADDR	(1 << 27)
+#define SMC_SDBR_BASEADDR_MASK	((1 << 27) | (1 << 28) | (1 << 29) | (1 << 30) \
+    				| (1 << 31))
+#define SMC_SDUBR		0x81810 /* Upper Base Register */
+#define SMC_SBSR		0x81814 /* SDRAM Bank Size Register */
+#define SMC_SBSR_BANK_NB	(1 << 2) /* Number of DDR Banks
+					   0 => 2 Banks
+					   1 => 1 Bank
+					   */
+#define SMC_SBSR_BANK_SZ	(1 << 27) /* SDRAM Bank Size :
+					   0x00000 Empty
+					   0x00001 128MB
+					   0x00010 256MB
+					   0x00100 512MB
+					   0x01000 1GB
+					   */
+#define SMC_SBSR_BANK_SZ_MASK	((1 << 27) | (1 << 28) | (1 << 29) | (1 << 30) \
+    				| (1 << 31))
+
+
+/* Two possible addresses for ATUe depending on configuration. */
+#define IOP34X_ATUE_ADDR(esstrsr) ((((esstrsr) & (IOP34X_CONTROLLER_ONLY | \
+    IOP34X_INT_SEL_PCIX)) == (IOP34X_CONTROLLER_ONLY | IOP34X_INT_SEL_PCIX)) ? \
+    0xffdc8000 : 0xffdcd000)
+
+/* Three possible addresses for ATU-X depending on configuration. */
+#define IOP34X_ATUX_ADDR(esstrsr) (!((esstrsr) & IOP34X_CONTROLLER_ONLY) ? \
+    0xffdcc000 : !((esstrsr) & IOP34X_INT_SEL_PCIX) ? 0xffdc8000 : 0xffdcd000)
+
+#define IOP34X_OIOBAR_SIZE		0x10000
+#define IOP34X_PCIX_OIOBAR		0xfffb0000
+#define IOP34X_PCIX_OIOBAR_VADDR	0xf01b0000
+#define IOP34X_PCIX_OMBAR		0x100000000
+#define IOP34X_PCIE_OIOBAR		0xfffd0000
+#define IOP34X_PCIE_OIOBAR_VADDR	0xf01d0000
+#define IOP34X_PCIE_OMBAR		0x200000000
+
+/* ATU Registers */
+/* Common for ATU-X and ATUe */
+#define ATU_VID		0x0000 /* ATU Vendor ID */
+#define ATU_DID		0x0002 /* ATU Device ID */
+#define ATU_CMD		0x0004 /* ATU Command Register */
+#define ATU_SR		0x0006 /* ATU Status Register */
+#define ATU_RID		0x0008 /* ATU Revision ID */
+#define ATU_CCR		0x0009 /* ATU Class Code */
+#define ATU_CLSR	0x000c /* ATU Cacheline Size */
+#define ATU_LT		0x000d /* ATU Latency Timer */
+#define ATU_HTR		0x000e /* ATU Header Type */
+#define ATU_BISTR	0x000f /* ATU BIST Register */
+#define ATU_IABAR0	0x0010 /* Inbound ATU Base Address register 0 */
+#define ATU_IAUBAR0	0x0014 /* Inbound ATU Upper Base Address Register 0 */
+#define ATU_IABAR1	0x0018 /* Inbound ATU Base Address Register 1 */
+#define ATU_IAUBAR1	0x001c /* Inbound ATU Upper Base Address Register 1 */
+#define ATU_IABAR2	0x0020 /* Inbound ATU Base Address Register 2 */
+#define ATU_IAUBAR2	0x0024 /* Inbound ATU Upper Base Address Register 2 */
+#define ATU_VSIR	0x002c /* ATU Subsystem Vendor ID Register */
+#define ATU_SIR		0x002e /* ATU Subsystem ID Register */
+#define ATU_ERBAR	0x0030 /* Expansion ROM Base Address Register */
+#define ATU_CAPPTR	0x0034 /* ATU Capabilities Pointer Register */
+#define ATU_ILR		0x003c /* ATU Interrupt Line Register */
+#define ATU_IPR		0x003d /* ATU Interrupt Pin Register */
+#define ATU_MGNT	0x003e /* ATU Minimum Grand Register */
+#define ATU_MLAT	0x003f /* ATU Maximum Latency Register */
+#define ATU_IALR0	0x0040 /* Inbound ATU Limit Register 0 */
+#define ATU_IATVR0	0x0044 /* Inbound ATU Translate Value Register 0 */
+#define ATU_IAUTVR0	0x0048 /* Inbound ATU Upper Translate Value Register 0*/
+#define ATU_IALR1	0x004c /* Inbound ATU Limit Register 1 */
+#define ATU_IATVR1	0x0050 /* Inbound ATU Translate Value Register 1 */
+#define ATU_IAUTVR1	0x0054 /* Inbound ATU Upper Translate Value Register 1*/
+#define ATU_IALR2	0x0058 /* Inbound ATU Limit Register 2 */
+#define ATU_IATVR2	0x005c /* Inbound ATU Translate Value Register 2 */
+#define ATU_IAUTVR2	0x0060 /* Inbound ATU Upper Translate Value Register 2*/
+#define ATU_ERLR	0x0064 /* Expansion ROM Limit Register */
+#define ATU_ERTVR	0x0068 /* Expansion ROM Translater Value Register */
+#define ATU_ERUTVR	0x006c /* Expansion ROM Upper Translate Value Register*/
+#define ATU_CR		0x0070 /* ATU Configuration Register */
+#define ATU_CR_OUT_EN	(1 << 1)
+#define ATU_PCSR	0x0074 /* PCI Configuration and Status Register */
+#define PCIE_BUSNO(x)	((x & 0xff000000) >> 24)
+#define ATUX_CORE_RST	((1 << 30) | (1 << 31)) /* Core Processor Reset */
+#define ATUX_P_RSTOUT	(1 << 21) /* Central Resource PCI Bus Reset */
+#define ATUE_CORE_RST	((1 << 9) | (1 << 8)) /* Core Processor Reset */
+#define ATU_ISR		0x0078 /* ATU Interrupt Status Register */
+#define ATUX_ISR_PIE	(1 << 18) /* PCI Interface error */
+#define ATUX_ISR_IBPR	(1 << 16) /* Internal Bus Parity Error */
+#define ATUX_ISR_DCE	(1 << 14) /* Detected Correctable error */
+#define ATUX_ISR_ISCE	(1 << 13) /* Initiated Split Completion Error Msg */
+#define ATUX_ISR_RSCE	(1 << 12) /* Received Split Completion Error Msg */
+#define ATUX_ISR_DPE	(1 << 9)  /* Detected Parity Error */
+#define ATUX_ISR_IBMA	(1 << 7)  /* Internal Bus Master Abort */
+#define ATUX_ISR_PMA	(1 << 3)  /* PCI Master Abort */
+#define ATUX_ISR_PTAM	(1 << 2)  /* PCI Target Abort (Master) */
+#define ATUX_ISR_PTAT	(1 << 1)  /* PCI Target Abort (Target) */
+#define ATUX_ISR_PMPE	(1 << 0)  /* PCI Master Parity Error */
+#define ATUX_ISR_ERRMSK	(ATUX_ISR_PIE | ATUX_ISR_IBPR | ATUX_ISR_DCE | \
+    ATUX_ISR_ISCE | ATUX_ISR_RSCE | ATUX_ISR_DPE | ATUX_ISR_IBMA | ATUX_ISR_PMA\
+    | ATUX_ISR_PTAM | ATUX_ISR_PTAT | ATUX_ISR_PMPE)
+#define ATUE_ISR_HON	(1 << 13) /* Halt on Error Interrupt */
+#define ATUE_ISR_RSE	(1 << 12) /* Root System Error Message */
+#define ATUE_ISR_REM	(1 << 11) /* Root Error Message */
+#define ATUE_ISR_PIE	(1 << 10) /* PCI Interface error */
+#define ATUE_ISR_CEM	(1 << 9)  /* Correctable Error Message */
+#define ATUE_ISR_UEM	(1 << 8)  /* Uncorrectable error message */
+#define ATUE_ISR_CRS	(1 << 7)  /* Received Configuration Retry Status */
+#define ATUE_ISR_IBMA	(1 << 5)  /* Internal Bus Master Abort */
+#define ATUE_ISR_DPE	(1 << 4)  /* Detected Parity Error Interrupt */
+#define ATUE_ISR_MAI	(1 << 3)  /* Received Master Abort Interrupt */
+#define ATUE_ISR_STAI	(1 << 2)  /* Signaled Target Abort Interrupt */
+#define ATUE_ISR_TAI	(1 << 1)  /* Received Target Abort Interrupt */
+#define ATUE_ISR_MDPE	(1 << 0)  /* Master Data Parity Error Interrupt */
+#define ATUE_ISR_ERRMSK	(ATUE_ISR_HON | ATUE_ISR_RSE | ATUE_ISR_REM | \
+    ATUE_ISR_PIE | ATUE_ISR_CEM | ATUE_ISR_UEM | ATUE_ISR_CRS | ATUE_ISR_IBMA |\
+    ATUE_ISR_DPE | ATUE_ISR_MAI | ATUE_ISR_STAI | ATUE_ISR_TAI | ATUE_ISR_MDPE)
+#define ATU_IMR		0x007c /* ATU Interrupt Mask Register */
+/* 0x0080 - 0x008f reserved */
+#define ATU_VPDCID	0x0090 /* VPD Capability Identifier Register */
+#define ATU_VPDNIP	0x0091 /* VPD Next Item Pointer Register */
+#define ATU_VPDAR	0x0092 /* VPD Address Register */
+#define ATU_VPDDR	0x0094 /* VPD Data Register */
+#define ATU_PMCID	0x0098 /* PM Capability Identifier Register */
+#define ATU_PMNIPR	0x0099 /* PM Next Item Pointer Register */
+#define ATU_PMCR	0x009a /* ATU Power Management Capabilities Register */
+#define ATU_PMCSR	0x009c /* ATU Power Management Control/Status Register*/
+#define ATU_MSICIR	0x00a0 /* MSI Capability Identifier Register */
+#define ATU_MSINIPR	0x00a1 /* MSI Next Item Pointer Register */
+#define ATU_MCR		0x00a2 /* Message Control Register */
+#define ATU_MAR		0x00a4 /* Message Address Register */
+#define ATU_MUAR	0x00a8 /* Message Upper Address Register */
+#define ATU_MDR		0x00ac /* Message Data Register */
+#define ATU_PCIXSR	0x00d4 /* PCI-X Status Register */
+#define PCIXSR_BUSNO(x)         (((x) & 0xff00) >> 8)
+#define ATU_IABAR3	0x0200 /* Inbound ATU Base Address Register 3 */
+#define ATU_IAUBAR3	0x0204 /* Inbound ATU Upper Base Address Register 3 */
+#define ATU_IALR3	0x0208 /* Inbound ATU Limit Register 3 */
+#define ATU_ITVR3	0x020c /* Inbound ATU Upper Translate Value Reg 3 */
+#define ATU_OIOBAR	0x0300 /* Outbound I/O Base Address Register */
+#define ATU_OIOWTVR	0x0304 /* Outbound I/O Window Translate Value Reg */
+#define ATU_OUMBAR0	0x0308 /* Outbound Upper Memory Window base addr reg 0*/
+#define ATU_OUMBAR_FUNC	(28)
+#define ATU_OUMBAR_EN	(1 << 31)
+#define ATU_OUMWTVR0	0x030c /* Outbound Upper 32bit Memory Window Translate Value Register 0 */
+#define ATU_OUMBAR1	0x0310 /* Outbound Upper Memory Window base addr reg1*/
+#define ATU_OUMWTVR1	0x0314 /* Outbound Upper 32bit Memory Window Translate Value Register 1 */
+#define ATU_OUMBAR2	0x0318 /* Outbound Upper Memory Window base addr reg2*/
+#define ATU_OUMWTVR2	0x031c /* Outbount Upper 32bit Memory Window Translate Value Register 2 */
+#define ATU_OUMBAR3	0x0320 /* Outbound Upper Memory Window base addr reg3*/
+#define ATU_OUMWTVR3	0x0324 /* Outbound Upper 32bit Memory Window Translate Value Register 3 */
+
+/* ATU-X specific */
+#define ATUX_OCCAR	0x0330 /* Outbound Configuration Cycle Address Reg */
+#define ATUX_OCCDR	0x0334 /* Outbound Configuration Cycle Data Reg */
+#define ATUX_OCCFN	0x0338 /* Outbound Configuration Cycle Function Number*/
+/* ATUe specific */
+#define ATUE_OCCAR	0x032c /* Outbound Configuration Cycle Address Reg */
+#define ATUE_OCCDR	0x0330 /* Outbound Configuration Cycle Data Reg */
+#define ATUE_OCCFN	0x0334 /* Outbound Configuration Cycle Function Number*/
+/* Interrupts */
+
+/* IINTRSRC0 */
+#define ICU_INT_ADMA0_EOT	(0) /* ADMA 0 End of transfer */
+#define ICU_INT_ADMA0_EOC	(1) /* ADMA 0 End of Chain */
+#define ICU_INT_ADMA1_EOT	(2) /* ADMA 1 End of transfer */
+#define ICU_INT_ADMA1_EOC	(3) /* ADMA 1 End of chain */
+#define ICU_INT_ADMA2_EOT	(4) /* ADMA 2 End of transfer */
+#define ICU_INT_ADMA2_EOC	(5) /* ADMA 2 end of chain */
+#define ICU_INT_WDOG		(6) /* Watchdog timer */
+/* 7 Reserved */
+#define ICU_INT_TIMER0		(8) /* Timer 0 */
+#define ICU_INT_TIMER1		(9) /* Timer 1 */
+#define ICU_INT_I2C0		(10) /* I2C bus interface 0 */
+#define ICU_INT_I2C1		(11) /* I2C bus interface 1 */
+#define ICU_INT_MU		(12) /* Message Unit */
+#define ICU_INT_MU_IPQ		(13) /* Message unit inbound post queue */
+#define ICU_INT_ATUE_IM		(14) /* ATU-E inbound message */
+#define ICU_INT_ATU_BIST	(15) /* ATU/Start BIST */
+#define ICU_INT_PMC		(16) /* PMC */
+#define ICU_INT_PMU		(17) /* PMU */
+#define ICU_INT_PC		(18) /* Processor cache */
+/* 19-23 Reserved */
+#define ICU_INT_XINT0		(24)
+#define ICU_INT_XINT1		(25)
+#define ICU_INT_XINT2		(26)
+#define ICU_INT_XINT3		(27)
+#define ICU_INT_XINT4		(28)
+#define ICU_INT_XINT5		(29)
+#define ICU_INT_XINT6		(30)
+#define ICU_INT_XINT7		(31)
+/* IINTSRC1 */
+#define ICU_INT_XINT8		(32)
+#define ICU_INT_XINT9		(33)
+#define ICU_INT_XINT10		(34)
+#define ICU_INT_XINT11		(35)
+#define ICU_INT_XINT12		(36)
+#define ICU_INT_XINT13		(37)
+#define ICU_INT_XINT14		(38)
+#define ICU_INT_XINT15		(39)
+/* 40-50 reserved */
+#define ICU_INT_UART0		(51) /* UART 0 */
+#define ICU_INT_UART1		(52) /* UART 1 */
+#define ICU_INT_PBIUE		(53) /* Peripheral bus interface unit error */
+#define ICU_INT_ATUCRW		(54) /* ATU Configuration register write */
+#define ICU_INT_ATUE		(55) /* ATU error */
+#define ICU_INT_MCUE		(56) /* Memory controller unit error */
+#define ICU_INT_ADMA0E		(57) /* ADMA Channel 0 error */
+#define ICU_INT_ADMA1E		(58) /* ADMA Channel 1 error */
+#define ICU_INT_ADMA2E		(59) /* ADMA Channel 2 error */
+/* 60-61 reserved */
+#define ICU_INT_MUE		(62) /* Messaging Unit Error */
+/* 63 reserved */
+
+/* IINTSRC2 */
+#define ICU_INT_IP		(64) /* Inter-processor */
+/* 65-93 reserved */
+#define ICU_INT_SIBBE		(94) /* South internal bus bridge error */
+/* 95 reserved */
+
+/* IINTSRC3 */
+#define ICU_INT_I2C2		(96) /* I2C bus interface 2 */
+#define ICU_INT_ATUE_BIST	(97) /* ATU-E/Start BIST */
+#define ICU_INT_ATUE_CRW	(98) /* ATU-E Configuration register write */
+#define ICU_INT_ATUEE		(99) /* ATU-E Error */
+#define ICU_INT_IMU		(100) /* IMU */
+/* 101-106 reserved */
+#define ICU_INT_ATUE_MA		(107) /* ATUE Interrupt message A */
+#define ICU_INT_ATUE_MB		(108) /* ATUE Interrupt message B */
+#define ICU_INT_ATUE_MC		(109) /* ATUE Interrupt message C */
+#define ICU_INT_ATUE_MD		(110) /* ATUE Interrupt message D */
+#define ICU_INT_MU_MSIX_TW	(111) /* MU MSI-X Table write */
+/* 112 reserved */
+#define ICU_INT_IMSI		(113) /* Inbound MSI */
+/* 114-126 reserved */
+#define ICU_INT_HPI		(127) /* HPI */
+
+
+#endif /* I81342_REG_H_ */
diff --git a/sys/arm/xscale/i8134x/i81342var.h b/sys/arm/xscale/i8134x/i81342var.h
new file mode 100644
index 0000000..c7fde4b
--- /dev/null
+++ b/sys/arm/xscale/i8134x/i81342var.h
@@ -0,0 +1,70 @@
+/*-
+ * Copyright (c) 2006 Olivier Houchard
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* $FreeBSD$ */
+#ifndef I81342VAR_H_
+#define I81342VAR_H_
+
+#include <sys/rman.h>
+
+struct i81342_softc {
+	device_t dev;
+	bus_space_tag_t 	sc_st;
+	bus_space_handle_t 	sc_sh;
+	bus_space_handle_t	sc_atux_sh;
+	bus_space_handle_t	sc_atue_sh;
+	bus_space_tag_t		sc_pciio;
+	bus_space_tag_t		sc_pcimem;
+	struct rman 		sc_irq_rman;
+};
+
+struct i81342_pci_map {
+	vm_offset_t vaddr;
+	vm_paddr_t paddr;
+	vm_size_t size;
+	struct i81342_pci_map *next;
+};
+
+struct i81342_pci_softc {
+	device_t		sc_dev;
+	bus_space_tag_t		sc_st;
+	bus_space_handle_t	sc_atu_sh;
+	struct bus_space	sc_pciio;
+	struct bus_space	sc_pcimem;
+	struct rman		sc_mem_rman;
+	struct rman		sc_io_rman;
+	struct rman		sc_irq_rman;
+	char			sc_is_atux;
+	int			sc_busno;
+	struct i81342_pci_map	*sc_pci_mappings;
+};
+
+void i81342_bs_init(bus_space_tag_t, void *);
+void i81342_io_bs_init(bus_space_tag_t, void *);
+void i81342_mem_bs_init(bus_space_tag_t, void *);
+void i81342_sdram_bounds(bus_space_tag_t, bus_space_handle_t, vm_paddr_t *,
+    vm_size_t *);
+#endif /*I81342VAR_H_ */
diff --git a/sys/arm/xscale/i8134x/obio.c b/sys/arm/xscale/i8134x/obio.c
new file mode 100644
index 0000000..534f0e7
--- /dev/null
+++ b/sys/arm/xscale/i8134x/obio.c
@@ -0,0 +1,167 @@
+/*	$NetBSD: obio.c,v 1.11 2003/07/15 00:25:05 lukem Exp $	*/
+
+/*-
+ * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * On-board device autoconfiguration support for Intel IQ80321
+ * evaluation boards.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/malloc.h>
+
+#include <machine/bus.h>
+
+#include <arm/xscale/i8134x/i81342reg.h>
+#include <arm/xscale/i8134x/obiovar.h>
+
+
+static int
+obio_probe(device_t dev)
+{
+	return (0);
+}
+
+static int
+obio_attach(device_t dev)
+{
+	struct obio_softc *sc = device_get_softc(dev);
+
+	sc->oba_st = &obio_bs_tag;
+	sc->oba_rman.rm_type = RMAN_ARRAY;
+	sc->oba_rman.rm_descr = "OBIO I/O";
+	if (rman_init(&sc->oba_rman) != 0 ||
+	    rman_manage_region(&sc->oba_rman,
+	    IOP34X_UART0_VADDR, IOP34X_UART1_VADDR + 0x40) != 0)
+		panic("obio_attach: failed to set up I/O rman");
+	sc->oba_irq_rman.rm_type = RMAN_ARRAY;
+	sc->oba_irq_rman.rm_descr = "OBIO IRQ";
+	if (rman_init(&sc->oba_irq_rman) != 0 ||
+	    rman_manage_region(&sc->oba_irq_rman, ICU_INT_UART0, ICU_INT_UART1) != 0)
+		panic("obio_attach: failed to set up IRQ rman");
+	device_add_child(dev, "uart", 0);
+	device_add_child(dev, "uart", 1);
+	bus_generic_probe(dev);
+	bus_generic_attach(dev);
+	return (0);
+}
+
+static struct resource *
+obio_alloc_resource(device_t bus, device_t child, int type, int *rid,
+    u_long start, u_long end, u_long count, u_int flags)
+{
+	struct resource *rv;
+	struct rman *rm;
+	bus_space_tag_t bt = NULL;
+	bus_space_handle_t bh = 0;
+	struct obio_softc *sc = device_get_softc(bus);
+	int unit = device_get_unit(child);
+
+	switch (type) {
+	case SYS_RES_IRQ:
+		rm = &sc->oba_irq_rman;
+		if (unit == 0)
+			start = end = ICU_INT_UART0;
+		else
+			start = end = ICU_INT_UART1;
+		break;
+	case SYS_RES_MEMORY:
+		return (NULL);
+	case SYS_RES_IOPORT:
+		rm = &sc->oba_rman;
+		bt = sc->oba_st;
+		if (unit == 0) {
+			bh = IOP34X_UART0_VADDR;
+			start = bh;
+			end = IOP34X_UART1_VADDR;
+		} else {
+			bh = IOP34X_UART1_VADDR;
+			start = bh;
+			end = start + 0x40;
+		}
+		break;
+	default:
+		return (NULL);
+	}
+
+
+	rv = rman_reserve_resource(rm, start, end, count, flags, child);
+	if (rv == NULL) 
+		return (NULL);
+	if (type == SYS_RES_IRQ)
+		return (rv);
+	rman_set_rid(rv, *rid);
+	rman_set_bustag(rv, bt);
+	rman_set_bushandle(rv, bh);
+	
+	return (rv);
+
+}
+
+static int
+obio_activate_resource(device_t bus, device_t child, int type, int rid,
+    struct resource *r)
+{
+	return (0);
+}
+static device_method_t obio_methods[] = {
+	DEVMETHOD(device_probe, obio_probe),
+	DEVMETHOD(device_attach, obio_attach),
+
+	DEVMETHOD(bus_alloc_resource, obio_alloc_resource),
+	DEVMETHOD(bus_activate_resource, obio_activate_resource),
+	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
+	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
+
+	{0, 0},
+};
+
+static driver_t obio_driver = {
+	"obio",
+	obio_methods,
+	sizeof(struct obio_softc),
+};
+static devclass_t obio_devclass;
+
+DRIVER_MODULE(obio, iq, obio_driver, obio_devclass, 0, 0);
diff --git a/sys/arm/xscale/i8134x/obio_space.c b/sys/arm/xscale/i8134x/obio_space.c
new file mode 100644
index 0000000..252f2c6
--- /dev/null
+++ b/sys/arm/xscale/i8134x/obio_space.c
@@ -0,0 +1,225 @@
+/*	$NetBSD: obio_space.c,v 1.6 2003/07/15 00:25:05 lukem Exp $	*/
+
+/*-
+ * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * bus_space functions for IQ80321 on-board devices
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+
+#include <machine/pcb.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm_kern.h>
+#include <vm/vm_extern.h>
+
+#include <machine/bus.h>
+
+/* Prototypes for all the bus_space structure functions */
+bs_protos(obio);
+bs_protos(generic);
+bs_protos(generic_armv4);
+
+/*
+ * The obio bus space tag.  This is constant for all instances, so
+ * we never have to explicitly "create" it.
+ */
+struct bus_space obio_bs_tag = {
+	/* cookie */
+	(void *) 0,
+
+	/* mapping/unmapping */
+	obio_bs_map,
+	obio_bs_unmap,
+	obio_bs_subregion,
+
+	/* allocation/deallocation */
+	obio_bs_alloc,
+	obio_bs_free,
+
+	/* barrier */
+	obio_bs_barrier,
+
+	/* read (single) */
+	generic_bs_r_1,
+	generic_armv4_bs_r_2,
+	generic_bs_r_4,
+	NULL,
+
+	/* read multiple */
+	generic_bs_rm_1,
+	NULL,
+	NULL,
+	NULL,
+
+	/* read region */
+	generic_bs_rr_1,
+	NULL,
+	NULL,
+	NULL,
+
+	/* write (single) */
+	generic_bs_w_1,
+	generic_armv4_bs_w_2,
+	generic_bs_w_4,
+	NULL,
+
+	/* write multiple */
+	generic_bs_wm_1,
+	NULL,
+	NULL,
+	NULL,
+
+	/* write region */
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+
+	/* set multiple */
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+
+	/* set region */
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+
+	/* copy */
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+};
+
+int
+obio_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flags,
+    bus_space_handle_t *bshp)
+{
+	const struct pmap_devmap *pd;
+	vm_paddr_t startpa, endpa, pa, offset;
+	vm_offset_t va;
+	pt_entry_t *pte;
+
+	if ((pd = pmap_devmap_find_pa(bpa, size)) != NULL) {
+		/* Device was statically mapped. */
+		*bshp = pd->pd_va + (bpa - pd->pd_pa);
+		return (0);
+	}
+
+	endpa = round_page(bpa + size);
+	offset = bpa & PAGE_MASK;
+	startpa = trunc_page(bpa);
+		
+	va = kmem_alloc(kernel_map, endpa - startpa);
+	if (va == 0)
+		return (ENOMEM);
+
+	*bshp = va + offset;
+
+	for (pa = startpa; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) {
+		pmap_kenter(va, pa);
+		pte = vtopte(va);
+		*pte &= ~L2_S_CACHE_MASK;
+		PTE_SYNC(pte);
+	}
+
+	return (0);
+}
+
+int
+obio_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend, bus_size_t size,
+    bus_size_t alignment, bus_size_t boundary, int flags, bus_addr_t *bpap,
+    bus_space_handle_t *bshp)
+{
+
+	panic("obio_bs_alloc(): not implemented");
+}
+
+
+void
+obio_bs_unmap(void *t, bus_space_handle_t h, bus_size_t size)
+{
+	vm_offset_t va, endva;
+
+	if (pmap_devmap_find_va((vm_offset_t)t, size) != NULL) {
+		/* Device was statically mapped; nothing to do. */
+		return;
+	}
+
+	endva = round_page((vm_offset_t)t + size);
+	va = trunc_page((vm_offset_t)t);
+
+	while (va < endva) {
+		pmap_kremove(va);
+		va += PAGE_SIZE;
+	}
+	kmem_free(kernel_map, va, endva - va);
+}
+
+void    
+obio_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
+{
+
+	panic("obio_bs_free(): not implemented");
+}
+
+int
+obio_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset,
+    bus_size_t size, bus_space_handle_t *nbshp)
+{
+
+	*nbshp = bsh + offset;
+	return (0);
+}
+
+void
+obio_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset,
+    bus_size_t len, int flags)
+{
+
+	/* Nothing to do. */
+}
diff --git a/sys/arm/xscale/i8134x/obiovar.h b/sys/arm/xscale/i8134x/obiovar.h
new file mode 100644
index 0000000..7350d0a
--- /dev/null
+++ b/sys/arm/xscale/i8134x/obiovar.h
@@ -0,0 +1,55 @@
+/*	$NetBSD: obiovar.h,v 1.4 2003/06/16 17:40:53 thorpej Exp $	*/
+
+/*-
+ * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ *
+ */
+
+#ifndef _IQ81342_OBIOVAR_H_
+#define	_IQ81342_OBIOVAR_H_
+
+#include <sys/rman.h>
+
+struct obio_softc {
+	bus_space_tag_t oba_st;		/* bus space tag */
+	int oba_irq;			/* XINT interrupt bit # */
+	struct rman oba_rman;
+	struct rman oba_irq_rman;
+	
+};
+extern struct bus_space obio_bs_tag;
+
+#endif /* _IQ80321_OBIOVAR_H_ */
diff --git a/sys/arm/xscale/i8134x/std.crb b/sys/arm/xscale/i8134x/std.crb
new file mode 100644
index 0000000..fe80ffb
--- /dev/null
+++ b/sys/arm/xscale/i8134x/std.crb
@@ -0,0 +1,6 @@
+#CRB board configuration
+#$FreeBSD$
+include		"../xscale/i8134x/std.i81342"
+files		"../xscale/i8134x/files.crb"
+makeoptions	KERNPHYSADDR=0x00200000
+makeoptions	KERNVIRTADDR=0xc0200000
diff --git a/sys/arm/xscale/i8134x/std.i81342 b/sys/arm/xscale/i8134x/std.i81342
new file mode 100644
index 0000000..e95af9d
--- /dev/null
+++ b/sys/arm/xscale/i8134x/std.i81342
@@ -0,0 +1,5 @@
+#XScale i81342 generic configuration
+#$FreeBSD$
+files		"../xscale/i8134x/files.i81342"
+include		"../xscale/std.xscale"
+cpu 		CPU_XSCALE_81342
diff --git a/sys/arm/xscale/i8134x/uart_bus_i81342.c b/sys/arm/xscale/i8134x/uart_bus_i81342.c
new file mode 100644
index 0000000..fc99d07
--- /dev/null
+++ b/sys/arm/xscale/i8134x/uart_bus_i81342.c
@@ -0,0 +1,92 @@
+/*-
+ * Copyright (c) 2004 Olivier Houchard.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <machine/bus.h>
+#include <sys/rman.h>
+#include <machine/resource.h>
+
+#include <dev/pci/pcivar.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_bus.h>
+#include <dev/uart/uart_cpu.h>
+
+#include <dev/ic/ns16550.h>
+
+#include "uart_if.h"
+
+static int uart_i81342_probe(device_t dev);
+
+static device_method_t uart_i81342_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		uart_i81342_probe),
+	DEVMETHOD(device_attach,	uart_bus_attach),
+	DEVMETHOD(device_detach,	uart_bus_detach),
+	{ 0, 0 }
+};
+
+static driver_t uart_i81342_driver = {
+	uart_driver_name,
+	uart_i81342_methods,
+	sizeof(struct uart_softc),
+};
+
+extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
+static int
+uart_i81342_probe(device_t dev)
+{
+	struct uart_softc *sc;
+	int err;
+
+	sc = device_get_softc(dev);
+	sc->sc_class = &uart_ns8250_class;
+	if (device_get_unit(dev) == 0) {
+		sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs);
+		bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas));
+	}
+	sc->sc_rres = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->sc_rrid,
+            0, ~0, uart_getrange(sc->sc_class), RF_ACTIVE);
+	
+	sc->sc_bas.bsh = rman_get_bushandle(sc->sc_rres);
+	sc->sc_bas.bst = rman_get_bustag(sc->sc_rres);
+	bus_space_write_4(sc->sc_bas.bst, sc->sc_bas.bsh, REG_IER << 2,
+	    0x40 | 0x10);
+        bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid, sc->sc_rres);
+
+	err = uart_bus_probe(dev, 2, 33334000, 0, device_get_unit(dev));
+	sc->sc_rxfifosz = sc->sc_txfifosz = 1;
+	return (err);
+}
+
+
+DRIVER_MODULE(uart, obio, uart_i81342_driver, uart_devclass, 0, 0);
diff --git a/sys/arm/xscale/i8134x/uart_cpu_i81342.c b/sys/arm/xscale/i8134x/uart_cpu_i81342.c
new file mode 100644
index 0000000..02e7050
--- /dev/null
+++ b/sys/arm/xscale/i8134x/uart_cpu_i81342.c
@@ -0,0 +1,68 @@
+/*-
+ * Copyright (c) 2003 Marcel Moolenaar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/cons.h>
+#include <machine/bus.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_cpu.h>
+
+#include <arm/xscale/i8134x/i81342reg.h>
+#include <arm/xscale/i8134x/obiovar.h>
+
+bus_space_tag_t uart_bus_space_io;
+bus_space_tag_t uart_bus_space_mem;
+
+int
+uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
+{
+	return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0);
+}
+
+int
+uart_cpu_getdev(int devtype, struct uart_devinfo *di)
+{
+
+	di->ops = uart_getops(&uart_ns8250_class);
+	di->bas.chan = 0;
+	di->bas.bst = &obio_bs_tag;
+	di->bas.regshft = 2; 
+	di->bas.rclk = 33334000;
+	di->baudrate = 115200;
+	di->databits = 8;
+	di->stopbits = 1;
+	di->parity = UART_PARITY_NONE;
+	uart_bus_space_io = &obio_bs_tag;
+	uart_bus_space_mem = NULL;
+	di->bas.bsh = IOP34X_UART0_VADDR;
+	return (0);
+}