- MFp4: modify slightly the arm intr API, there's arm CPUs with more than 32

interrupts.
- Implement teardown methods where appropriate.

1 files changed, 14 insertions, 16 deletions

diff --git a/sys/arm/sa11x0/sa11x0_irqhandler.c b/sys/arm/sa11x0/sa11x0_irqhandler.c
index a3f7db4..5cda4c6 100644
--- a/sys/arm/sa11x0/sa11x0_irqhandler.c
+++ b/sys/arm/sa11x0/sa11x0_irqhandler.c
@@ -102,37 +102,35 @@ int current_intr_depth;
 extern struct sa11x0_softc *sa11x0_softc;
 
 
-/* Recalculate the interrupt masks from scratch.
- * We could code special registry and deregistry versions of this function that
- * would be faster, but the code would be nastier, and we don't expect this to
- * happen very much anyway.
- */
+static uint32_t sa11x0_irq_mask = 0xfffffff;
+
+extern vm_offset_t saipic_base;
+
 int
-arm_get_irqnb(void *frame)
+arm_get_next_irq()
 {
-	struct sa11x0_softc *sc = sa11x0_softc;
+	int irq;
 
-	return(bus_space_read_4(sc->sc_iot, sc->sc_ioh, SAIPIC_IP));
+	if ((irq = (bus_space_read_4(sc->sc_iot, sc->sc_ioh, SAIPIC_IP) &
+	    sa11x0_irq_mask)) != 0)
+		return (ffs(irq) - 1);
+	return (-1);
 }
 
-static uint32_t sa11x0_irq_mask = 0xfffffff;
-
-extern vm_offset_t saipic_base;
-
 void
-arm_mask_irqs(int irq)
+arm_mask_irq(uintptr_t irq)
 {
 
-	sa11x0_irq_mask &= ~irq;
+	sa11x0_irq_mask &= ~(1 << irq);
 	__asm __volatile("str	%0, [%1, #0x04]" /* SAIPIC_MR */
 	    : : "r" (sa11x0_irq_mask), "r" (saipic_base));
 }
 
 void
-arm_unmask_irqs(int irq)
+arm_unmask_irq(uintptr_t irq)
 {
 
-	sa11x0_irq_mask |= irq;
+	sa11x0_irq_mask |= (1 << irq);
 	__asm __volatile("str	%0, [%1, #0x04]" /* SAIPIC_MR */
 	    : : "r" (sa11x0_irq_mask), "r" (saipic_base));
 }