MFC r257170, r257171, r257172, r257240, r257278, r257279, r257280, r257281,

    r257282, r257332

  Wait for DesignWare UART transfers completion before accessing line control

  Enable UART busy detection handling for Armada XP - based board

  Enable SATA interface on Armada XP
  Run mvs SATA driver on Armada XP instead of old mv_sata

  Retire arm_remap_nocache() and the data and constants associated with it.

  Remove hard-coded mappings related to Armada XP support

  Fix-up DTB for Armada XP registers' base according to the actual settings

  Change Armada XP kernel load address to the u-boot's end address

  Remove not working and deprecated PJ4Bv6 support

  Switch off explicit broadcasting of the TLB flush operations for PJ4B CPU

  Add missing ARMv6 CPU functions to ARM Makefile

4 files changed, 90 insertions, 6 deletions

diff --git a/sys/arm/mv/armadaxp/std.armadaxp b/sys/arm/mv/armadaxp/std.armadaxp
index bf2a5f6..d731ad3 100644
--- a/sys/arm/mv/armadaxp/std.armadaxp
+++ b/sys/arm/mv/armadaxp/std.armadaxp
@@ -1,16 +1,16 @@
 # $FreeBSD$
 
-# kernel gets loaded at 0x00f00000 by the loader, but runs at virtual address
-# 0xc0f00000.  RAM starts at 0.  We put the pagetable at a reasonable place
+# kernel gets loaded at 0x00200000 by the loader, but runs at virtual address
+# 0xc0200000.  RAM starts at 0.  We put the pagetable at a reasonable place
 # in memory, but may need to bounce it higher if there's a problem with this.
 # We could paper over this by loading the kernel at 0xc0000000 virtual, but
 # that leads to other complications, so we'll just reclaim the lower region of
 # ram after we're loaded.  Put the page tables for startup at 1MB.
-makeoptions	KERNPHYSADDR=0x00f00000
-makeoptions	KERNVIRTADDR=0xc0f00000
+makeoptions	KERNPHYSADDR=0x00200000
+makeoptions	KERNVIRTADDR=0xc0200000
 
-options		KERNPHYSADDR=0x00f00000
-options		KERNVIRTADDR=0xc0f00000
+options		KERNPHYSADDR=0x00200000
+options		KERNVIRTADDR=0xc0200000
 options		PHYSADDR=0x00000000
 options		STARTUP_PAGETABLE_ADDR=0x00100000
 
diff --git a/sys/arm/mv/common.c b/sys/arm/mv/common.c
index d4bee64..366fcf1 100644
--- a/sys/arm/mv/common.c
+++ b/sys/arm/mv/common.c
@@ -2078,9 +2078,79 @@ fdt_fixup_busfreq(phandle_t root)
 		OF_setprop(sb, "bus-frequency", (void *)&freq, sizeof(freq));
 }
 
+static void
+fdt_fixup_ranges(phandle_t root)
+{
+	phandle_t node;
+	pcell_t par_addr_cells, addr_cells, size_cells;
+	pcell_t ranges[3], reg[2], *rangesptr;
+	int len, tuple_size, tuples_count;
+	uint32_t base;
+
+	/* Fix-up SoC ranges according to real fdt_immr_pa */
+	if ((node = fdt_find_compatible(root, "simple-bus", 1)) != 0) {
+		if (fdt_addrsize_cells(node, &addr_cells, &size_cells) == 0 &&
+		    (par_addr_cells = fdt_parent_addr_cells(node) <= 2)) {
+			tuple_size = sizeof(pcell_t) * (par_addr_cells +
+			   addr_cells + size_cells);
+			len = OF_getprop(node, "ranges", ranges,
+			    sizeof(ranges));
+			tuples_count = len / tuple_size;
+			/* Unexpected settings are not supported */
+			if (tuples_count != 1)
+				goto fixup_failed;
+
+			rangesptr = &ranges[0];
+			rangesptr += par_addr_cells;
+			base = fdt_data_get((void *)rangesptr, addr_cells);
+			*rangesptr = cpu_to_fdt32(fdt_immr_pa);
+			if (OF_setprop(node, "ranges", (void *)&ranges[0],
+			    sizeof(ranges)) < 0)
+				goto fixup_failed;
+		}
+	}
+
+	/* Fix-up PCIe reg according to real PCIe registers' PA */
+	if ((node = fdt_find_compatible(root, "mrvl,pcie", 1)) != 0) {
+		if (fdt_addrsize_cells(OF_parent(node), &par_addr_cells,
+		    &size_cells) == 0) {
+			tuple_size = sizeof(pcell_t) * (par_addr_cells +
+			    size_cells);
+			len = OF_getprop(node, "reg", reg, sizeof(reg));
+			tuples_count = len / tuple_size;
+			/* Unexpected settings are not supported */
+			if (tuples_count != 1)
+				goto fixup_failed;
+
+			base = fdt_data_get((void *)&reg[0], par_addr_cells);
+			base &= ~0xFF000000;
+			base |= fdt_immr_pa;
+			reg[0] = cpu_to_fdt32(base);
+			if (OF_setprop(node, "reg", (void *)&reg[0],
+			    sizeof(reg)) < 0)
+				goto fixup_failed;
+		}
+	}
+	/* Fix-up succeeded. May return and continue */
+	return;
+
+fixup_failed:
+	while (1) {
+		/*
+		 * In case of any error while fixing ranges just hang.
+		 *	1. No message can be displayed yet since console
+		 *	   is not initialized.
+		 *	2. Going further will cause failure on bus_space_map()
+		 *	   relying on the wrong ranges or data abort when
+		 *	   accessing PCIe registers.
+		 */
+	}
+}
+
 struct fdt_fixup_entry fdt_fixup_table[] = {
 	{ "mrvl,DB-88F6281", &fdt_fixup_busfreq },
 	{ "mrvl,DB-78460", &fdt_fixup_busfreq },
+	{ "mrvl,DB-78460", &fdt_fixup_ranges },
 	{ NULL, NULL }
 };
 
diff --git a/sys/arm/mv/mv_machdep.c b/sys/arm/mv/mv_machdep.c
index d31a512..9758cfb 100644
--- a/sys/arm/mv/mv_machdep.c
+++ b/sys/arm/mv/mv_machdep.c
@@ -329,6 +329,19 @@ initarm_devmap_init(void)
 	i = 0;
 	arm_devmap_register_table(&fdt_devmap[0]);
 
+#ifdef SOC_MV_ARMADAXP
+	vm_paddr_t cur_immr_pa;
+
+	/*
+	 * Acquire SoC registers' base passed by u-boot and fill devmap
+	 * accordingly. DTB is going to be modified basing on this data
+	 * later.
+	 */
+	__asm __volatile("mrc p15, 4, %0, c15, c0, 0" : "=r" (cur_immr_pa));
+	cur_immr_pa = (cur_immr_pa << 13) & 0xff000000;
+	if (cur_immr_pa != 0)
+		fdt_immr_pa = cur_immr_pa;
+#endif
 	/*
 	 * IMMR range.
 	 */
diff --git a/sys/arm/mv/mv_sata.c b/sys/arm/mv/mv_sata.c
index 28c641f..87b3823 100644
--- a/sys/arm/mv/mv_sata.c
+++ b/sys/arm/mv/mv_sata.c
@@ -200,6 +200,7 @@ sata_probe(device_t dev)
 	case MV_DEV_88F6282:
 	case MV_DEV_MV78100:
 	case MV_DEV_MV78100_Z0:
+	case MV_DEV_MV78460:
 		sc->sc_version = 2;
 		sc->sc_edma_qlen = 32;
 		break;