PCI/PCI-Express support for Marvell systems.

Obtained from:	Marvell, Semihalf

2 files changed, 19 insertions, 36 deletions

diff --git a/sys/arm/mv/orion/db88f5xxx.c b/sys/arm/mv/orion/db88f5xxx.c
index 5c333b4..d3a1a8c 100644
--- a/sys/arm/mv/orion/db88f5xxx.c
+++ b/sys/arm/mv/orion/db88f5xxx.c
@@ -57,7 +57,11 @@ __FBSDID("$FreeBSD$");
  * virtual_avail - 0xefff_ffff	: KVA (virtual_avail is typically < 0xc0a0_0000)
  * 0xf000_0000 - 0xf0ff_ffff	: no-cache allocation area (16MB)
  * 0xf100_0000 - 0xf10f_ffff	: SoC integrated devices registers range (1MB)
- * 0xf110_0000 - 0xfffe_ffff	: PCI, PCIE (MEM+IO) outbound windows (~238MB)
+ * 0xf110_0000 - 0xf11f_ffff	: PCI-Express I/O space (1MB)
+ * 0xf120_0000 - 0xf12f_ffff	: PCI I/O space (1MB)
+ * 0xf130_0000 - 0xf52f_ffff	: PCI-Express memory space (64MB)
+ * 0xf530_0000 - 0xf92f_ffff	: PCI memory space (64MB)
+ * 0xf930_0000 - 0xfffe_ffff	: unused (~108MB)
  * 0xffff_0000 - 0xffff_0fff	: 'high' vectors page (4KB)
  * 0xffff_1000 - 0xffff_1fff	: ARM_TP_ADDRESS/RAS page (4KB)
  * 0xffff_2000 - 0xffff_ffff	: unused (~55KB)
@@ -65,6 +69,7 @@ __FBSDID("$FreeBSD$");
 
 const struct pmap_devmap *pmap_devmap_bootstrap_table;
 vm_offset_t pmap_bootstrap_lastaddr;
+int platform_pci_get_irq(u_int bus, u_int slot, u_int func, u_int pin);
 
 /* Static device mappings. */
 static const struct pmap_devmap pmap_devmap[] = {
@@ -117,7 +122,6 @@ static const struct pmap_devmap pmap_devmap[] = {
 	{ 0, 0, 0, 0, 0, }
 };
 
-#if 0
 int platform_pci_get_irq(u_int bus, u_int slot, u_int func, u_int pin)
 {
 	int irq;
@@ -145,9 +149,8 @@ int platform_pci_get_irq(u_int bus, u_int slot, u_int func, u_int pin)
 		mv_gpio_configure(IRQ2GPIO(irq), MV_GPIO_POLARITY |
 		    MV_GPIO_LEVEL, ~0u);
 
-	return(irq);
+	return (irq);
 }
-#endif
 
 int
 platform_pmap_init(void)
diff --git a/sys/arm/mv/orion/orion.c b/sys/arm/mv/orion/orion.c
index 8eb4908a..5ee3bac 100644
--- a/sys/arm/mv/orion/orion.c
+++ b/sys/arm/mv/orion/orion.c
@@ -41,10 +41,7 @@ __FBSDID("$FreeBSD$");
 #include <arm/mv/mvreg.h>
 #include <arm/mv/mvvar.h>
 
-#if 0
-#include <arm/mv/mv_pci.h>
 extern int platform_pci_get_irq(u_int bus, u_int slot, u_int func, u_int pin);
-#endif
 
 struct obio_device obio_devices[] = {
 	{ "ic", MV_IC_BASE, MV_IC_SIZE,
@@ -94,31 +91,26 @@ struct obio_device obio_devices[] = {
 		{ -1 }, { -1 },
 		CPU_PM_CTRL_NONE
 	},
-	{ "pcib", MV_PCIE_BASE, MV_PCIE_SIZE,
-		{ MV_INT_PEX0_ERR, -1 },
-		{ -1 },
-		CPU_PM_CTRL_NONE
-        },
-	{ "pcib", MV_PCI_BASE, MV_PCI_SIZE,
-		{ MV_INT_PCI_ERR, -1 },
-		{-1 },
-		CPU_PM_CTRL_NONE
-        },
 	{ NULL, 0, 0, { 0 } }
 };
 
-#if 0
-const struct mv_pci_info pci_info[] = {
-	{ 1,	MV_PCIE_IO_BASE, MV_PCIE_IO_SIZE,
-		MV_PCIE_MEM_BASE, MV_PCIE_MEM_SIZE,
+const struct obio_pci mv_pci_info[] = {
+	{ MV_TYPE_PCIE,
+		MV_PCIE_BASE,	MV_PCIE_SIZE,
+		MV_PCIE_IO_BASE, MV_PCIE_IO_SIZE,	4, 0x51,
+		MV_PCIE_MEM_BASE, MV_PCIE_MEM_SIZE,	4, 0x59,
 		NULL, MV_INT_PEX0
 	},
-	{ 0,	MV_PCI_IO_BASE, MV_PCI_IO_SIZE,
-		MV_PCI_MEM_BASE, MV_PCI_MEM_SIZE,
+
+	{ MV_TYPE_PCI,
+		MV_PCI_BASE, MV_PCI_SIZE,
+		MV_PCI_IO_BASE, MV_PCI_IO_SIZE,		3, 0x51,
+		MV_PCI_MEM_BASE, MV_PCI_MEM_SIZE,	3, 0x59,
 		platform_pci_get_irq, -1
 	},
+
+	{ 0, 0, 0 }
 };
-#endif
 
 struct resource_spec mv_gpio_spec[] = {
 	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
@@ -130,18 +122,6 @@ struct resource_spec mv_gpio_spec[] = {
 };
 
 const struct decode_win cpu_win_tbl[] = {
-	/* PCIE IO */
-	{ 4, 0x51, MV_PCIE_IO_PHYS_BASE, MV_PCIE_IO_SIZE, -1 },
-
-	/* PCI IO */
-	{ 3, 0x51, MV_PCI_IO_PHYS_BASE, MV_PCI_IO_SIZE, -1 },
-
-	/* PCIE MEM */
-	{ 4, 0x59, MV_PCIE_MEM_PHYS_BASE, MV_PCIE_MEM_SIZE, -1 },
-
-	/* PCI MEM */
-	{ 3, 0x59, MV_PCI_MEM_PHYS_BASE, MV_PCI_MEM_SIZE, -1 },
-
 	/* Device bus BOOT */
 	{ 1, 0x0f, MV_DEV_BOOT_PHYS_BASE, MV_DEV_BOOT_SIZE, -1 },