Convert Marvell ARM platforms to FDT convention.

The following systems are involved:

  - DB-88F5182
  - DB-88F5281
  - DB-88F6281
  - DB-78100
  - SheevaPlug

This overhaul covers the following major changes:

  - All integrated peripherals drivers for Marvell ARM SoC, which are
    currently in the FreeBSD source tree are reworked and adjusted so they
    derive config data out of the device tree blob (instead of hard coded /
    tabelarized values).

  - Since the common FDT infrastrucutre (fdtbus, simplebus) is used we say
    good by to obio / mbus drivers and numerous hard-coded config data.

Note that world needs to be built WITH_FDT for the affected platforms.

Reviewed by:	imp
Sponsored by:	The FreeBSD Foundation.

1 files changed, 431 insertions, 473 deletions

diff --git a/sys/arm/mv/mv_pci.c b/sys/arm/mv/mv_pci.c
index 26cd1f5..c8664ef 100644
--- a/sys/arm/mv/mv_pci.c
+++ b/sys/arm/mv/mv_pci.c
@@ -1,9 +1,13 @@
 /*-
- * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
+ * Copyright (c) 2008 MARVELL INTERNATIONAL LTD.
+ * Copyright (c) 2010 The FreeBSD Foundation
  * All rights reserved.
  *
  * Developed by Semihalf.
  *
+ * Portions of this software were developed by Semihalf
+ * under sponsorship from the FreeBSD Foundation.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
@@ -51,10 +55,14 @@ __FBSDID("$FreeBSD$");
 #include <vm/vm.h>
 #include <vm/pmap.h>
 
+#include <dev/fdt/fdt_common.h>
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
 #include <dev/pci/pcivar.h>
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcib_private.h>
 
+#include "ofw_bus_if.h"
 #include "pcib_if.h"
 
 #include <machine/resource.h>
@@ -62,6 +70,7 @@ __FBSDID("$FreeBSD$");
 
 #include <arm/mv/mvreg.h>
 #include <arm/mv/mvvar.h>
+#include <arm/mv/mvwin.h>
 
 #define PCI_CFG_ENA		(1 << 31)
 #define PCI_CFG_BUS(bus)	(((bus) & 0xff) << 16)
@@ -93,18 +102,22 @@ __FBSDID("$FreeBSD$");
 
 #define PCI_VENDORID_MRVL	0x11AB
 
-struct pcib_mbus_softc {
+struct mv_pcib_softc {
 	device_t	sc_dev;
 
-	struct rman	sc_iomem_rman;
-	bus_addr_t	sc_iomem_base;
-	bus_addr_t	sc_iomem_size;
-	bus_addr_t	sc_iomem_alloc;		/* Next allocation. */
+	struct rman	sc_mem_rman;
+	bus_addr_t	sc_mem_base;
+	bus_addr_t	sc_mem_size;
+	bus_addr_t	sc_mem_alloc;		/* Next allocation. */
+	int		sc_mem_win_target;
+	int		sc_mem_win_attr;
 
-	struct rman	sc_ioport_rman;
-	bus_addr_t	sc_ioport_base;
-	bus_addr_t	sc_ioport_size;
-	bus_addr_t	sc_ioport_alloc;	/* Next allocation. */
+	struct rman	sc_io_rman;
+	bus_addr_t	sc_io_base;
+	bus_addr_t	sc_io_size;
+	bus_addr_t	sc_io_alloc;		/* Next allocation. */
+	int		sc_io_win_target;
+	int		sc_io_win_attr;
 
 	struct resource	*sc_res;
 	bus_space_handle_t sc_bsh;
@@ -113,452 +126,208 @@ struct pcib_mbus_softc {
 
 	int		sc_busnr;		/* Host bridge bus number */
 	int		sc_devnr;		/* Host bridge device number */
+	int		sc_type;
 
-	const struct obio_pci *sc_info;
+	struct fdt_pci_intr	sc_intr_info;
 };
 
-static void pcib_mbus_identify(driver_t *driver, device_t parent);
-static int pcib_mbus_probe(device_t);
-static int pcib_mbus_attach(device_t);
-
-static struct resource *pcib_mbus_alloc_resource(device_t, device_t, int, int *,
+/* Local forward prototypes */
+static int mv_pcib_decode_win(phandle_t, struct mv_pcib_softc *);
+static void mv_pcib_hw_cfginit(void);
+static uint32_t mv_pcib_hw_cfgread(struct mv_pcib_softc *, u_int, u_int,
+    u_int, u_int, int);
+static void mv_pcib_hw_cfgwrite(struct mv_pcib_softc *, u_int, u_int,
+    u_int, u_int, uint32_t, int);
+static int mv_pcib_init(struct mv_pcib_softc *, int, int);
+static int mv_pcib_init_all_bars(struct mv_pcib_softc *, int, int, int, int);
+static void mv_pcib_init_bridge(struct mv_pcib_softc *, int, int, int);
+static int mv_pcib_intr_info(phandle_t, struct mv_pcib_softc *);
+static inline void pcib_write_irq_mask(struct mv_pcib_softc *, uint32_t);
+
+
+/* Forward prototypes */
+static int mv_pcib_probe(device_t);
+static int mv_pcib_attach(device_t);
+
+static struct resource *mv_pcib_alloc_resource(device_t, device_t, int, int *,
     u_long, u_long, u_long, u_int);
-static int pcib_mbus_release_resource(device_t, device_t, int, int,
+static int mv_pcib_release_resource(device_t, device_t, int, int,
     struct resource *);
-static int pcib_mbus_read_ivar(device_t, device_t, int, uintptr_t *);
-static int pcib_mbus_write_ivar(device_t, device_t, int, uintptr_t);
+static int mv_pcib_read_ivar(device_t, device_t, int, uintptr_t *);
+static int mv_pcib_write_ivar(device_t, device_t, int, uintptr_t);
 
-static int pcib_mbus_maxslots(device_t);
-static uint32_t pcib_mbus_read_config(device_t, u_int, u_int, u_int, u_int,
-    int);
-static void pcib_mbus_write_config(device_t, u_int, u_int, u_int, u_int,
+static int mv_pcib_maxslots(device_t);
+static uint32_t mv_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int);
+static void mv_pcib_write_config(device_t, u_int, u_int, u_int, u_int,
     uint32_t, int);
-static int pcib_mbus_init(struct pcib_mbus_softc *sc, int bus, int maxslot);
-static int pcib_mbus_init_bar(struct pcib_mbus_softc *sc, int bus, int slot,
-    int func, int barno);
-static void pcib_mbus_init_bridge(struct pcib_mbus_softc *sc, int bus, int slot,
-    int func);
-static int pcib_mbus_init_resources(struct pcib_mbus_softc *sc, int bus,
-    int slot, int func, int hdrtype);
+static int mv_pcib_route_interrupt(device_t, device_t, int);
 
 /*
  * Bus interface definitions.
  */
-static device_method_t pcib_mbus_methods[] = {
+static device_method_t mv_pcib_methods[] = {
 	/* Device interface */
-	DEVMETHOD(device_identify,		pcib_mbus_identify),
-	DEVMETHOD(device_probe,			pcib_mbus_probe),
-	DEVMETHOD(device_attach,		pcib_mbus_attach),
+	DEVMETHOD(device_probe,			mv_pcib_probe),
+	DEVMETHOD(device_attach,		mv_pcib_attach),
 
 	/* Bus interface */
 	DEVMETHOD(bus_print_child,		bus_generic_print_child),
-	DEVMETHOD(bus_read_ivar,		pcib_mbus_read_ivar),
-	DEVMETHOD(bus_write_ivar,		pcib_mbus_write_ivar),
-	DEVMETHOD(bus_alloc_resource,		pcib_mbus_alloc_resource),
-	DEVMETHOD(bus_release_resource,		pcib_mbus_release_resource),
+	DEVMETHOD(bus_read_ivar,		mv_pcib_read_ivar),
+	DEVMETHOD(bus_write_ivar,		mv_pcib_write_ivar),
+	DEVMETHOD(bus_alloc_resource,		mv_pcib_alloc_resource),
+	DEVMETHOD(bus_release_resource,		mv_pcib_release_resource),
 	DEVMETHOD(bus_activate_resource,	bus_generic_activate_resource),
 	DEVMETHOD(bus_deactivate_resource,	bus_generic_deactivate_resource),
 	DEVMETHOD(bus_setup_intr,		bus_generic_setup_intr),
 	DEVMETHOD(bus_teardown_intr,		bus_generic_teardown_intr),
 
 	/* pcib interface */
-	DEVMETHOD(pcib_maxslots,		pcib_mbus_maxslots),
-	DEVMETHOD(pcib_read_config,		pcib_mbus_read_config),
-	DEVMETHOD(pcib_write_config,		pcib_mbus_write_config),
-	DEVMETHOD(pcib_route_interrupt,		pcib_route_interrupt),
+	DEVMETHOD(pcib_maxslots,		mv_pcib_maxslots),
+	DEVMETHOD(pcib_read_config,		mv_pcib_read_config),
+	DEVMETHOD(pcib_write_config,		mv_pcib_write_config),
+	DEVMETHOD(pcib_route_interrupt,		mv_pcib_route_interrupt),
+
+	/* OFW bus interface */
+	DEVMETHOD(ofw_bus_get_compat,   ofw_bus_gen_get_compat),
+	DEVMETHOD(ofw_bus_get_model,    ofw_bus_gen_get_model),
+	DEVMETHOD(ofw_bus_get_name,     ofw_bus_gen_get_name),
+	DEVMETHOD(ofw_bus_get_node,     ofw_bus_gen_get_node),
+	DEVMETHOD(ofw_bus_get_type,     ofw_bus_gen_get_type),
 
 	{ 0, 0 }
 };
 
-static driver_t pcib_mbus_driver = {
+static driver_t mv_pcib_driver = {
 	"pcib",
-	pcib_mbus_methods,
-	sizeof(struct pcib_mbus_softc),
+	mv_pcib_methods,
+	sizeof(struct mv_pcib_softc),
 };
 
 devclass_t pcib_devclass;
 
-DRIVER_MODULE(pcib, mbus, pcib_mbus_driver, pcib_devclass, 0, 0);
+DRIVER_MODULE(pcib, fdtbus, mv_pcib_driver, pcib_devclass, 0, 0);
 
 static struct mtx pcicfg_mtx;
 
-static inline void
-pcib_write_irq_mask(struct pcib_mbus_softc *sc, uint32_t mask)
-{
-
-	if (!sc->sc_info->op_type != MV_TYPE_PCI)
-		return;
-
-	bus_space_write_4(sc->sc_bst, sc->sc_bsh,
-	    PCIE_REG_IRQ_MASK, mask);
-}
-
-static void
-pcib_mbus_hw_cfginit(void)
-{
-	static int opened = 0;
-
-	if (opened)
-		return;
-
-	mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
-	opened = 1;
-}
-
-static uint32_t
-pcib_mbus_hw_cfgread(struct pcib_mbus_softc *sc, u_int bus, u_int slot,
-    u_int func, u_int reg, int bytes)
-{
-	uint32_t addr, data, ca, cd;
-
-	ca = (sc->sc_info->op_type != MV_TYPE_PCI) ?
-	    PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR;
-	cd = (sc->sc_info->op_type != MV_TYPE_PCI) ?
-	    PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA;
-	addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) |
-	    PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);
-
-	mtx_lock_spin(&pcicfg_mtx);
-	bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);
-
-	data = ~0;
-	switch (bytes) {
-	case 1:
-		data = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
-		    cd + (reg & 3));
-		break;
-	case 2:
-		data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh,
-		    cd + (reg & 2)));
-		break;
-	case 4:
-		data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
-		    cd));
-		break;
-	}
-	mtx_unlock_spin(&pcicfg_mtx);
-	return (data);
-}
-
-static void
-pcib_mbus_hw_cfgwrite(struct pcib_mbus_softc *sc, u_int bus, u_int slot,
-    u_int func, u_int reg, uint32_t data, int bytes)
-{
-	uint32_t addr, ca, cd;
-
-	ca = (sc->sc_info->op_type != MV_TYPE_PCI) ?
-	    PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR;
-	cd = (sc->sc_info->op_type != MV_TYPE_PCI) ?
-	    PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA;
-	addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) |
-	    PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);
-
-	mtx_lock_spin(&pcicfg_mtx);
-	bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);
-
-	switch (bytes) {
-	case 1:
-		bus_space_write_1(sc->sc_bst, sc->sc_bsh,
-		    cd + (reg & 3), data);
-		break;
-	case 2:
-		bus_space_write_2(sc->sc_bst, sc->sc_bsh,
-		    cd + (reg & 2), htole16(data));
-		break;
-	case 4:
-		bus_space_write_4(sc->sc_bst, sc->sc_bsh,
-		    cd, htole32(data));
-		break;
-	}
-	mtx_unlock_spin(&pcicfg_mtx);
-}
-
 static int
-pcib_mbus_maxslots(device_t dev)
-{
-	struct pcib_mbus_softc *sc = device_get_softc(dev);
-
-	return ((sc->sc_info->op_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX);
-}
-
-static uint32_t
-pcib_mbus_read_config(device_t dev, u_int bus, u_int slot, u_int func,
-    u_int reg, int bytes)
-{
-	struct pcib_mbus_softc *sc = device_get_softc(dev);
-
-	/* Skip self */
-	if (bus == sc->sc_busnr && slot == sc->sc_devnr)
-		return (~0U);
-
-	return (pcib_mbus_hw_cfgread(sc, bus, slot, func, reg, bytes));
-}
-
-static void
-pcib_mbus_write_config(device_t dev, u_int bus, u_int slot, u_int func,
-    u_int reg, uint32_t val, int bytes)
+mv_pcib_probe(device_t self)
 {
-	struct pcib_mbus_softc *sc = device_get_softc(dev);
-
-	/* Skip self */
-	if (bus == sc->sc_busnr && slot == sc->sc_devnr)
-		return;
-
-	pcib_mbus_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes);
-}
-
-static void
-pcib_mbus_add_child(driver_t *driver, device_t parent, struct pcib_mbus_softc *sc)
-{
-	device_t child;
-	int error;
-
-	/* Configure CPU decoding windows */
-	error = decode_win_cpu_set(sc->sc_info->op_io_win_target,
-	    sc->sc_info->op_io_win_attr, sc->sc_info->op_io_base,
-	    sc->sc_info->op_io_size, -1);
-	if (error < 0) {
-		device_printf(parent, "Could not set up CPU decode "
-		    "window for PCI IO\n");
-		return;
-	}
-	error = decode_win_cpu_set(sc->sc_info->op_mem_win_target,
-	    sc->sc_info->op_mem_win_attr, sc->sc_info->op_mem_base,
-	    sc->sc_info->op_mem_size, -1);
-	if (error < 0) {
-		device_printf(parent, "Could not set up CPU decode "
-		    "windows for PCI MEM\n");
-		return;
-	}
-
-	/* Create driver instance */
-	child = BUS_ADD_CHILD(parent, 0, driver->name, -1);
-	bus_set_resource(child, SYS_RES_MEMORY, 0,
-	    sc->sc_info->op_base, sc->sc_info->op_size);
-	device_set_softc(child, sc);
-}
-
-static void
-pcib_mbus_identify(driver_t *driver, device_t parent)
-{
-	const struct obio_pci *info = mv_pci_info;
-	struct pcib_mbus_softc *sc;
-	uint32_t control;
-
-	while (info->op_base) {
-		sc = malloc(driver->size, M_DEVBUF, M_NOWAIT | M_ZERO);
-		if (sc == NULL) {
-			device_printf(parent, "Could not allocate pcib "
-			    "memory\n");
-			break;
-		}
-		sc->sc_info = info++;
-
-		/*
-		 * PCI bridge objects are instantiated immediately. PCI-Express
-		 * bridges require more complicated handling depending on
-		 * platform configuration.
-		 */
-		if (sc->sc_info->op_type == MV_TYPE_PCI) {
-			pcib_mbus_add_child(driver, parent, sc);
-			continue;
-		}
-
-		/*
-		 * Read link configuration
-		 */
-		sc->sc_rid = 0;
-		sc->sc_res = BUS_ALLOC_RESOURCE(parent, parent, SYS_RES_MEMORY,
-		    &sc->sc_rid, sc->sc_info->op_base, sc->sc_info->op_base +
-		    sc->sc_info->op_size - 1, sc->sc_info->op_size,
-		    RF_ACTIVE);
-		if (sc->sc_res == NULL) {
-			device_printf(parent, "Could not map pcib memory\n");
-			break;
-		}
-
-		sc->sc_bst = rman_get_bustag(sc->sc_res);
-		sc->sc_bsh = rman_get_bushandle(sc->sc_res);
-
-		control = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
-		    PCIE_REG_CONTROL);
-
-		BUS_RELEASE_RESOURCE(parent, parent, SYS_RES_MEMORY, sc->sc_rid,
-		    sc->sc_res);
+	phandle_t parnode;
+
+	/*
+	 * The PCI subnode does not have the 'compatible' property, so we need
+	 * to check in the parent PCI node. However the parent is not
+	 * represented by a separate ofw_bus child, and therefore
+	 * ofw_bus_is_compatible() cannot be used, but direct fdt equivalent.
+	 */
+	parnode = OF_parent(ofw_bus_get_node(self));
+	if (parnode == 0)
+		return (ENXIO);
+	if (!(fdt_is_compatible(parnode, "mrvl,pcie") ||
+	    fdt_is_compatible(parnode, "mrvl,pci")))
+		return (ENXIO);
 
-		/*
-		 * If this PCI-E port (controller) is configured (by the
-		 * underlying firmware) with lane width other than 1x, there
-		 * are auxiliary resources defined for aggregating more width
-		 * on our lane. Skip all such entries as they are not
-		 * standalone ports and must not have a device object
-		 * instantiated.
-		 */
-		if ((control & PCIE_CTRL_LINK1X) == 0)
-			while (info->op_base &&
-			    info->op_type == MV_TYPE_PCIE_AGGR_LANE)
-				info++;
+	device_set_desc(self, "Marvell Integrated PCI/PCI-E Controller");
 
-		pcib_mbus_add_child(driver, parent, sc);
-	}
+	return (BUS_PROBE_DEFAULT);
 }
 
 static int
-pcib_mbus_probe(device_t self)
+mv_pcib_attach(device_t self)
 {
-	char buf[128];
-	struct pcib_mbus_softc *sc;
-	const char *id, *type;
+	struct mv_pcib_softc *sc;
+	phandle_t node, parnode;
 	uint32_t val;
-	int rv = ENOENT, bus, dev;
+	int err;
 
 	sc = device_get_softc(self);
+	sc->sc_dev = self;
 
-	sc->sc_rid = 0;
-	sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid,
-	    RF_ACTIVE);
-	if (sc->sc_res == NULL) {
-		device_printf(self, "Could not map memory\n");
+	parnode = OF_parent(ofw_bus_get_node(self));
+	if (fdt_is_compatible(parnode, "mrvl,pcie")) {
+		sc->sc_type = MV_TYPE_PCIE;
+		sc->sc_mem_win_target = MV_WIN_PCIE_MEM_TARGET;
+		sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR;
+		sc->sc_io_win_target = MV_WIN_PCIE_IO_TARGET;
+		sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR;
+#ifdef SOC_MV_ORION
+	} else if (fdt_is_compatible(parnode, "mrvl,pci")) {
+		sc->sc_type = MV_TYPE_PCI;
+		sc->sc_mem_win_target = MV_WIN_PCI_MEM_TARGET;
+		sc->sc_mem_win_attr = MV_WIN_PCI_MEM_ATTR;
+		sc->sc_io_win_target = MV_WIN_PCI_IO_TARGET;
+		sc->sc_io_win_attr = MV_WIN_PCI_IO_ATTR;
+#endif
+	} else
 		return (ENXIO);
-	}
 
-	sc->sc_bst = rman_get_bustag(sc->sc_res);
-	sc->sc_bsh = rman_get_bushandle(sc->sc_res);
+	node = ofw_bus_get_node(self);
 
-	pcib_mbus_hw_cfginit();
-
-	/* Retrieve configuration of the bridge */
-	if (sc->sc_info->op_type == MV_TYPE_PCI) {
-		val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
-		    PCI_REG_P2P_CONF);
-		bus = sc->sc_busnr = (val & P2P_CONF_BUS_MASK) >>
-		    P2P_CONF_BUS_OFFS;
-		dev = sc->sc_devnr = (val & P2P_CONF_DEV_MASK) >>
-		    P2P_CONF_DEV_OFFS;
-	} else {
-		val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS);
-		if (val & STATUS_LINK_DOWN)
-			goto out;
-		bus = sc->sc_busnr = (val & STATUS_BUS_MASK) >> STATUS_BUS_OFFS;
-		dev = sc->sc_devnr = (val & STATUS_DEV_MASK) >> STATUS_DEV_OFFS;
-	}
-
-	val = pcib_mbus_hw_cfgread(sc, bus, dev, 0, PCIR_VENDOR, 2);
-	if (val != PCI_VENDORID_MRVL)
-		goto out;
-
-	val = pcib_mbus_hw_cfgread(sc, bus, dev, 0, PCIR_DEVICE, 2);
-	switch (val) {
-	case 0x5281:
-		id = "88F5281";
-		break;
-	case 0x5182:
-		id = "88F5182";
-		break;
-	case 0x6281:
-		id = "88F6281";
-		break;
-	case 0x6381:
-		id = "MV78100 Z0";
-		break;
-	case 0x7810:
-		id = "MV78100";
-		break;
-	case 0x7820:
-		/*
-		 * According to documentation ID 0x7820 is assigned to MV78200.
-		 * However some MV78100 chips also use it.
-		 */
-		id = "MV78100/MV78200";
-		break;
-	default:
-		device_printf(self, "unknown Marvell PCI bridge: %x\n", val);
-		goto out;
-	}
-
-	type = "PCI";
-	val = pcib_mbus_hw_cfgread(sc, bus, dev, 0, PCIR_CAP_PTR, 1);
-	while (val != 0) {
-		val = pcib_mbus_hw_cfgread(sc, bus, dev, 0, val, 2);
-		switch (val & 0xff) {
-		case PCIY_PCIX:
-			type = "PCI-X";
-			break;
-		case PCIY_EXPRESS:
-			type = "PCI-Express";
-			break;
-		}
-		val = (val >> 8) & 0xff;
+	/*
+	 * Get PCI interrupt info.
+	 */
+	if (mv_pcib_intr_info(node, sc) != 0) {
+		device_printf(self, "could not retrieve interrupt info\n");
+		return (ENXIO);
 	}
 
-	snprintf(buf, sizeof(buf), "Marvell %s %s host controller", id,
-	    type);
-	device_set_desc_copy(self, buf);
-	rv = BUS_PROBE_DEFAULT;
-out:
-	bus_release_resource(self, SYS_RES_MEMORY, sc->sc_rid, sc->sc_res);
-	return (rv);
-}
-
-static int
-pcib_mbus_attach(device_t self)
-{
-	struct pcib_mbus_softc *sc;
-	uint32_t val;
-	int err;
-
-	sc = device_get_softc(self);
-	sc->sc_dev = self;
-
+	/*
+	 * Retrieve our mem-mapped registers range.
+	 */
 	sc->sc_rid = 0;
 	sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid,
 	    RF_ACTIVE);
 	if (sc->sc_res == NULL) {
-		device_printf(self, "Could not map memory\n");
+		device_printf(self, "could not map memory\n");
 		return (ENXIO);
 	}
 	sc->sc_bst = rman_get_bustag(sc->sc_res);
 	sc->sc_bsh = rman_get_bushandle(sc->sc_res);
 
-	/* Enable PCI bridge */
-	val = pcib_mbus_hw_cfgread(sc, sc->sc_busnr, sc->sc_devnr, 0,
+	/*
+	 * Configure decode windows for PCI(E) access.
+	 */
+	if (mv_pcib_decode_win(node, sc) != 0)
+		return (ENXIO);
+
+	mv_pcib_hw_cfginit();
+
+	/*
+	 * Enable PCI bridge.
+	 */
+	val = mv_pcib_hw_cfgread(sc, sc->sc_busnr, sc->sc_devnr, 0,
 	    PCIR_COMMAND, 2);
 	val |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
 	    PCIM_CMD_PORTEN;
-	pcib_mbus_hw_cfgwrite(sc, sc->sc_busnr, sc->sc_devnr, 0,
+	mv_pcib_hw_cfgwrite(sc, sc->sc_busnr, sc->sc_devnr, 0,
 	    PCIR_COMMAND, val, 2);
 
-	sc->sc_iomem_base = sc->sc_info->op_mem_base;
-	sc->sc_iomem_size = sc->sc_info->op_mem_size;
-	sc->sc_iomem_alloc = sc->sc_info->op_mem_base;
-
-	sc->sc_ioport_base = sc->sc_info->op_io_base;
-	sc->sc_ioport_size = sc->sc_info->op_io_size;
-	sc->sc_ioport_alloc = sc->sc_info->op_io_base;
+	sc->sc_mem_alloc = sc->sc_mem_base;
+	sc->sc_io_alloc = sc->sc_io_base;
 
-	sc->sc_iomem_rman.rm_type = RMAN_ARRAY;
-	err = rman_init(&sc->sc_iomem_rman);
+	sc->sc_mem_rman.rm_type = RMAN_ARRAY;
+	err = rman_init(&sc->sc_mem_rman);
 	if (err)
 		return (err);
 
-	sc->sc_ioport_rman.rm_type = RMAN_ARRAY;
-	err = rman_init(&sc->sc_ioport_rman);
+	sc->sc_io_rman.rm_type = RMAN_ARRAY;
+	err = rman_init(&sc->sc_io_rman);
 	if (err) {
-		rman_fini(&sc->sc_iomem_rman);
+		rman_fini(&sc->sc_mem_rman);
 		return (err);
 	}
 
-	err = rman_manage_region(&sc->sc_iomem_rman, sc->sc_iomem_base,
-	    sc->sc_iomem_base + sc->sc_iomem_size - 1);
+	err = rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base,
+	    sc->sc_mem_base + sc->sc_mem_size - 1);
 	if (err)
 		goto error;
 
-	err = rman_manage_region(&sc->sc_ioport_rman, sc->sc_ioport_base,
-	    sc->sc_ioport_base + sc->sc_ioport_size - 1);
+	err = rman_manage_region(&sc->sc_io_rman, sc->sc_io_base,
+	    sc->sc_io_base + sc->sc_io_size - 1);
 	if (err)
 		goto error;
 
-	err = pcib_mbus_init(sc, sc->sc_busnr, pcib_mbus_maxslots(sc->sc_dev));
+	err = mv_pcib_init(sc, sc->sc_busnr, mv_pcib_maxslots(sc->sc_dev));
 	if (err)
 		goto error;
 
@@ -566,13 +335,14 @@ pcib_mbus_attach(device_t self)
 	return (bus_generic_attach(self));
 
 error:
-	rman_fini(&sc->sc_iomem_rman);
-	rman_fini(&sc->sc_ioport_rman);
+	/* XXX SYS_RES_ should be released here */
+	rman_fini(&sc->sc_mem_rman);
+	rman_fini(&sc->sc_io_rman);
 	return (err);
 }
 
 static int
-pcib_mbus_init_bar(struct pcib_mbus_softc *sc, int bus, int slot, int func,
+mv_pcib_init_bar(struct mv_pcib_softc *sc, int bus, int slot, int func,
     int barno)
 {
 	bus_addr_t *allocp, limit;
@@ -580,28 +350,28 @@ pcib_mbus_init_bar(struct pcib_mbus_softc *sc, int bus, int slot, int func,
 	int reg, width;
 
 	reg = PCIR_BAR(barno);
-	bar = pcib_mbus_read_config(sc->sc_dev, bus, slot, func, reg, 4);
+	bar = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4);
 	if (bar == 0)
 		return (1);
 
 	/* Calculate BAR size: 64 or 32 bit (in 32-bit units) */
 	width = ((bar & 7) == 4) ? 2 : 1;
 
-	pcib_mbus_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4);
-	size = pcib_mbus_read_config(sc->sc_dev, bus, slot, func, reg, 4);
+	mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4);
+	size = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4);
 
 	/* Get BAR type and size */
 	if (bar & 1) {
 		/* I/O port */
-		allocp = &sc->sc_ioport_alloc;
-		limit = sc->sc_ioport_base + sc->sc_ioport_size;
+		allocp = &sc->sc_io_alloc;
+		limit = sc->sc_io_base + sc->sc_io_size;
 		size &= ~0x3;
 		if ((size & 0xffff0000) == 0)
 			size |= 0xffff0000;
 	} else {
 		/* Memory */
-		allocp = &sc->sc_iomem_alloc;
-		limit = sc->sc_iomem_base + sc->sc_iomem_size;
+		allocp = &sc->sc_mem_alloc;
+		limit = sc->sc_mem_base + sc->sc_mem_size;
 		size &= ~0xF;
 	}
 	mask = ~size;
@@ -619,108 +389,61 @@ pcib_mbus_init_bar(struct pcib_mbus_softc *sc, int bus, int slot, int func,
 		printf("PCI %u:%u:%u: reg %x: size=%08x: addr=%08x\n",
 		    bus, slot, func, reg, size, addr);
 
-	pcib_mbus_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
+	mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
 	if (width == 2)
-		pcib_mbus_write_config(sc->sc_dev, bus, slot, func, reg + 4,
+		mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4,
 		    0, 4);
 
 	return (width);
 }
 
 static void
-pcib_mbus_init_bridge(struct pcib_mbus_softc *sc, int bus, int slot, int func)
+mv_pcib_init_bridge(struct mv_pcib_softc *sc, int bus, int slot, int func)
 {
 	bus_addr_t io_base, mem_base;
 	uint32_t io_limit, mem_limit;
 	int secbus;
 
-	io_base = sc->sc_info->op_io_base;
-	io_limit = io_base + sc->sc_info->op_io_size - 1;
-	mem_base = sc->sc_info->op_mem_base;
-	mem_limit = mem_base + sc->sc_info->op_mem_size - 1;
+	io_base = sc->sc_io_base;
+	io_limit = io_base + sc->sc_io_size - 1;
+	mem_base = sc->sc_mem_base;
+	mem_limit = mem_base + sc->sc_mem_size - 1;
 
 	/* Configure I/O decode registers */
-	pcib_mbus_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1,
+	mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1,
 	    io_base >> 8, 1);
-	pcib_mbus_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEH_1,
+	mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEH_1,
 	    io_base >> 16, 2);
-	pcib_mbus_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITL_1,
+	mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITL_1,
 	    io_limit >> 8, 1);
-	pcib_mbus_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITH_1,
+	mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITH_1,
 	    io_limit >> 16, 2);
 
 	/* Configure memory decode registers */
-	pcib_mbus_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMBASE_1,
+	mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMBASE_1,
 	    mem_base >> 16, 2);
-	pcib_mbus_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMLIMIT_1,
+	mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMLIMIT_1,
 	    mem_limit >> 16, 2);
 
 	/* Disable memory prefetch decode */
-	pcib_mbus_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEL_1,
+	mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEL_1,
 	    0x10, 2);
-	pcib_mbus_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEH_1,
+	mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEH_1,
 	    0x0, 4);
-	pcib_mbus_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITL_1,
+	mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITL_1,
 	    0xF, 2);
-	pcib_mbus_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITH_1,
+	mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITH_1,
 	    0x0, 4);
 
-	secbus = pcib_mbus_read_config(sc->sc_dev, bus, slot, func,
+	secbus = mv_pcib_read_config(sc->sc_dev, bus, slot, func,
 	    PCIR_SECBUS_1, 1);
 
 	/* Configure buses behind the bridge */
-	pcib_mbus_init(sc, secbus, PCI_SLOTMAX);
+	mv_pcib_init(sc, secbus, PCI_SLOTMAX);
 }
 
 static int
-pcib_mbus_init_resources(struct pcib_mbus_softc *sc, int bus, int slot,
-    int func, int hdrtype)
-{
-	const struct obio_pci_irq_map *map = sc->sc_info->op_pci_irq_map;
-	int maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6;
-	int bar = 0, irq = -1;
-	int pin, i;
-
-	/* Program the base address registers */
-	while (bar < maxbar) {
-		i = pcib_mbus_init_bar(sc, bus, slot, func, bar);
-		bar += i;
-		if (i < 0) {
-			device_printf(sc->sc_dev,
-			    "PCI IO/Memory space exhausted\n");
-			return (ENOMEM);
-		}
-	}
-
-	/* Perform interrupt routing */
-	pin = pcib_mbus_read_config(sc->sc_dev, bus, slot, func,
-	    PCIR_INTPIN, 1);
-
-	if (map != NULL)
-		while (map->opim_irq >= 0) {
-			if ((map->opim_slot == slot || map->opim_slot < 0) &&
-			    (map->opim_pin == pin || map->opim_pin < 0))
-				irq = map->opim_irq;
-
-			map++;
-		}
-	else
-		irq = sc->sc_info->op_irq;
-
-	if (irq >= 0)
-		pcib_mbus_write_config(sc->sc_dev, bus, slot, func,
-		    PCIR_INTLINE, irq, 1);
-	else {
-		device_printf(sc->sc_dev, "Missing IRQ routing information "
-		    "for PCI device %u:%u:%u\n", bus, slot, func);
-		return (ENXIO);
-	}
-
-	return (0);
-}
-
-static int
-pcib_mbus_init(struct pcib_mbus_softc *sc, int bus, int maxslot)
+mv_pcib_init(struct mv_pcib_softc *sc, int bus, int maxslot)
 {
 	int slot, func, maxfunc, error;
 	uint8_t hdrtype, command, class, subclass;
@@ -728,7 +451,7 @@ pcib_mbus_init(struct pcib_mbus_softc *sc, int bus, int maxslot)
 	for (slot = 0; slot <= maxslot; slot++) {
 		maxfunc = 0;
 		for (func = 0; func <= maxfunc; func++) {
-			hdrtype = pcib_mbus_read_config(sc->sc_dev, bus, slot,
+			hdrtype = mv_pcib_read_config(sc->sc_dev, bus, slot,
 			    func, PCIR_HDRTYPE, 1);
 
 			if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
@@ -737,13 +460,13 @@ pcib_mbus_init(struct pcib_mbus_softc *sc, int bus, int maxslot)
 			if (func == 0 && (hdrtype & PCIM_MFDEV))
 				maxfunc = PCI_FUNCMAX;
 
-			command = pcib_mbus_read_config(sc->sc_dev, bus, slot,
+			command = mv_pcib_read_config(sc->sc_dev, bus, slot,
 			    func, PCIR_COMMAND, 1);
 			command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
-			pcib_mbus_write_config(sc->sc_dev, bus, slot, func,
+			mv_pcib_write_config(sc->sc_dev, bus, slot, func,
 			    PCIR_COMMAND, command, 1);
 
-			error = pcib_mbus_init_resources(sc, bus, slot, func,
+			error = mv_pcib_init_all_bars(sc, bus, slot, func,
 			    hdrtype);
 
 			if (error)
@@ -751,20 +474,20 @@ pcib_mbus_init(struct pcib_mbus_softc *sc, int bus, int maxslot)
 
 			command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
 			    PCIM_CMD_PORTEN;
-			pcib_mbus_write_config(sc->sc_dev, bus, slot, func,
+			mv_pcib_write_config(sc->sc_dev, bus, slot, func,
 			    PCIR_COMMAND, command, 1);
 
 			/* Handle PCI-PCI bridges */
-			class = pcib_mbus_read_config(sc->sc_dev, bus, slot,
+			class = mv_pcib_read_config(sc->sc_dev, bus, slot,
 			    func, PCIR_CLASS, 1);
-			subclass = pcib_mbus_read_config(sc->sc_dev, bus, slot,
+			subclass = mv_pcib_read_config(sc->sc_dev, bus, slot,
 			    func, PCIR_SUBCLASS, 1);
 
 			if (class != PCIC_BRIDGE ||
 			    subclass != PCIS_BRIDGE_PCI)
 				continue;
 
-			pcib_mbus_init_bridge(sc, bus, slot, func);
+			mv_pcib_init_bridge(sc, bus, slot, func);
 		}
 	}
 
@@ -774,20 +497,43 @@ pcib_mbus_init(struct pcib_mbus_softc *sc, int bus, int maxslot)
 	return (0);
 }
 
+static int
+mv_pcib_init_all_bars(struct mv_pcib_softc *sc, int bus, int slot,
+    int func, int hdrtype)
+{
+	int maxbar, bar, i;
+
+	maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6;
+	bar = 0;
+
+	/* Program the base address registers */
+	while (bar < maxbar) {
+		i = mv_pcib_init_bar(sc, bus, slot, func, bar);
+		bar += i;
+		if (i < 0) {
+			device_printf(sc->sc_dev,
+			    "PCI IO/Memory space exhausted\n");
+			return (ENOMEM);
+		}
+	}
+
+	return (0);
+}
+
 static struct resource *
-pcib_mbus_alloc_resource(device_t dev, device_t child, int type, int *rid,
+mv_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
     u_long start, u_long end, u_long count, u_int flags)
 {
-	struct pcib_mbus_softc *sc = device_get_softc(dev);
+	struct mv_pcib_softc *sc = device_get_softc(dev);
 	struct rman *rm = NULL;
 	struct resource *res;
 
 	switch (type) {
 	case SYS_RES_IOPORT:
-		rm = &sc->sc_ioport_rman;
+		rm = &sc->sc_io_rman;
 		break;
 	case SYS_RES_MEMORY:
-		rm = &sc->sc_iomem_rman;
+		rm = &sc->sc_mem_rman;
 		break;
 	default:
 		return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
@@ -799,7 +545,7 @@ pcib_mbus_alloc_resource(device_t dev, device_t child, int type, int *rid,
 		return (NULL);
 
 	rman_set_rid(res, *rid);
-	rman_set_bustag(res, obio_tag);
+	rman_set_bustag(res, fdtbus_bs_tag);
 	rman_set_bushandle(res, start);
 
 	if (flags & RF_ACTIVE)
@@ -812,7 +558,7 @@ pcib_mbus_alloc_resource(device_t dev, device_t child, int type, int *rid,
 }
 
 static int
-pcib_mbus_release_resource(device_t dev, device_t child, int type, int rid,
+mv_pcib_release_resource(device_t dev, device_t child, int type, int rid,
     struct resource *res)
 {
 
@@ -824,9 +570,9 @@ pcib_mbus_release_resource(device_t dev, device_t child, int type, int rid,
 }
 
 static int
-pcib_mbus_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
+mv_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
 {
-	struct pcib_mbus_softc *sc = device_get_softc(dev);
+	struct mv_pcib_softc *sc = device_get_softc(dev);
 
 	switch (which) {
 	case PCIB_IVAR_BUS:
@@ -841,9 +587,9 @@ pcib_mbus_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
 }
 
 static int
-pcib_mbus_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
+mv_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
 {
-	struct pcib_mbus_softc *sc = device_get_softc(dev);
+	struct mv_pcib_softc *sc = device_get_softc(dev);
 
 	switch (which) {
 	case PCIB_IVAR_BUS:
@@ -853,3 +599,215 @@ pcib_mbus_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
 
 	return (ENOENT);
 }
+
+static inline void
+pcib_write_irq_mask(struct mv_pcib_softc *sc, uint32_t mask)
+{
+
+	if (!sc->sc_type != MV_TYPE_PCI)
+		return;
+
+	bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_IRQ_MASK, mask);
+}
+
+static void
+mv_pcib_hw_cfginit(void)
+{
+	static int opened = 0;
+
+	if (opened)
+		return;
+
+	mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
+	opened = 1;
+}
+
+static uint32_t
+mv_pcib_hw_cfgread(struct mv_pcib_softc *sc, u_int bus, u_int slot,
+    u_int func, u_int reg, int bytes)
+{
+	uint32_t addr, data, ca, cd;
+
+	ca = (sc->sc_type != MV_TYPE_PCI) ?
+	    PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR;
+	cd = (sc->sc_type != MV_TYPE_PCI) ?
+	    PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA;
+	addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) |
+	    PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);
+
+	mtx_lock_spin(&pcicfg_mtx);
+	bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);
+
+	data = ~0;
+	switch (bytes) {
+	case 1:
+		data = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
+		    cd + (reg & 3));
+		break;
+	case 2:
+		data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh,
+		    cd + (reg & 2)));
+		break;
+	case 4:
+		data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
+		    cd));
+		break;
+	}
+	mtx_unlock_spin(&pcicfg_mtx);
+	return (data);
+}
+
+static void
+mv_pcib_hw_cfgwrite(struct mv_pcib_softc *sc, u_int bus, u_int slot,
+    u_int func, u_int reg, uint32_t data, int bytes)
+{
+	uint32_t addr, ca, cd;
+
+	ca = (sc->sc_type != MV_TYPE_PCI) ?
+	    PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR;
+	cd = (sc->sc_type != MV_TYPE_PCI) ?
+	    PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA;
+	addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) |
+	    PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);
+
+	mtx_lock_spin(&pcicfg_mtx);
+	bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);
+
+	switch (bytes) {
+	case 1:
+		bus_space_write_1(sc->sc_bst, sc->sc_bsh,
+		    cd + (reg & 3), data);
+		break;
+	case 2:
+		bus_space_write_2(sc->sc_bst, sc->sc_bsh,
+		    cd + (reg & 2), htole16(data));
+		break;
+	case 4:
+		bus_space_write_4(sc->sc_bst, sc->sc_bsh,
+		    cd, htole32(data));
+		break;
+	}
+	mtx_unlock_spin(&pcicfg_mtx);
+}
+
+static int
+mv_pcib_maxslots(device_t dev)
+{
+	struct mv_pcib_softc *sc = device_get_softc(dev);
+
+	return ((sc->sc_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX);
+}
+
+static uint32_t
+mv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
+    u_int reg, int bytes)
+{
+	struct mv_pcib_softc *sc = device_get_softc(dev);
+
+	/* Skip self */
+	if (bus == sc->sc_busnr && slot == sc->sc_devnr)
+		return (~0U);
+
+	return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes));
+}
+
+static void
+mv_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
+    u_int reg, uint32_t val, int bytes)
+{
+	struct mv_pcib_softc *sc = device_get_softc(dev);
+
+	/* Skip self */
+	if (bus == sc->sc_busnr && slot == sc->sc_devnr)
+		return;
+
+	mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes);
+}
+
+static int
+mv_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
+{
+	struct mv_pcib_softc *sc;
+	int err, interrupt;
+
+	sc = device_get_softc(pcib);
+
+	err = fdt_pci_route_intr(pci_get_bus(dev), pci_get_slot(dev),
+	    pci_get_function(dev), pin, &sc->sc_intr_info, &interrupt);
+	if (err == 0)
+		return (interrupt);
+
+	device_printf(pcib, "could not route pin %d for device %d.%d\n",
+	    pin, pci_get_slot(dev), pci_get_function(dev));
+	return (PCI_INVALID_IRQ);
+}
+
+static int
+mv_pcib_decode_win(phandle_t node, struct mv_pcib_softc *sc)
+{
+	struct fdt_pci_range io_space, mem_space;
+	device_t dev;
+	int error;
+
+	dev = sc->sc_dev;
+
+	if ((error = fdt_pci_ranges(node, &io_space, &mem_space)) != 0) {
+		device_printf(dev, "could not retrieve 'ranges' data\n");
+		return (error);
+	}
+
+	/* Configure CPU decoding windows */
+	error = decode_win_cpu_set(sc->sc_io_win_target,
+	    sc->sc_io_win_attr, io_space.base_parent, io_space.len, -1);
+	if (error < 0) {
+		device_printf(dev, "could not set up CPU decode "
+		    "window for PCI IO\n");
+		return (ENXIO);
+	}
+	error = decode_win_cpu_set(sc->sc_mem_win_target,
+	    sc->sc_mem_win_attr, mem_space.base_parent, mem_space.len, -1);
+	if (error < 0) {
+		device_printf(dev, "could not set up CPU decode "
+		    "windows for PCI MEM\n");
+		return (ENXIO);
+	}
+
+	sc->sc_io_base = io_space.base_parent;
+	sc->sc_io_size = io_space.len;
+
+	sc->sc_mem_base = mem_space.base_parent;
+	sc->sc_mem_size = mem_space.len;
+
+	return (0);
+}
+
+static int
+mv_pcib_intr_info(phandle_t node, struct mv_pcib_softc *sc)
+{
+	int error;
+
+	if ((error = fdt_pci_intr_info(node, &sc->sc_intr_info)) != 0)
+		return (error);
+
+	return (0);
+}
+
+#if 0
+		control = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
+		    PCIE_REG_CONTROL);
+
+		/*
+		 * If this PCI-E port (controller) is configured (by the
+		 * underlying firmware) with lane width other than 1x, there
+		 * are auxiliary resources defined for aggregating more width
+		 * on our lane. Skip all such entries as they are not
+		 * standalone ports and must not have a device object
+		 * instantiated.
+		 */
+		if ((control & PCIE_CTRL_LINK1X) == 0)
+			while (info->op_base &&
+			    info->op_type == MV_TYPE_PCIE_AGGR_LANE)
+				info++;
+
+		mv_pcib_add_child(driver, parent, sc);
+#endif