MFC r257738, r259202, r258410, r260288, r260292, r260294, r260320, r260323,

    r260326, r260327, r260331, r260333, r260340, r260371, r260372, r260373,
    r260374, r260375

  Add common bus_space tag definition shared for most supported ARMv6/v7 SoCs.
  Correct license statements to reflect the fact that these files were all
  derived from sys/arm/mv/bus_space.c.

  In pmap_unmapdev(), remember the size, and use that as an argument to
  kva_free(), or we'd end up always passing it a size of 0

  In pmap_mapdev(), first check whether a static mapping exists,

  Convert TI static device mapping to use the new arm_devmap_add_entry(),

  Use the common armv6 fdt_bus_tag defintion for tegra instead of a local copy.

  Eliminate use of fdt_immr_addr(), it's not needed for tegra

  Convert lpc from using fdt_immr style to arm_devmap_add_entry() to make
  static device mappings.

  Retire machine/fdt.h as a header used by MI code, as its function is now
  obsolete. This involves the following pieces:
  - Remove it entirely on PowerPC, where it is not used by MD code either
  - Remove all references to machine/fdt.h in non-architecture-specific code
    (aside from uart_cpu_fdt.c, shared by ARM and MIPS, and so is somewhat
    non-arch-specific).
  - Fix code relying on header pollution from machine/fdt.h includes
  - Legacy fdtbus.c (still used on x86 FDT systems) now passes resource
    requests to its parent (nexus). This allows x86 FDT devices to allocate
    both memory and IO requests and removes the last notionally MI use of
    fdtbus_bs_tag.
  - On those architectures that retain a machine/fdt.h, unused bits like
    FDT_MAP_IRQ and FDT_INTR_MAX have been removed.

  Add #include <machine/fdt.h> to a few files that used to get it via pollution

  Enable the mv cesa security/crypto device by providing the required property
  in the dts source, and adding the right devices to the kernel config.

  Remove dev/fdt/fdt_pci.c, which was code specific to Marvell ARM SoCs,
  related to setting up static device mappings.  Since it was only used by
  arm/mv/mv_pci.c, it's now just static functions within that file, plus
  one public function that gets called only from arm/mv/mv_machdep.c.

  Switch RPi to using arm_devmap_add_entry() to set up static device mapping.

  Allow 'no static device mappings' to potentially work.

  Don't try to find a static mapping before calling pmap_mapdev(), that logic
  is now part of pmap_mapdev() and doesn't need to be duplicated here.

 Switch a10 to using arm_devmap_add_entry() to set up static device mapping.

4 files changed, 42 insertions, 38 deletions

diff --git a/sys/arm/lpc/lpc_gpio.c b/sys/arm/lpc/lpc_gpio.c
index 0b97b07..33b32ee 100644
--- a/sys/arm/lpc/lpc_gpio.c
+++ b/sys/arm/lpc/lpc_gpio.c
@@ -502,12 +502,18 @@ lpc_gpio_get_state(device_t dev, int pin, int *state)
 void
 platform_gpio_init()
 {
+	bus_space_tag_t bst;
+	bus_space_handle_t bsh;
+
+	bst = fdtbus_bs_tag;
+
 	/* Preset SPI devices CS pins to one */
-	bus_space_write_4(fdtbus_bs_tag, 
-	    LPC_GPIO_BASE, LPC_GPIO_P3_OUTP_SET,
+	bus_space_map(bst, LPC_GPIO_PHYS_BASE, LPC_GPIO_SIZE, 0, &bsh);
+	bus_space_write_4(bst, bsh, LPC_GPIO_P3_OUTP_SET,
 	    1 << (SSD1289_CS_PIN - LPC_GPIO_GPO_00(0)) |
 	    1 << (SSD1289_DC_PIN - LPC_GPIO_GPO_00(0)) |
 	    1 << (ADS7846_CS_PIN - LPC_GPIO_GPO_00(0)));	
+	bus_space_unmap(bst, bsh, LPC_GPIO_SIZE);
 }
 
 static device_method_t lpc_gpio_methods[] = {
diff --git a/sys/arm/lpc/lpc_machdep.c b/sys/arm/lpc/lpc_machdep.c
index a900997..0cdfd03 100644
--- a/sys/arm/lpc/lpc_machdep.c
+++ b/sys/arm/lpc/lpc_machdep.c
@@ -50,6 +50,7 @@ __FBSDID("$FreeBSD$");
 #include <vm/pmap.h>
 
 #include <machine/bus.h>
+#include <machine/fdt.h>
 #include <machine/devmap.h>
 #include <machine/machdep.h>
 
@@ -57,21 +58,17 @@ __FBSDID("$FreeBSD$");
 #include <arm/lpc/lpcvar.h>
 
 #include <dev/fdt/fdt_common.h>
-#include <dev/ic/ns16550.h>
 
 vm_offset_t
 initarm_lastaddr(void)
 {
 
-	return (fdt_immr_va);
+	return (arm_devmap_lastaddr());
 }
 
 void
 initarm_early_init(void)
 {
-
-	if (fdt_immr_addr(LPC_DEV_BASE) != 0)
-		while (1);
 }
 
 void
@@ -89,28 +86,16 @@ initarm_late_init(void)
 {
 }
 
-#define FDT_DEVMAP_MAX	(1 + 2 + 1 + 1)
-static struct arm_devmap_entry fdt_devmap[FDT_DEVMAP_MAX] = {
-	{ 0, 0, 0, 0, 0, }
-};
-
 /*
- * Construct pmap_devmap[] with DT-derived config data.
+ * Add a single static device mapping.
+ * The values used were taken from the ranges property of the SoC node in the
+ * dts file when this code was converted to arm_devmap_add_entry().
  */
 int
 initarm_devmap_init(void)
 {
 
-	/*
-	 * IMMR range.
-	 */
-	fdt_devmap[0].pd_va = fdt_immr_va;
-	fdt_devmap[0].pd_pa = fdt_immr_pa;
-	fdt_devmap[0].pd_size = fdt_immr_size;
-	fdt_devmap[0].pd_prot = VM_PROT_READ | VM_PROT_WRITE;
-	fdt_devmap[0].pd_cache = PTE_NOCACHE;
-	
-	arm_devmap_register_table(&fdt_devmap[0]);
+	arm_devmap_add_entry(LPC_DEV_PHYS_BASE, LPC_DEV_SIZE);
 	return (0);
 }
 
@@ -131,15 +116,24 @@ bus_dma_get_range_nb(void)
 void
 cpu_reset(void)
 {
+	bus_space_tag_t bst;
+	bus_space_handle_t bsh;
+
+	bst = fdtbus_bs_tag;
+
 	/* Enable WDT */
-	bus_space_write_4(fdtbus_bs_tag, 
-	    LPC_CLKPWR_BASE, LPC_CLKPWR_TIMCLK_CTRL,
+	bus_space_map(bst, LPC_CLKPWR_PHYS_BASE, LPC_CLKPWR_SIZE, 0, &bsh);
+	bus_space_write_4(bst, bsh, LPC_CLKPWR_TIMCLK_CTRL,
 	    LPC_CLKPWR_TIMCLK_CTRL_WATCHDOG);
+	bus_space_unmap(bst, bsh, LPC_CLKPWR_SIZE);
 
 	/* Instant assert of RESETOUT_N with pulse length 1ms */
-	bus_space_write_4(fdtbus_bs_tag, LPC_WDTIM_BASE, LPC_WDTIM_PULSE, 13000);
-	bus_space_write_4(fdtbus_bs_tag, LPC_WDTIM_BASE, LPC_WDTIM_MCTRL, 0x70);
+	bus_space_map(bst, LPC_WDTIM_PHYS_BASE, LPC_WDTIM_SIZE, 0, &bsh);
+	bus_space_write_4(bst, bsh, LPC_WDTIM_PULSE, 13000);
+	bus_space_write_4(bst, bsh, LPC_WDTIM_MCTRL, 0x70);
+	bus_space_unmap(bst, bsh, LPC_WDTIM_SIZE);
 
-	for (;;);
+	for (;;)
+		continue;
 }
 
diff --git a/sys/arm/lpc/lpc_mmc.c b/sys/arm/lpc/lpc_mmc.c
index 3aa6d47..257487d 100644
--- a/sys/arm/lpc/lpc_mmc.c
+++ b/sys/arm/lpc/lpc_mmc.c
@@ -507,14 +507,14 @@ lpc_mmc_setup_xfer(struct lpc_mmc_softc *sc, struct mmc_data *data)
 	if (data->flags & MMC_DATA_READ) {
 		sc->lm_xfer_direction = DIRECTION_READ;
 		lpc_dmac_setup_transfer(sc->lm_dev, LPC_MMC_DMACH_READ,
-		    LPC_SD_BASE + LPC_SD_FIFO, sc->lm_buffer_phys,
+		    LPC_SD_PHYS_BASE + LPC_SD_FIFO, sc->lm_buffer_phys,
 		    data_words, 0);
 	}
 
 	if (data->flags & MMC_DATA_WRITE) {
 		sc->lm_xfer_direction = DIRECTION_WRITE;
 		lpc_dmac_setup_transfer(sc->lm_dev, LPC_MMC_DMACH_WRITE,
-		    sc->lm_buffer_phys, LPC_SD_BASE + LPC_SD_FIFO,
+		    sc->lm_buffer_phys, LPC_SD_PHYS_BASE + LPC_SD_FIFO,
 		    data_words, 0);
 	}
 
diff --git a/sys/arm/lpc/lpcreg.h b/sys/arm/lpc/lpcreg.h
index 557d9b7..b63dfbc 100644
--- a/sys/arm/lpc/lpcreg.h
+++ b/sys/arm/lpc/lpcreg.h
@@ -32,7 +32,6 @@
 #define	LPC_DEV_PHYS_BASE		0x40000000
 #define	LPC_DEV_P5_PHYS_BASE		0x20000000
 #define	LPC_DEV_P6_PHYS_BASE		0x30000000
-#define	LPC_DEV_BASE			0xd0000000
 #define	LPC_DEV_SIZE			0x10000000
 
 /*
@@ -88,7 +87,7 @@
 /*
  * Watchdog timer. (from UM10326: LPC32x0 User manual, page 572)
  */
-#define	LPC_WDTIM_BASE			(LPC_DEV_BASE + 0x3c000)
+#define	LPC_WDTIM_PHYS_BASE		(LPC_DEV_PHYS_BASE + 0x3c000)
 #define	LPC_WDTIM_INT			0x00
 #define	LPC_WDTIM_CTRL			0x04
 #define	LPC_WDTIM_COUNTER		0x08
@@ -97,11 +96,12 @@
 #define	LPC_WDTIM_EMR			0x14
 #define	LPC_WDTIM_PULSE			0x18
 #define	LPC_WDTIM_RES			0x1c
+#define	LPC_WDTIM_SIZE			0x20
 
 /*
  * Clocking and power control. (from UM10326: LPC32x0 User manual, page 58)
  */
-#define	LPC_CLKPWR_BASE			(LPC_DEV_BASE + 0x4000)
+#define	LPC_CLKPWR_PHYS_BASE		(LPC_DEV_PHYS_BASE + 0x4000)
 #define	LPC_CLKPWR_PWR_CTRL		0x44
 #define	LPC_CLKPWR_OSC_CTRL		0x4c
 #define	LPC_CLKPWR_SYSCLK_CTRL		0x50
@@ -189,6 +189,7 @@
 #define	LPC_CLKPWR_UARTCLK_CTRL		0xe4
 #define	LPC_CLKPWR_POS0_IRAM_CTRL	0x110
 #define	LPC_CLKPWR_POS1_IRAM_CTRL	0x114
+#define	LPC_CLKPWR_SIZE			0x118
 
 /* Additional UART registers in CLKPWR address space. */
 #define	LPC_CLKPWR_UART_U3CLK		0xd0
@@ -201,9 +202,9 @@
 #define	LPC_CLKPWR_UART_IRDACLK		0xe0
 
 /* Additional UART registers */
-#define	LPC_UART_BASE			(LPC_DEV_BASE + 0x80000)
-#define	LPC_UART_CONTROL_BASE		(LPC_DEV_BASE + 0x54000)
-#define	LPC_UART5_BASE			(LPC_DEV_BASE + 0x90000)
+#define	LPC_UART_BASE			0x80000
+#define	LPC_UART_CONTROL_BASE		0x54000
+#define	LPC_UART5_BASE			0x90000
 #define	LPC_UART_CTRL			0x00
 #define	LPC_UART_CLKMODE		0x04
 #define	LPC_UART_CLKMODE_UART3(_n)	(((_n) & 0x3) << 4)
@@ -211,6 +212,7 @@
 #define	LPC_UART_CLKMODE_UART5(_n)	(((_n) & 0x3) << 8)
 #define	LPC_UART_CLKMODE_UART6(_n)	(((_n) & 0x3) << 10)
 #define	LPC_UART_LOOP			0x08
+#define	LPC_UART_CONTROL_SIZE		0x0c
 #define	LPC_UART_FIFOSIZE		64
 
 /*
@@ -236,7 +238,7 @@
 /*
  * MMC/SD controller. (from UM10326: LPC32x0 User manual, page 436)
  */
-#define	LPC_SD_BASE			(LPC_DEV_P5_PHYS_BASE + 0x98000)
+#define	LPC_SD_PHYS_BASE		(LPC_DEV_P5_PHYS_BASE + 0x98000)
 #define	LPC_SD_CLK			(13 * 1000 * 1000)	// 13Mhz
 #define	LPC_SD_POWER			0x00
 #define	LPC_SD_POWER_OPENDRAIN		(1 << 6)
@@ -535,7 +537,7 @@
 /*
  * GPIO (from UM10326: LPC32x0 User manual, page 606)
  */
-#define	LPC_GPIO_BASE			(LPC_DEV_BASE + 0x28000)
+#define	LPC_GPIO_PHYS_BASE		(LPC_DEV_PHYS_BASE + 0x28000)
 #define	LPC_GPIO_P0_COUNT		8
 #define	LPC_GPIO_P1_COUNT		24
 #define	LPC_GPIO_P2_COUNT		13
@@ -564,6 +566,8 @@
 #define	LPC_GPIO_P3_OUTP_SET		0x04
 #define	LPC_GPIO_P3_OUTP_CLR		0x08
 #define	LPC_GPIO_P3_OUTP_STATE		0x0c
+#define	LPC_GPIO_SIZE			0x80
+
 /* Aliases for logical pin numbers: */
 #define	LPC_GPIO_GPI_00(_n)		(0 + _n)
 #define	LPC_GPIO_GPI_15(_n)		(10 + _n)