MFC r262409, r262411, r262413, r262420, r262426, r262427, r262440, r262456,

    r262482, r262483, r262531,

  Move the declaration for mpentry() into a header file instead of pasting
  it into a bunch of different .c files.

  If the L2 cache type is PIPT, pass a physical address for a flush.

  Actually set the proper bit to indicate TTB shared memory.

  Add a new cache maintenance function, idcache_inv_all, to the table, and
  implementations for each of the chips we support.

  Invalidate caches immediately upon entry to init_secondary().  Also set
  the Bufferable bit in the PDE entries of the secondary processor startup
  pagetables.

  Add the bits needed to run SMP on imx6.

  Invalidate the SCU cache tag ram on all 4 cores, not just 1-3.

  Minor tweaks to the imx GPT timer

  Vybrid enhancements...
  - Pin configuration is a complete iomux register now and includes
    drive strength, pull mode, mux mode, speed, etc.
  - Add i2c devices to the tree
  - Add IPG clock
  - Add support for Quartz Module.
  - Pin configuration is a complete iomux register now and includes
    drive strength, pull mode, mux mode, speed, etc.
  - Add i2c devices to the tree
  - Add IPG clock

2 files changed, 12 insertions, 0 deletions

diff --git a/sys/arm/include/cpufunc.h b/sys/arm/include/cpufunc.h
index 0b53906..f38f9c1 100644
--- a/sys/arm/include/cpufunc.h
+++ b/sys/arm/include/cpufunc.h
@@ -104,6 +104,12 @@ struct cpu_functions {
 	 *
 	 * There are some rules that must be followed:
 	 *
+	 *	ID-cache Invalidate All:
+	 *		Unlike other functions, this one must never write back.
+	 *		It is used to intialize the MMU when it is in an unknown
+	 *		state (such as when it may have lines tagged as valid
+	 *		that belong to a previous set of mappings).
+	 *                                          
 	 *	I-cache Synch (all or range):
 	 *		The goal is to synchronize the instruction stream,
 	 *		so you may beed to write-back dirty D-cache blocks
@@ -138,6 +144,7 @@ struct cpu_functions {
 	void	(*cf_dcache_inv_range)	(vm_offset_t, vm_size_t);
 	void	(*cf_dcache_wb_range)	(vm_offset_t, vm_size_t);
 
+	void	(*cf_idcache_inv_all)	(void);
 	void	(*cf_idcache_wbinv_all)	(void);
 	void	(*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t);
 	void	(*cf_l2cache_wbinv_all) (void);
@@ -238,6 +245,7 @@ void tlb_broadcast(int);
 #define	cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s))
 #define	cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s))
 
+#define	cpu_idcache_inv_all()	cpufuncs.cf_idcache_inv_all()
 #define	cpu_idcache_wbinv_all()	cpufuncs.cf_idcache_wbinv_all()
 #define	cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s))
 #define cpu_l2cache_wbinv_all()	cpufuncs.cf_l2cache_wbinv_all()
@@ -495,6 +503,7 @@ void	armv6_dcache_wbinv_range	(vm_offset_t, vm_size_t);
 void	armv6_dcache_inv_range		(vm_offset_t, vm_size_t);
 void	armv6_dcache_wb_range		(vm_offset_t, vm_size_t);
 
+void	armv6_idcache_inv_all		(void);
 void	armv6_idcache_wbinv_all		(void);
 void	armv6_idcache_wbinv_range	(vm_offset_t, vm_size_t);
 
@@ -503,6 +512,7 @@ void	armv7_tlb_flushID		(void);
 void	armv7_tlb_flushID_SE		(u_int);
 void	armv7_icache_sync_range		(vm_offset_t, vm_size_t);
 void	armv7_idcache_wbinv_range	(vm_offset_t, vm_size_t);
+void	armv7_idcache_inv_all		(void);
 void	armv7_dcache_wbinv_all		(void);
 void	armv7_idcache_wbinv_all		(void);
 void	armv7_dcache_wbinv_range	(vm_offset_t, vm_size_t);
@@ -587,6 +597,7 @@ void	armv4_tlb_flushD	(void);
 void	armv4_tlb_flushD_SE	(u_int va);
 
 void	armv4_drain_writebuf	(void);
+void	armv4_idcache_inv_all	(void);
 #endif
 
 #if defined(CPU_IXP12X0)
diff --git a/sys/arm/include/smp.h b/sys/arm/include/smp.h
index 883c5b9..179882d 100644
--- a/sys/arm/include/smp.h
+++ b/sys/arm/include/smp.h
@@ -15,6 +15,7 @@
 #define IPI_TLB		7
 
 void	init_secondary(int cpu);
+void	mpentry(void);
 
 void	ipi_all_but_self(u_int ipi);
 void	ipi_cpu(int cpu, u_int ipi);