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| author | ian <ian@FreeBSD.org> | 2014-05-14 17:01:35 +0000 |
|---|---|---|
| committer | ian <ian@FreeBSD.org> | 2014-05-14 17:01:35 +0000 |
| commit | 4ee6f0bd3bade07595ecc84f07aa45d765a3eae1 (patch) | |
| tree | 7a01699924eb16ea53bc6b1e046064461b0a836e /sys/arm/include | |
| parent | 13afdc288fd9e982249ab19116c195578ff90fa1 (diff) | |
| download | FreeBSD-src-4ee6f0bd3bade07595ecc84f07aa45d765a3eae1.zip FreeBSD-src-4ee6f0bd3bade07595ecc84f07aa45d765a3eae1.tar.gz | |
MFC r256707, r256708, r257291, r258358
Switch to use WBWA mappings for page tables on armv6, this is needed for SMP.
Fix PTE_SYNC() for PIPT L2 caches, using the virtual address wasn't so useful.
Use PTE_SYNC() for >= armv6
Spell cpu_l2cache_wb_range correctly.
Fix condition that determines PMAP_NEEDS_PTE_SYNC value for ARM
Use values of the correct defines to determine statement's result.
ARM_ARCH_ symbols are always defined, hence only values are relevant.
Avoid clearing EXEC permission bit when setting the page RW on ARMv6/v7
When emulating modified bit the executable attribute was cleared by
mistake when calling pmap_set_prot().
Diffstat (limited to 'sys/arm/include')
| -rw-r--r-- | sys/arm/include/pmap.h | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/sys/arm/include/pmap.h b/sys/arm/include/pmap.h index 9374ab5..d796c46 100644 --- a/sys/arm/include/pmap.h +++ b/sys/arm/include/pmap.h @@ -63,7 +63,7 @@ #endif #define PTE_CACHE 6 #define PTE_DEVICE 2 -#define PTE_PAGETABLE 4 +#define PTE_PAGETABLE 6 #else #define PTE_NOCACHE 1 #define PTE_CACHE 2 @@ -491,7 +491,7 @@ extern int pmap_needs_pte_sync; #if (ARM_MMU_SA1 == 1) && (ARM_NMMUS == 1) #define PMAP_NEEDS_PTE_SYNC 1 #define PMAP_INCLUDE_PTE_SYNC -#elif defined(CPU_XSCALE_81342) +#elif defined(CPU_XSCALE_81342) || ARM_ARCH_6 || ARM_ARCH_7A #define PMAP_NEEDS_PTE_SYNC 1 #define PMAP_INCLUDE_PTE_SYNC #elif (ARM_MMU_SA1 == 0) @@ -561,11 +561,18 @@ extern int pmap_needs_pte_sync; #define PMAP_INCLUDE_PTE_SYNC #endif +#ifdef ARM_L2_PIPT +#define _sync_l2(pte, size) cpu_l2cache_wb_range(vtophys(pte), size) +#else +#define _sync_l2(pte, size) cpu_l2cache_wb_range(pte, size) +#endif + #define PTE_SYNC(pte) \ do { \ if (PMAP_NEEDS_PTE_SYNC) { \ cpu_dcache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\ - cpu_l2cache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\ + cpu_drain_writebuf(); \ + _sync_l2((vm_offset_t)(pte), sizeof(pt_entry_t));\ } else \ cpu_drain_writebuf(); \ } while (/*CONSTCOND*/0) @@ -575,7 +582,8 @@ do { \ if (PMAP_NEEDS_PTE_SYNC) { \ cpu_dcache_wb_range((vm_offset_t)(pte), \ (cnt) << 2); /* * sizeof(pt_entry_t) */ \ - cpu_l2cache_wb_range((vm_offset_t)(pte), \ + cpu_drain_writebuf(); \ + _sync_l2((vm_offset_t)(pte), \ (cnt) << 2); /* * sizeof(pt_entry_t) */ \ } else \ cpu_drain_writebuf(); \ |
